JPH11121388A - Diffusion equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To formation of a wafer where in-plane sheet resistance distribution is more uniform, by arranging a plurality of gas discharge vents for discharging impurity gas from a diffusion equipment. SOLUTION: A plurality of gas discharge vents 7 are arranged on a quartz tube 2, impurity gas which is not yet reacted is discharged together with decomposition product gas and carrier gas to the outside of the quartz tube 2 from a discharge vent 8a of a gas discharge pipe 8 through the gas discharge vents 7. For example, eight gas discharge vents 7 are arranged on symmetrical positions by applying the normal passing the center of a wafer as a symmetry axis. The gas discharge pipe 8 is welded to the quartz tube 2. An annular part facing the quartz tube 2 is arranged on the position corresponding to the gas discharge vents 7, and the inner part is interconnected with the discharge vent 8a as a gas discharge path 8b. Since the impurity gas is dispersedly discharged from the periphery of the wafer, flow of the impurity gas is uniform in the quartz tube of a diffusion equipment, and sheet resistance distribution in a wafer surface can be made uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a diffusion device for diffusing impurities into a semiconductor substrate. In particular, the present invention is effective as a diffusion device for diffusing impurities into a polycrystalline silicon layer used as a wiring of a semiconductor device to have a predetermined electric conductivity.

[0002]

2. Description of the Related Art Doping a polycrystalline silicon layer with an impurity such as phosphorus to have a predetermined electric conductivity and use it as a wiring layer is one of the essential steps in the manufacture of a semiconductor device.

FIG. 1 is a longitudinal sectional view of a conventional vertical diffusion apparatus generally used, and FIG. 2 is a perspective view of a state where an electric furnace is removed. The impurity gas supplied together with the carrier gas from the impurity gas supply pipe 1 into the quartz tube 2 is decomposed on the surface of the wafer 5 supported on the wafer support 3 and heated by the electric furnace 4, and the dopant is contained in the wafer 5. To spread. Unreacted impurity gas, decomposition product gas and carrier gas are exhausted from a gas exhaust port 6 communicating with a negative pressure exhaust source not shown.

However, such a conventional apparatus has a problem that the sheet resistance in the surface of the wafer in which impurities are diffused is not uniform.

[0005] Using a conventional apparatus, phosphorus was diffused into a silicon wafer having a diameter of 6 inches. POC as impurity material
l ₃ is bubbled with N ₂ , and O ₂ and N
₂ was supplied from the impurity gas supply pipe 1 into the quartz pipe 2 to perform doping. Table 1 shows the doping conditions.

[0006]

Table 1 Impurity gas POCl ₃ flow rate 80 ± 30 ml / min Bubbling gas N ₂ flow rate 2 l / min Diluent gas O ₂ flow rate 240 sccm Diluent gas N ₂ flow rate 10 l / min Wafer temperature 875 ° C. Container pressure (exhaust pressure) −8 mmH ₂ O (relative to atmospheric pressure) Diffusion time 25 minutes The sheet resistance in the wafer surface thus diffused was measured using an automatic wafer mapping system VR-70 V2.32 manufactured by Kokusai Electric Co., Ltd. Then, measurement was performed at 121 locations. FIG. 3 shows the distribution of the sheet resistance in the wafer surface based on the measurement results. Contour lines are drawn for every 0.5% change in sheet resistance to show the distribution of sheet resistance. The maximum, minimum, average, median and standard deviation of the sheet resistance are shown below.

[0007]

[Table 2] Maximum value 30.9Ω / □ Minimum value 28.5Ω / □ Average value 29.68Ω / □ Median value 29.7Ω / □ Standard deviation 0.64Ω / □ (2.2%)

[0008]

FIG. 3 also shows the position of the exhaust port 6. It should be noted that the sheet resistance distribution in the wafer surface is high near the exhaust port, that is, doping is not sufficiently performed near the exhaust port. In consideration of this point, in the conventional apparatus, since the impurity gas is exhausted from only one exhaust port, the flow of the impurity gas is closer to the exhaust port than to other portions, for example, to the portion opposite to the wafer exhaust port. It is considered that the speed is higher, and therefore the residence time on the wafer is shorter, or the density of the impurity gas is relatively thinner than other portions. A silicon chip divided from a wafer having a non-uniform sheet resistance in-plane distribution has a problem that the electric resistance varies.

SUMMARY OF THE INVENTION An object of the present invention is to provide a diffusion apparatus which can solve such a conventional problem and can produce a wafer having a more uniform in-plane sheet resistance distribution.

[0010]

In order to achieve the above object, a diffusion device according to the present invention is a diffusion device for diffusing an impurity into a predetermined position of a semiconductor substrate, wherein an impurity gas is discharged from the diffusion device. And a plurality of gas outlets for the same.

Here, it is preferable that the plurality of outlets are arranged at symmetrical positions.

Further, it is particularly preferable that the position where the impurity is diffused is a polycrystalline silicon layer used as a wiring of a semiconductor device.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the diffusion device according to the present invention is as follows.
The configuration is the same as that of the conventional apparatus shown in FIG. 1 except for the configuration of the gas outlet for discharging the impurity gas. FIG. 4 is a perspective view of one embodiment of the present invention with the electric furnace removed, and FIG. 5 is a cross-sectional view taken along line AA of FIG. A plurality of gas outlets 7 are provided in the quartz tube 2, and unreacted impurity gas, decomposition product gas, and carrier gas (bubbling gas, dilution gas) are passed through the gas outlet 7 through the gas outlet 7. The gas is exhausted out of the quartz tube 2 from the exhaust port 8a. FIG.
In the figure, there is shown an example in which there are eight gas outlets 7, each of which is disposed symmetrically with respect to a normal passing through the center of the wafer as a symmetric axis. FIG. 6 is a longitudinal sectional view of the quartz tube in the vicinity of the gas discharge tube 8. However, the wafer support is not shown. The gas discharge pipe 8 is welded to the quartz pipe 2, and the annular portion facing the quartz pipe 2 is located at a position corresponding to the gas discharge port 7, and the inside thereof is formed as a gas discharge path 8 b as an exhaust port 8 a.
Is in communication with

In this apparatus, since the impurity gas is dispersed and exhausted from the periphery of the wafer, the flow of the impurity gas is uniform in the quartz tube of the diffusion device, and the sheet resistance distribution in the wafer surface is made uniform. Can be.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the diffusion apparatus shown in FIGS. 4 to 6, the gas outlet 7 is connected to two places on the diameter of the quartz tube 2, for example, two diameters connecting a position closest to the exhaust port 8a and a position farthest from the exhaust port 8a. By disposing the sheet resistance at two locations at the same distance as the exhaust port 8a of the quartz tube 2, the distribution of the sheet resistance in the wafer surface is improved. However, the number of gas outlets 7 is preferably large.

Using an apparatus having nine gas outlets, phosphorus was diffused into a silicon wafer having a diameter of 6 inches. The diffusion conditions are the same as the conditions shown in Table 1.

The sheet resistance in the plane of the silicon wafer into which phosphorus was diffused was measured at 121 points using an automatic wafer mapping system VR-70 V2.32 manufactured by Kokusai Electric Co., Ltd. The maximum, minimum, average, median and standard deviation of the sheet resistance are shown below.

[0018]

[Table 3] Maximum value 30.3Ω / □ Minimum value 29.5Ω / □ Average value 29.94Ω / □ Median value 29.9Ω / □ Standard deviation 0.15Ω / □ (0.5%) Figure 7 shows the measurement results. 0.5% change in sheet resistance based on
The contour line is drawn every time to show the distribution of the sheet resistance. In FIG. 7, the position of the gas outlet 7 is also indicated by an arrow. The small number of contour lines in FIG. 7 indicates that the change in sheet resistance is small and the slope is gentle.

The diffusion conditions of this embodiment and the conventional example are exactly the same. As is clear from the comparison between Table 2 and Table 3 or the comparison between FIG. 2 and FIG. 7, the in-plane distribution of the sheet resistance was significantly improved by using the diffusion device of the present invention. This is achieved by providing multiple gas outlets.
This is because the flow of the impurity gas in the diffusion device was made uniform. In FIG. 7, the number of gas outlets is nine, and the position is mirror-symmetrical with respect to a plane passing through the center of the wafer 5 and the center of the orientation flat 5a. If the gas outlets are provided and the arrangement of the gas outlets is symmetrical with respect to the center of the wafer, the distribution of the sheet resistance in the wafer surface becomes more uniform.

Therefore, if the diffusion device of this embodiment is used for doping a polycrystalline silicon layer for wiring, the resistance of the wiring of a large number of semiconductor devices divided from one wafer can be made uniform. The production yield of the semiconductor device can be improved.

In the above embodiment, an example has been shown in which the gas discharge port is provided in the quartz tube 2 and the gas discharge tube 8 is arranged on the outer periphery of the quartz tube 2. However, rather than providing a gas outlet in the quartz tube 2, it comprises an annular pipe disposed in the quartz tube and a straight pipe protruding out of the quartz tube, and a plurality of gas outlets are provided in the annular pipe. It is also possible to use the provided gas discharge pipe.

[0022]

As described above, when the diffusion apparatus of the present invention is used, the sheet resistance distribution in the obtained wafer surface is uniform, and therefore, the electric resistance of the semiconductor chip divided from such a wafer is reduced. Variation can be reduced. In particular, the present invention is effective for doping polycrystalline silicon used as a wiring of a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a conventional diffusion device.

FIG. 2 is a perspective view of a conventional diffusion apparatus with an electric furnace removed.

FIG. 3 is a diagram showing distribution of sheet resistance in a silicon wafer surface in which phosphorus is diffused by a conventional apparatus.

FIG. 4 is a perspective view of an embodiment of the diffusion apparatus according to the present invention, with an electric furnace removed.

FIG. 5 is a sectional view taken along line AA of FIG. 4;

FIG. 6 is a longitudinal sectional view of a quartz tube in the vicinity of a gas discharge tube 8.

FIG. 7 is a diagram showing a sheet resistance distribution in a silicon wafer surface in which phosphorus is diffused by the diffusion device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Impurity gas supply pipe 2 Quartz tube 3 Wafer support 4 Electric furnace 5 Wafer 6 Exhaust port 7 Gas exhaust port 8 Gas exhaust pipe 8a Exhaust port 8b Gas exhaust path

Claims (3)

[Claims] 1. A diffusion device for diffusing an impurity into a predetermined portion of a semiconductor substrate, the diffusion device having a plurality of gas outlets for discharging an impurity gas from the diffusion device. 2. The diffusion device according to claim 1, wherein the plurality of outlets are arranged at symmetric positions. 3. The diffusion device according to claim 1, wherein the predetermined portion is a polycrystalline silicon layer used as a wiring of a semiconductor device.