JPH11120767A - Semiconductor memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a circuit which can be simplified and in which operation speed can be increased by providing plural transfer gates receiving internal addresses in parallel, controlling ON/OFF of each transfer gate of an output switching unit in accordance with a selected address mode, and outputting plural internal addresses constituting an internal address set as a column selection signal. SOLUTION: An address signal A is inputted to a row address buffer 105 and a column address buffer 109. An output from the row address buffer 105 is inputted to a row decoder 102, a row line of a memory cell array 101 is selected by a decoding signal from the above. On the other hand, a column address inputted to the column address buffer 109 is applied to a counter/register 110 of the next stage. A signal SFi is outputted from the counter/register 110, and applied to an output switching circuit 106 of the next stage. The output switching circuit 106 is so-called a gate circuit of plural bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory circuit, and more particularly, to a semiconductor memory circuit having an addressing system in which an address signal wraps in synchronization with a clock and accesses a predetermined column.

[0002]

2. Description of the Related Art It is known that a synchronous DRAM (SDRAM) performs burst access to write / read data for a memory cell array in synchronization with a clock. The synchronous DRAM includes an addressing circuit having a counter configuration for performing a burst operation.

Prior to describing the addressing circuit, a portion for selecting a column address in an SDRAM will be briefly described as follows.

An address signal is applied to a counter / register having a binary counter configuration via a column address buffer to generate an internal address, for example, CA0, CA1, CA
2 is generated. The internal address is applied to a partial decoder and decoded, so that two sets of 4 bits × 2 are obtained. In each output set, the output sequence of 4 bits is switched. Thus, the column drive signals (CDRV0 to CDV3, CDRV4 to CDRV7)
Is obtained. These column drive signals CDRV are added to the main decoder together with other signals and decoded, and column selection is performed in the memory cell array based on a column selection signal as its output.

FIG. 8 shows counter circuits a to c for generating internal addresses CA0 to CA2 during the above-described column addressing operation. FIG. 9 shows a partial decoder PD and a switching circuit E which operate in response to those internal addresses.
X is shown.

First, in FIG. 8, in a counter circuit a, an address signal is supplied to A0IN via an address buffer.
And the internal address CA0 is output. The internal address CA0 as this output is applied to the next-stage counter circuit b. The signal A1IN from the address buffer is applied to the counter circuit b. Thereby, internal address signal CA1 is obtained in counter circuit b. In the counter circuit C, the same operation as described above is repeated to obtain the internal address signal CA2.

The internal address signals CA0 to CA2 obtained in this manner are applied to the partial decoder PD of FIG. 9. Before describing this, the counter circuit of FIG. 8 will be described in more detail.

FIG. 8 shows signals A0IN and A0 which are a conventional counter / register circuit composed of only a binary counter.
1IN and A2IN are outputs from the address buffer, and are clocked inverters C-INV80, 81 and 82.
Are entered respectively. These inverters 80-
The signal CLKT applied to the inverter 82 is generated during the tap cycle, and the signals A0IN are supplied to these inverters 80-82.
To A2IN and output to the nodes N80, 81 and 82, respectively.

As for the counter circuit a, the node N
80 is input to the clocked inverter C-INV83,
By the internal clock CLK, the internal column address CA
Output as 0. Clocked inverter C-INV8
6, the inverted signal N83 of the internal column address CA0 by INV89 is input, and the clocked inverter C-IN
The signal is output to the node N80 at the CLK timing opposite to that of V83. When the signal CLK is clocked, the internal column address CA0 performs an inversion operation every cycle.

As for the counter circuit b, the node N
81 is input to the clock inverter C-INV84 and output as an internal column address CA1 according to the internal clock CLK. The clocked inverter C-INV87 has a lower counter output CA0 and a counter output CA1.
, And outputs the exclusive OR to the node N81 at the CLK timing opposite to that of the clocked inverter C-INV84. From here on,
The internal column addresses CA2, CA3,... Are connected to form a counter. In the figure, there are three counter circuits a to c.

The internal address signals CA0 to CA2 are obtained by such counter circuits a to c.

The CA0 and CA1 of the internal address signals thus obtained are added to the NOR gate NOR as they are and inverted by the inverter INV in the two sets of partial decoders PD in FIG. Further, the internal address signal CA2 is supplied to one partial decoder P
In the NOR gate NOR of D, the data is inverted and added to the NOR gate NOR by the inverter INV in the other decoder PD. As a result, decoding is performed in each partial decoder PD, and a 4-bit decoded output is obtained. These 4-bit × 2 outputs are respectively applied to the next-stage switching circuit EX, output as column drive signals CDRV0 to CRV7, and the column selection lines are driven.

[0013] The column is selected as described above.
Addressing for a predetermined column in the SDRAM is performed as shown in FIG. Since this addressing is well known, a detailed description is omitted, but it is simply as follows. (1) When burst length = 8 (A3 and above are fixed by tap address)-Sequential mode: increment in A0, A1, A2 (tap 1: 1 → 2 → 3 → 4 → 5 → 6 → 7 → 0) • Interleave mode: When A0 = "0", increment in A0, A1, A2 (tap 1: 1 → 2 → 3 → 4 → 5 → 6 → 7 → 0) When A0 = “1” , A0, A1, A2 increment (Tap 1: 1 → 0 → 3 → 2 → 5 → 4 → 7 → 6) (2) When burst length = 4 (A2 and above are fixed by tap address) ・ Sequential mode : Increment in A0 and A1 • Interleave mode: Increment when A0 = "0" Decrement when "1" (3) When burst length = 2 (A1 and above are fixed by tap address)-Sequencer Mode: Increment in A0. Interleave mode: Increment in A0. The addressing operation is also performed by the output of FIG. 9 as described above, that is, as shown in FIG. That is, as can be seen from FIG. 7, it is necessary to change the carry stop position to the upper address according to the burst length, and it is necessary to enable two count operations of increment count and decrement count.

However, it is inevitable that the control of the counter circuit capable of performing the two count operations of the increment count and the decrement count is complicated. Further, when an addressing operation is performed by a decode circuit using an increment counter circuit, a delay occurs in memory access. Furthermore, conventional counters consisted of ordinary binary counters,
Even if the carry should not be carried, there is also a problem that carry to the upper address is automatically performed.

[0015]

As described above, conventionally,
Since the internal address is generated by the binary counter, in the case of a memory having a variable burst length and two addressing modes of sequential and interleaving, a carry-stop control circuit for an upper address which varies depending on the burst length, and increment and decrement A new operation control circuit for counting is required, so that the control circuit becomes complicated, and the time until memory access is increased is taken into consideration.
The present invention enables and simplifies each addressing operation,
It is an object of the present invention to provide a semiconductor memory circuit capable of achieving high speed.

[0016]

The semiconductor memory circuit of the present invention has one or more types of address selection modes, generates an internal address serially based on a head address, and accesses data based on the internal address. In a semiconductor memory circuit, an internal address generating circuit having a shift register structure for generating an internal address set including a plurality of bits of an internal address in response to an external address, and a transfer gate for selectively receiving and outputting the internal address An output switching circuit functioning as
An output switching unit for receiving the internal address set, the unit having a plurality of transfer gates for receiving the plurality of internal addresses constituting the internal address set in parallel; A switching control circuit that controls on and off of each of the transfer gates in the output switching unit with a timing, and outputs a plurality of internal addresses constituting the internal address set as a column selection signal addressed. , Are provided.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to describing an embodiment of the present invention, one of the features of the present invention will be described in comparison with a conventional one. Conventionally, tap addresses (A0, A1, A
2), the internal addresses (CA0, CA1, CA
In order to generate 2), a counter circuit in which a plurality of binary counters are connected in series has been used. On the other hand, in the present invention, the internal address is generated using the shift register without using the binary counter, and the speed is increased by the amount of the carry. Further, conventionally, the generated internal address (CA0-CA2)
Is decoded by a partial decoder to obtain a decoded signal. Thereafter, a switching circuit in the next stage switches the output to output a column drive signal (CD) to be applied to the main decoder.
RV0-3, 4-7). On the other hand, in the present invention, the function is included in another circuit without providing the switching circuit as a single-stage circuit, the single-stage circuit is omitted, and the path of the signal flow is shortened.

FIG. 6 is a block diagram showing a configuration of a main part of a DRAM according to the present invention. In this DRAM, an address signal A is input to a row address buffer 105 and a column address buffer 109. An output from the row address buffer 105 is input to a row decoder 102, and a row signal of the memory cell array 101 is selected by a decode signal from the output. On the other hand, the column address input to the column address buffer 109 is added to the counter / register 110 at the next stage. As will be described in detail later, the register here is substantially a shift register, and is configured to be able to shift in both forward and reverse directions. The counter / register 110 outputs a signal SFi.
(4 bits of SF0 to SF3 in the embodiment of FIG. 2) are output and applied to the output switching circuit 106 in the next stage. The output switching circuit 106 is a so-called multi-bit gate circuit, and has two circuits CIR1 and CRI2, each of which is a 4-bit parallel gate, for example. Output SFi from the counter / register 110
(4 bits) are added to two sets of circuits CIR1 and CIR2 (4 bits each) in the output switching circuit 106. These circuits CIR1 and CIR2 are alternately opened and closed, and the opened circuit CIR1 or CIR2 is opened.
Thus, the output SFi output from the counter / register at its own timing is output as the column drive signal CDRVi. For example, from the output switching circuit 106, the circuit C
8-bit column drive signals CDRV0 to CDRV7 are output with opening and closing of IR1 and CIR2.

In FIG. 6, only the column drive signal CDRVi has been described as the column addressing. However, a well-known partial decode signal applied to the main column decoder 104, for example, YA _j , Y
The description of B _k and YC ₁ is omitted. Here, as in the conventional case, the column drive signal CDRV
It goes without saying that these signals, in addition to i, are also applied to the main column decoder for decoding, and the column selection signal CSLi is output.

Next, each circuit in FIG. 6 will be described in more detail.

Since the column address buffer 109 is the same as the conventionally known one, the description is omitted here.

The counter / register 110 at the next stage is shown in FIG. The counter / register 110 has four registers RG0 to RG3, and is configured so that outputs (internal addresses SF0 to SF3) thereof can be shifted in a forward direction and a backward direction, respectively. Transfer gates 51 to 58 are provided to enable shifting in these two directions. In other words, simply, when the gates 51 to 54 are open and the gates 55 to 58 are closed, the shift is performed in the forward direction. When the gates 51 to 54 are closed and the gates 55 to 58 are open, the shift is performed in the reverse direction. Is performed.

Each of the registers RGi has the same structure, and the structure is shown in FIG. The operation of each register will be briefly described below with reference to the timing chart of FIG.

D which is the output of the register RGi-1 at the preceding stage
n-1 is input to the clocked inverter C-INV31, and is output to the node N31 by CLK = "L". This output becomes the input of the clocked inverter C-INV32, and is output to Dn which is the output of this register by CLK = "H".

The head data of the register at this time is created as follows. Signals A0IN and A1IN are the outputs of the address buffer, and are the lowest address of the column address and the next address. These signals A0IN, A1I
N is input to the NOR gate NOR34, and its output is input to the clocked inverter C-INV33.
CLK generated at the first cycle after / R signal input
T is fetched as the top address by T
To the first data of the register.

The shift register shown in FIG. 2 is constructed by connecting four registers RGi having such a configuration in series. The operation of the shift register will be described below.

FIG. 2 shows a shift register composed of four registers. The signals input to each register RGi are as follows.
It is a combination of the signals A0IN and A1IN and the inverted signals BA0IN and BA1IN of A0IN and A1IN. According to the above-mentioned head address, one of the four register outputs becomes “H”, and the other three register outputs become “L”.
, The data of “H” is shifted. When the addressing mode is sequential, the transfer gates 51, 52, 53, and 54 are turned on, and the transfer gates 51 to 58 between the registers RGi are turned on.
Data is shifted in the path of register 0 → register 1 → register 2 → register 3 → register 0. At this time, the register output SFi switches in the order of 0 → 1 → 2 → 3 → 0. If this is assumed to be a forward shift, the forward shift at the time of interleaving is also performed by the transfer gates 51, 52, 53, 5
4 conducts and performs data shift similarly.

On the other hand, in order to perform the reverse shift at the time of interleaving, the transfer gates 55, 56, 57, 5
8 conducts, register 3 → register 2 → register 1
Data shifts along the path from register 0 to register 3. At this time, the register output SFi becomes 3 → 2 → 1 → 0 →
It switches in the order of 3.

As described above, each of the other transfer gates is turned off at the time of another direction shift.
For example, if the start address is A1IN / A0IN = "0" /
If it is "1" and sequential, the transfer gate is 5
1, 52, 53 and 54 are conducting. At this time,
The start address is fetched by the signal CLKT generated at the start cycle, the node N31 of the register 1 goes to "L" level, and the nodes N31 of the registers 0, 2, and 3 go to "H".
Become a level. When CLK = “H” in the next cycle, the output of the register 1 outputs “H”, and the outputs of the registers 0, 2, and 3 output “L”. In addition, when output SF1 = “H”, SF
0, 2, 3 = "L" is output via the transfer gate. Next, when CLK = “L”, data is taken into the register via the clocked inverter C-INV31 of the next stage register. By sequentially clocking the CLK, the “H” data of SF1 is shifted from SF1 → 2 → 3 → 0.

For example, if the start address is A1IN / A0
If IN = "0" / "1" and the interleave mode, the transfer gates 55, 56, 57, 58 are conducting. The start address is fetched by the signal CLKT generated at the start cycle, the node N31 of the register 3 goes to "L" level, and the node N31 of the registers 0, 1, and 2 goes to "H".
Become a level. When CLK = “H” in the next cycle, the output of the register 3 outputs “H” and the outputs of the registers 0, 1, and 2 output “L”. And when the output SF1 is “H”, SF
0, 2, 3 = "L" is output via the transfer gate. Next, when CLK = “L”, data is taken into the register via the clocked inverter C-INV31 of the next stage register. By sequentially clocking the CLK, the “H” data of SF1 is shifted from SF1 → 0 → 3 → 2.

The output (internal address set) SF output from the counter / register 110 in FIG.
0 to 3 are added to the output switching circuit 106 as described above. Details of the output switching circuit 106 are shown in FIG.
As can be seen from FIG. 1, the circuit 106 has two sets of transfer circuits (output switching units) CIR1 and CIR2. Each of these transfer circuits CIRi,
Transfer circuit C having four parallel gates G0 to G3
The output SF0 of the counter / register 110 is applied to the input side of the first gate G0 of each of the IR1 and IR2.
Similarly, the output SFi of the counter / register 110 is applied to the second to fourth gates Gi of the transfer circuits CIR1 and CIR2.
Is added. Each gate Gi is turned on / off by application of control signals (internal column addresses) CA2 and 1CA2 from the output switching control circuit 111, and when turned on, column address signals CDRV0 to CDRV7 are output.

The output switching circuit 106 will be described in more detail.
Have transfer circuits CIR1 and CIR2, respectively. BCA2 is input to one transfer circuit CIR1 as a control signal, and CA2 is input to the other transfer circuit CIR2 as a control signal. When the internal column address CA2 = "L", B
CA2 = “H”, and the output of the shift register is applied to the column drive signals CDRV0 to CDRV3 through the transfer circuit CIR1.
Will be forwarded as Also, the internal column address CA2 =
When “H”, BCA2 = “L”, and the register 11
The output SFi of 0 is transferred as column drive signals CDRV4 to 7 via the transfer circuit CIR2.

The control signal CA2 / BCA2 is output from the output switching control circuit 111, and the level inversion timing is determined so that the addressing shown in the table of FIG. 7 is performed in the sequential mode and the interleave mode. .

The details of the output switching control circuit 111 are shown in FIG.
Is shown in As can be seen from FIG.
It has two circuits a and b. The circuit a is a circuit that operates in the sequential mode of the addressing mode. The circuit b is a circuit that operates at the time of interleaving. One of the circuits a and b operates according to the operation mode, and the output is held in the register 63 and output as the signal CA2.

The above operation will be described in more detail. That is,
5 includes a circuit a for controlling CA2 when the addressing mode is sequential, and a circuit for controlling CA2 when interleaving.
There is a circuit b for controlling A2. The transfer gates 61 and 62 are opened according to the addressing mode, and the data from the circuit a or the circuit b is input to the register 63 and output to the internal column address CA2 in the next cycle.

Attention is paid to the sequential circuit a.
The operation of the circuit a for controlling the signal CA2 at the time of the sequential operation is performed by setting the tap address A2 to the clocked inverter CI.
Taken from NV21 when CLKT = "H". And
In the clocked inverter C-INV22, FIG.
When the output SF3 of the register 3 in the middle is selected, the inverted data of the current CA2 is fetched, and it is output to the CA2 in the next cycle.

Attention is paid to the interleave circuit b. The operation of the circuit b for controlling the signal CA2 at the time of interleaving is such that the tap address A2 is taken into the shift registers 64, 65, 66 in synchronization with CLKT, initialized, and the tap address A taken by the clocked inverter C-INV22.
The inverted data of 2 is sequentially shifted by the shift register, and after four cycles, the head address CA2 is inverted.

The order of addressing thus performed is as shown in FIG. That is, it functions when the burst length is equal to or longer than 8, and at the burst length = 1, 2, 4, only the lower addresses A0 and A1 transition, so that the internal column address CA2 remains the tap address.

In the description of the above embodiment, an example in which the "H" level is shifted has been described. However, there is no problem even if this is an “L” level shift. Further, the circuit section that takes in the start address A0IN / A1IN has been described with the example of the NOR gate NOR and the clocked inverter C-INV configuration, but may be configured with the NAND gate NAND and the clocked inverter C-INV. Also, this is not the case if similar logic results can be obtained.

As described above, according to the present invention,
Even in the case of a memory having a variable burst length and a sequential interleaving addressing mode, it is possible to provide a semiconductor memory circuit which enables each addressing operation, and is simplified and speeded up. Further, according to the present invention, with the shift register configuration, wrapping of an address corresponding to a head address for memory access can be realized by a simplified circuit with a small delay. In addition, since the configuration is such that the shift can be performed in either the forward or reverse direction, the address wrap setting can be performed according to the address selection mode.

[0041]

According to the present invention, the generation of an internal address is carried out by a shift register instead of carrying out a carry using a plurality of binary counters.
The speed can be increased by the amount of carry, and the function is included in another circuit instead of switching the column drive signal with the output switching circuit, so the signal path is shortened,
Access can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a shift register in the addressing circuit of FIG. 6;

FIG. 2 is an example of a shift register including four registers of FIG. 3;

FIG. 3 is a circuit diagram of a register included in the shift register of FIG. 2;

FIG. 4 is an operation waveform of the circuit of FIG. 3;

FIG. 5 is a generation circuit of CA2 / BCA2 which is an output switching control circuit.

FIG. 6 is a block diagram showing a configuration of a main part of a DRAM according to the embodiment of the present invention.

FIG. 7 is a table showing the addressing order in each addressing mode and burst length.

FIG. 8 shows a binary counter circuit as a conventional circuit.

FIG. 9 shows a conventional addressing circuit using a binary counter.

Claims (3)

[Claims] A plurality of address selection modes;
In a semiconductor memory circuit that serially generates an internal address based on a start address and accesses data based on the internal address, a shift register that receives an external address and generates an internal address set including a plurality of bits of an internal address An internal address generation circuit having a configuration, and an output switching circuit functioning as a transfer gate for selectively receiving and outputting the internal address, comprising: an output switching unit for receiving the internal address set;
This unit has a plurality of transfer gates that receive a plurality of the internal addresses constituting the internal address set in parallel, and an output switching circuit. According to a selected address mode, each of the transfer gates in the output switching unit is A switching control circuit that controls on and off with a timing and outputs a plurality of internal addresses constituting the internal address set as a column selection signal addressed to the semiconductor memory circuit. 2. The apparatus has one or more address selection modes,
In a semiconductor memory circuit that serially generates an internal address based on a start address and accesses data based on the internal address, a shift register that receives an external address and generates an internal address set including a plurality of bits of an internal address An internal address generation circuit having a configuration, an output switching circuit functioning as a transfer gate for selectively receiving and outputting the internal address, comprising a plurality of output switching units each receiving the internal address set in parallel, Each of the units has a plurality of transfer gates receiving the plurality of internal addresses constituting the internal address set in parallel, and the transfer circuit in each of the output switching units according to a selected address mode. The gate A switching control circuit that controls the timing of turning on and off with a timing, and outputs a column selection signal having a bit number that is a multiple of the bit number of the internal address constituting the internal address set as addressed. A semiconductor memory circuit, characterized in that: 3. The internal address generating circuit according to claim 1, wherein a plurality of registers from a first stage to a last stage are connected in series via a first transfer gate to form a forward shift circuit. , The output of the register at the subsequent stage is connected to the input of the register at the previous stage via the second transfer gate to form a reverse shift circuit, and the output of each register is output to the outside node of the first transfer gate. 3. The semiconductor device according to claim 1, wherein the first and second transfer gates are connected to an end, and the first and second transfer gates are turned on and off during a forward shift, and are turned off and on during a reverse shift. 14. The semiconductor memory circuit according to claim 1.