JP3410942B2 - Semiconductor memory circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit having an addressing system in which an address signal is wrapped in synchronism with a clock and a predetermined column is accessed.

[0002]

2. Description of the Related Art It is known that a synchronous DRAM (SDRAM) performs burst access to write / read data to / from a memory cell array in synchronization with a clock. Since the synchronous DRAM performs a burst operation, it has an addressing circuit having a counter structure.

Prior to describing this addressing circuit, a portion for selecting a column address in the SDRAM will be briefly described as follows.

The address signal is applied to a counter / register having a binary counter structure via a column address buffer to generate an internal address, for example, CA0, CA1, CA.
2 is generated. The internal address is added to the partial decoder to be decoded and two sets of 4 bits × 2 outputs are obtained. In each output set, the 4-bit output sequence is switched. This causes column drive signals (CDRV0 to CDV3, CDRV4 to CDRV7
Is obtained. These column drive signals CDRV are added together with other signals to the main decoder and decoded, and column selection is performed in the memory cell array based on the column selection signal as the output.

FIG. 8 shows counter circuits a to c which generate internal addresses CA0 to CA2 during the column addressing operation described above, and FIG. 9 shows a partial decoder PD and a switching circuit E which operate by receiving these internal addresses.
X is shown.

First, in FIG. 8, in the counter circuit a, the address signal is passed through the address buffer to A0IN.
And the internal address CA0 is output. The internal address CA0 as this output is added to the counter circuit b at the next stage. The signal A1IN from the address buffer is added to the counter circuit b. As a result, the internal address signal CA1 is obtained in the counter circuit b. In the counter circuit C, the same operation as described above is repeated to obtain the internal address signal CA2.

The internal address signals CA0 to CA2 thus obtained are applied to the partial decoder PD of FIG. 9. Before explaining this, the counter circuit of FIG. 8 will be described in a little more detail.

FIG. 8 shows signals A0IN and A, which are conventional counter / register circuits composed only of binary counters.
1IN and A2IN are outputs from the address buffer, and are clocked inverters C-INV80, 81, 82.
Have been entered respectively. These inverters 80-
The signal CLKT applied to 82 is generated during the tap cycle, and signals A0IN to these inverters 80-82.
~ A2IN is taken in and output to the nodes N80, 81, 82, respectively.

As for the counter circuit a, the node N
80 is input to the clocked inverter C-INV83,
Internal column address CA by internal clock CLK
Output as 0. Clocked inverter C-INV8
An inverted signal N83 of the internal column address CA0 by INV89 is input to 6 and clocked inverter C-IN
The signal is output to the node N80 at the CLK timing that is in the opposite phase of V83. When the signal CLK is clocked, the internal column address CA0 is inverted every cycle.

As for the counter circuit b, the node N
81 inputs to the clock inverter C-INV84 and outputs it as the internal column address CA1 according to the internal clock CLK. The clocked inverter C-INV87 has a lower counter output CA0 and a counter output CA1.
An exclusive OR output N84 is connected to the node N81 and is output to the node N81 at a CLK timing in a phase opposite to that of the clocked inverter C-INV84. After this, in the same way,
The internal column addresses CA2, CA3 ... Are connected to form a counter. In the figure, there are three counter circuits a to c.

The internal address signals CA0 to CA2 are obtained by the counter circuits a to c.

Of the internal address signals thus obtained, CA0 and CA1 are applied to the NOR gate NOR as they are and after being inverted by the inverter INV in the two sets of partial decoders PD shown in FIG. Further, the internal address signal CA2 is supplied to one of the partial decoders P
In the NOR gate NOR of D, it is added as it is, and in the other decoder PD, it is inverted and added to the NOR gate NOR by the inverter INV. As a result, decoding is performed in each partial decoder PD, and a 4-bit decoded output is obtained. These 4 bits × 2 outputs are respectively applied to the switching circuit EX of the next stage, output as column drive signals CDRV0 to CRV7, and the column selection lines are driven.

The columns are selected as described above,
Addressing for a predetermined column in the SDRAM is performed as shown in FIG. Since this addressing is well known, a detailed description thereof will be omitted, but it is simply as follows. (1) When burst length = 8 (A3 and above are fixed by tap address) ・ Sequential mode: increment within A0, A1, A2 (tap 1: 1 → 2 → 3 → 4 → 5 → 6 → 7 → 0) -Interleave mode: When A0 = "0", increment in A0, A1, A2 (tap 1: 1 → 2 → 3 → 4 → 5 → 6 → 7 → 0) When A0 = "1" , A0, A1, Increment within A2 (Tap 1: 1 → 0 → 3 → 2 → 5 → 4 → 7 → 6) (2) When burst length = 4 (A2 and above is fixed by tap address) ・ Sequential mode : Increment within A0, A1 ・ Interleave mode: Increment when A0 = "0" Decrement when "1" (3) When burst length = 2 (A1 and above are fixed by tap address) ・ Sequencer Mode: Increment interleaving mode in the A0: As described above by the output of the increment Figure 9 in the A0, that is, the addressing operation as shown in FIG. 7 is performed. That is, as can be seen from FIG. 7, it is necessary to change the carry stop position to the upper address depending on the burst length, and it is necessary to enable two counting operations of increment count and decrement count.

However, a counter circuit capable of performing two counting operations, that is, an increment count and a decrement count, cannot avoid avoiding complicated control. In addition, when an address operation is performed by the decode circuit using the increment counter circuit, a memory access delay occurs. Furthermore, since the conventional counter was composed of a normal binary counter,
Even when the carry is not allowed, there is a problem that the carry to the higher address is automatically performed.

[0015]

As described above, in the past,
Since the internal address is generated by the binary counter, in the case of a memory with a variable burst length and two addressing modes of sequential and interleave, a carry stop control circuit to the upper address that changes depending on the burst length and increment and decrement This is done in consideration of the problems that a new counting operation control circuit is required, which complicates the control circuit and further increases the time until memory access.
The present invention enables and simplifies each addressing operation,
An object of the present invention is to provide a semiconductor memory circuit capable of achieving high speed.

[0016]

A semiconductor memory circuit of the present invention has one or more kinds of address selection modes, serially generates an internal address based on a head address, and accesses data based on the internal address. In a semiconductor memory circuit, an internal address generation circuit of a shift register configuration for receiving an external address and generating an internal address set consisting of an internal address of a plurality of bits, each having a plurality of registers from a first stage to a final stage. A forward shift circuit is configured by connecting in series via a first transfer gate, and the output of the register on the rear stage side of the two adjacent registers is input to the input of the register on the front stage side via the second transfer gate. Connected to form a backward shift circuit, the front of the output of each register An outer node of the first transfer gate is connected to an output terminal, and the first and second transfer gates are turned on and off during forward shift and off and on during reverse shift, respectively. An internal address generating circuit, and an output switching circuit that functions as a transfer gate that selectively outputs the internal address when receiving the internal address, and an output switching unit that receives the internal address set. It has a transfer gate for a plurality of bits for receiving the plurality of internal addresses forming the internal address set in parallel, and by receiving a control signal, the transfer get for the plurality of bits in the switching unit is turned on and off respectively. Output switching circuit and selected The transfer gate in the output switching unit is controlled to be turned on and off at a timing according to the address mode, and the output is switched as a column selection signal addressing a plurality of internal addresses forming the internal address set. And a switching control circuit that outputs the control signal and that is output from the circuit.
Furthermore, the semiconductor memory circuit of the present invention has one or more kinds of address selection modes, serially generates an internal address based on the head address, and accesses data based on the internal address. An internal address generation circuit of a shift register configuration for receiving an address and generating an internal address set consisting of an internal address of a plurality of bits, wherein a plurality of registers from a first stage to a final stage are serially connected via a first transfer gate. To form a forward shift circuit, and in the two adjacent registers, the output of the register on the rear stage side is connected to the input of the register on the front stage side via the second transfer gate to form the reverse shift circuit. The first at the output of each of the registers
Connect the outer node of the transfer gate to the output,
An internal address generation circuit configured to turn on and off the first and second transfer gates during forward shift and off and on during reverse shift, respectively; and the internal address. An output switching circuit that functions as a transfer gate that receives and selectively outputs the received internal address set, and includes a plurality of output switching units that receive the internal address sets in parallel, and each unit includes a plurality of output switching units that form the internal address set. Of a plurality of transfer gates for receiving the internal address in parallel, and by receiving a control signal, the transfer gates of the plurality of bits in the plurality of switching units are respectively turned on,
An internal address that constitutes the internal address set by controlling the turning on and off of each transfer gate in each output switching unit in accordance with the output switching circuit that is turned off and the selected address mode. A switching control circuit that causes the output switching circuit to output the column selection signal having a bit number that is a multiple of the number of bits, and that outputs the control signal;
Is configured to include.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Prior to describing an embodiment of the present invention, one of the features of the present invention will be described in comparison with a conventional one. Conventionally, tap addresses (A0, A1, A
2) based on the internal address (CA0, CA1, CA
In order to generate 2), a counter circuit in which a plurality of counters each having a binary counter configuration are connected in series has been used. On the other hand, in the present invention, the internal address is generated using the shift register without using the binary counter, and the speed is increased by the carry amount. Further, conventionally, the generated internal address (CA0 to CA2)
Is decoded by a partial decoder to obtain a decoded signal, which is then switched by the switching circuit in the next stage and output to be applied to the main decoder.
RV0-3, 4-7) was obtained. On the other hand, in the present invention, the switching circuit is not provided as a one-stage circuit, but its function is included in another circuit, the one-stage circuit is omitted, and the signal flow path is shortened.

FIG. 6 is a block diagram showing a structure of a main part of the DRAM according to the present invention. In this DRAM, the address signal A is input to the row address buffer 105 and the column address buffer 109. The output from the row address buffer 105 is input to the row decoder 102, and the row signal of the memory cell array 101 is selected by the decode signal from the row decoder 102. On the other hand, the column address input to the column address buffer 109 is added to the counter / register 110 at the next stage. As will be described later in detail, the register here is substantially a shift register, and is configured to be capable of shifting in both forward and reverse directions. This counter / register 110 outputs the signal SFi
(4 bits of SF0 to SF3 in the embodiment of FIG. 2) are output and added to the output switching circuit 106 of the next stage. The output switching circuit 106 is a so-called multi-bit gate circuit, and has two circuits CIR1 and CRI2, each of which is a 4-bit parallel gate. Output SFi from the counter / register 110
(4 bits) are added to the two sets of circuits CIR1 and CIR2 (4 bits each) in the output switching circuit 106. These circuits CIR1 and CIR2 are alternately opened and closed to open the circuit CIR1 or CIR2.
Therefore, the output SFi output from the counter / register at its own timing is output as the column drive signal CDRVi. For example, from the output switching circuit 106 to the circuit C
8-bit column drive signals CDRV0 to 7 are output according to opening / closing of IR1 and CIR2.

In FIG. 6, only the column drive signal CDRVi is described as the column addressing, but a known partial decode signal added to the main column decoder 104, for example, YA _j , Y.
The description of B _k and YC _l is omitted. Here, as in the conventional case, the column drive signal CDRV is also used.
In addition to i, these signals are also added to the main column decoder to be decoded, and the column selection signal CSLi is output.

Next, each circuit in FIG. 6 will be described in more detail.

Since the column address buffer 109 is the same as a well-known one in the related art, its explanation is omitted here.

The next stage counter / register 110 is shown in FIG. The counter / register 110 has four registers RG0 to RG3, and the outputs (internal addresses SF0 to SF3) of the counter / register 110 can be shifted forward and backward respectively. Transfer gates 51 to 58 are provided to enable the shifts in the two directions. That is, simply, when the gates 51 to 54 are opened and the gates 55 to 58 are closed, the shift is performed in the forward direction, and when the gates 51 to 54 are closed and the gates 55 to 58 are opened, the shift is performed in the reverse direction. Is done.

Each of the registers RGi has the same structure, and its structure is shown in FIG. The operation of each register will be briefly described below with reference to the timing chart of FIG.

The output D of the register RGi-1 in the preceding stage
n-1 inputs to the clocked inverter C-INV31 and outputs it to the node N31 by CLK = “L”. This output becomes the input of the clocked inverter C-INV 32, and is output to Dn which is the output of this register by CLK = “H”.

The head data of the register at this time is created as follows. The signals A0IN and A1IN are the output of the address buffer and are the lowest address and the next address of the column address. These signals A0IN and A1I
N is input to the NOR gate NOR34, and its output is input to the clocked inverter C-INV33, and W
Signal CLK generated in the first cycle after inputting / R signal
It is fetched as the start address by T, and the node N31
To the first data of the register.

The four registers RGi thus configured are connected in series to form the shift register shown in FIG. 2. The operation of the shift register will be described below.

FIG. 2 is a shift register consisting of four registers, and the signals input to each register RGi are
It is a combination of the signals A0IN and A1IN and the inverted signals BA0IN and BA1IN of A0IN and A1IN. The output of one of the four registers becomes "H" and the output of the other three registers becomes "L" by the above-mentioned start address.
As a result, the "H" data is shifted. In the transfer gates 51 to 58 between the respective registers RGi, the transfer gates 51, 52, 53 and 54 are conductive when the addressing mode is sequential,
Data is shifted in the route of register 0 → register 1 → register 2 → register 3 → register 0. At this time, the register output SFi switches in the order of 0 → 1 → 2 → 3 → 0. If this is a forward shift, the forward shift at the time of interleaving will also be performed by the transfer gates 51, 52, 53, 5
4 becomes conductive, and data shift is performed similarly.

On the other hand, in order to perform the reverse shift at the time of interleaving, the transfer gates 55, 56, 57 and 5 are used.
If 8 is turned on, register 3 → register 2 → register 1
→ Data is shifted in the route of register 0 → register 3. At this time, the register output SFi is 3 → 2 → 1 → 0 →
It changes in the order of 3.

As described above, the other transfer gates are made non-conductive during another direction shift.
For example, the start address is A1IN / A0IN = "0" /
If it is "1" and sequential, the transfer gate is 5
1, 52, 53, 54 are conducting. At this time,
The node N31 of the register 1 is brought to "L" level by taking in the leading address by the signal CLKT generated in the leading cycle, and the node N31 of the registers 0, 2, 3 is "H".
Become a level. When CLK = “H” in the next cycle, the output of the register 1 outputs “H” and the outputs of the registers 0, 2 and 3 output “L”. And the output SF1 = "H" causes SF
0, 2, 3 = “L” is output via the transfer gate. Next, with CLK = “L”, data is taken into the register via the clocked inverter C-INV31 of the next stage register. By sequentially clocking CLK, the "H" data of SF1 is shifted to SF1 → 2 → 3 → 0.

For example, the start address is now A1IN / A0
If IN = “0” / “1” and the interleave mode, the transfer gates 55, 56, 57 and 58 are conductive. The head address is fetched by the signal CLKT generated in the head cycle, the node N31 of the register 3 becomes "L" level, and the node N31 of the registers 0, 1 and 2 is "H".
Become a level. When CLK = “H” in the next cycle, the output of the register 3 outputs “H” and the outputs of the registers 0, 1 and 2 output “L”. And the output SF1 = "H", SF
0, 2, 3 = “L” is output via the transfer gate. Next, with CLK = “L”, data is taken into the register via the clocked inverter C-INV31 of the next stage register. By sequentially clocking CLK, the “H” data of SF1 is shifted in the order of SF1 → 0 → 3 → 2.

The output (internal address set) SF output from the counter / register 110 of FIG. 2 in this way
0 to 3 are added to the output switching circuit 106 as described above. Details of the output switching circuit 106 are shown in FIG.
As can be seen from FIG. 1, this circuit 106 has two sets of transfer circuits (output switching units) CIR1 and CIR2. Each of these transfer circuits CIRi,
The transfer circuit C has four parallel gates G0 to G3.
The output SF0 of the counter / register 110 is applied to the input side of the first gate G0 of each of IR1 and IR2.
Similarly, the output SFi of the counter / register 110 is applied to the second to fourth gates Gi of the transfer circuits CIR1 and CIR2.
Is added. Application of control signals (internal column addresses) CA2, 1CA2 from the output switching control circuit 111 turns on / off each gate Gi, and when turned on, column address signals CDRV0-7 are output.

The output switching circuit 106 will be described in more detail. The output signal SFi of the register 110 is output.
There are transfer circuits CIR1 and CIR2 which are respectively input. BCA2 is input to one transfer circuit CIR1 as a control signal, and CA2 is input to the other transfer circuit CIR2 as a control signal. B when the internal column address CA2 = "L"
CA2 becomes “H”, and the output of the shift register is transferred through the transfer circuit CIR1 to the column drive signals CDRV0 to CDRV3.
Be transferred as. Also, the internal column address CA2 =
When "H", BCA2 = "L", and the register 11
The output SFi of 0 is transferred as the column drive signals CDRV4 to CDRV7 through the transfer circuit CIR2.

The control signal CA2 / BCA2 is output from the output switching control circuit 111, and the timing of its level inversion is determined so that the addressing shown in the chart of FIG. 7 is performed in the sequential mode and the interleave mode. .

Details of the output switching control circuit 111 are shown in FIG.
Shown in. As can be seen from this FIG.
It has two circuits a and b. The circuit a is a circuit that operates in the sequential mode of the addressing modes. The circuit b is a circuit that operates during interleaving. One of the circuits a and b operates according to the operation mode, the output is held in the register 63, and is output as the signal CA2.

The above operation will be described in more detail. That is,
The circuit of FIG. 5 includes a circuit a for controlling CA2 when the addressing mode is sequential and a circuit C for interleaving.
There is a circuit b that controls A2. In accordance with the addressing mode, each transfer gate 61, 62 opens and inputs the data from the circuit a or circuit b to the register 63 and outputs it to the internal column address CA2 in the next cycle.

Attention is paid to the sequential circuit a.
The operation of the circuit a for controlling the signal CA2 at the time of sequential operation is performed by setting the tap address A2 to the clocked inverter CI.
Capture from NV21 when CLKT = “H”. And
In the clocked inverter C-INV22, as shown in FIG.
When the output SF3 of the register 3 therein is selected, the inverted data of CA2 at the present time is fetched and output to CA2 in the next cycle.

Attention is paid to the interleave circuit b. The operation of the circuit b for controlling the signal CA2 during interleaving is performed by loading the tap address A2 into the shift registers 64, 65 and 66 in synchronization with CLKT, initializing the tap address A2, and tapping the tap address A loaded by the clocked inverter C-INV22.
The inverted data of 2 is sequentially shifted by the shift register, and CA4 of the head address is inverted after 4 cycles.

The addressing order performed by this is as shown in FIG. In other words, it functions when the burst length is 8 or more, and when the burst length is 1, 2, or 4, only the lower addresses A0 and A1 are transited, so that the internal column address CA2 remains the tap address.

In the description of the above embodiment, an example in which the "H" level is shifted has been described. However, there is no problem even if this is an "L" level shift. Further, the circuit section for fetching the head address A0IN / A1IN has been described with the example of the NOR gate NOR and the clocked inverter C-INV, but the NAND gate NOND and the clocked inverter C-INV may be used. Moreover, if the same logic result can be obtained, it is not limited to this.

As described in detail above, according to the present invention,
Even in the case of a memory having a variable burst length and a sequential interleaving addressing mode, it is possible to provide a semiconductor memory circuit which enables each addressing operation and is simplified and speeded up. Furthermore, according to the present invention, with the shift register configuration, the wrapping of the address corresponding to the leading address for memory access can be realized by a simplified circuit with a small delay. Further, since the applied configuration is capable of shifting in either the forward or reverse direction, it is possible to perform the address wrap setting according to the address selection mode.

[0041]

As described above, according to the present invention, the internal address is generated by the shift register instead of carrying the carry using a plurality of binary counters.
It is possible to increase the speed by the carry and further, instead of switching the column drive signal by the output switching circuit and performing the function in another circuit, the signal path is shortened,
It is possible to speed up access.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention applied to a shift register in the addressing circuit of FIG.

FIG. 2 shows an example of a shift register composed of four of the registers shown in FIG.

FIG. 3 is a circuit diagram of a register included in the shift register of FIG.

4 is an operation waveform of the circuit of FIG.

FIG. 5 is a generation circuit of CA2 / BCA2 which is an output switching control circuit.

FIG. 6 is a block diagram showing a configuration of a main part of a DRAM according to the embodiment of the present invention.

FIG. 7 is a table showing addressing order in each addressing mode and burst length.

FIG. 8 is a binary counter circuit as a conventional circuit.

FIG. 9 is a conventional addressing circuit using a binary counter.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Suematsu 1-25, Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa 1 Toshiba Microelectronics Stock Association (56) Reference JP-A-9-180443 (JP, A) Kaihei 10-188566 (JP, A) JP 4-184791 (JP, A) JP 8-147964 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11 / 407

Claims (2)

(57) [Claims] 1. A method having one or more types of address selection modes,
In a semiconductor memory circuit that serially generates an internal address based on a start address and accesses data based on the internal address, a shift register that receives an address from the outside and generates an internal address set composed of an internal address of multiple bits configuration, an internal address generating circuit, end of the first stage
First transfer of multiple registers up to each stage
Connected in series through the gate to form a forward shift circuit
In the two adjacent registers,
Side register output to the previous stage register input respectively
Connection via the second transfer gate
The output circuit of each register
Connect the outer node of the first transfer gate to the output
The first and second transfer gates in the forward direction.
When shifting, they are turned on and off respectively, and the reverse direction
Turned off and on when switching
An internal address generating circuit, and an output switching circuit functioning as a transfer gate for selectively receiving and outputting the internal address, the output switching unit receiving the internal address set,
This unit has a plurality of bits of transfer gates that receive the plurality of internal addresses forming the internal address set in parallel and receives a control signal.
Therefore, the switches for the plurality of bits in the switching unit
On lance fur target respectively, Ru is turned off, the output switching circuit, according to the selected address mode, said ON the transfer gates in the output switching unit controls timed off, the internal address Output from the output switching circuit as a column selection signal that addresses a plurality of internal addresses that make up the set.
And a switching control circuit for outputting the control signal , the semiconductor memory circuit. 2. Having at least one address selection mode,
In a semiconductor memory circuit that serially generates an internal address based on a start address and accesses data based on the internal address, a shift register that receives an address from the outside and generates an internal address set composed of an internal address of multiple bits The internal address generation circuit of the configuration,
First transfer of multiple registers up to each stage
Connected in series through the gate to form a forward shift circuit
In the two adjacent registers,
Side register output to the previous stage register input respectively
Connection via the second transfer gate
The output circuit of each register
Connect the outer node of the first transfer gate to the output
The first and second transfer gates in the forward direction.
When shifting, they are turned on and off respectively, and the reverse direction
Turned off and on when switching
An internal address generating circuit, and an output switching circuit that functions as a transfer gate that selectively outputs the internal address when receiving the internal address, and a plurality of output switching units that respectively receive the internal address set in parallel. a, the units will have a plurality of transfer gates for receiving a plurality of said internal addresses to configure said internal address set in parallel, the control
By receiving a signal, the switching units are
Each of the transfer gates for the above multiple bits
Depending on the output switching circuit that is turned on and off and the selected address mode, on / off of each transfer gate in each output switching unit is controlled at a timing to configure the internal address set. Addressing a column select signal with a bit number that is multiple times the bit number of the internal address
Output the control signal to be output from the output switching circuit
And a switching control circuit , the semiconductor memory circuit.