JPH11119750A - Driving circuit of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the necessary area of an integrated circuit with a simple circuit structure, and to realize a highly accurate output, a high-speed drive, and a low power consumption at the same time, by using a source follower action of MOS transistor for a driver of liquid crystal display device. SOLUTION: Switches SW3, 4 are turned on and off at a time t0, and enter a pre-charge mode. As the result, an output voltage Vout rises up to a voltage E2 to make SW1, 2 on and off, respectively. At a time t1, the SW1, 2 are turned on and off. As the result, the output voltage Vout changes into a voltage which is shifted from a bias voltage Vin only by a threshold voltage Vthp1 (<0) of a transistor 1 by an operation of the transistor 1. At a time t2, the switches SW 3, 4 are made on and off, respectively. In this state, since a transistor 2 operates as a source follower, the output voltage Vout changes into a voltage which is shifted from a bias voltage V1 for the gate of the transistor 2 only by the threshold voltage Vthp2 (<0) of the transistor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display (LC).
The present invention relates to a drive circuit of D), and more particularly, to an improvement of a driver (buffer) section which is an output stage of a drive circuit of a liquid crystal display device.

[0002]

2. Description of the Related Art Liquid crystal display devices are used for various devices including portable terminals such as portable devices and notebook computers because of their features of being thin, lightweight and low power. Among them, the demand for a liquid crystal display device using an active matrix driving method is increasing due to features such as high-speed response, high definition display, and high gradation display.

In general, a display portion of a liquid crystal display device using an active matrix driving method includes a semiconductor substrate on which transparent pixel electrodes and thin film transistors (TFTs) are arranged,
It consists of a counter substrate having one transparent electrode formed on the entire surface and a structure in which liquid crystal is sealed between the two substrates so as to face each other. An image is displayed by applying a voltage and changing the transmittance of the liquid crystal by the potential difference between each pixel electrode and the counter substrate electrode.

On the semiconductor substrate, a data line for transmitting a gradation voltage to be applied to each pixel electrode and a scanning line for transmitting a switching control signal (scanning signal) for the TFT are wired. A pulse-like scanning signal is sent to each scanning line from the scanning line driving circuit, and when the scanning signal applied to the scanning line is at a high level, the TFT connected to the scanning line from the data line driving circuit.
Are turned on, and the gradation voltage sent to the data line at that time is applied to the pixel electrode via the turned-on TFT. When the scanning signal goes low and the TFT changes to the off state, the potential difference between the pixel electrode and the counter substrate electrode is maintained until the next gradation voltage is applied to the pixel electrode. Then, by sequentially transmitting a scanning signal to each scanning line, a predetermined gradation voltage is applied to all the pixel electrodes, and an image can be displayed by rewriting the gradation voltage in a frame cycle.

As described above, since the liquid crystal display device must write a gradation voltage corresponding to an image to each pixel electrode via the data line, the data line drive circuit requires high performance. Further, the data line driving circuit must drive a large capacitive load including not only the liquid crystal capacitance of one pixel but also wiring resistance and wiring capacitance. In order to perform high-precision display and multi-gradation display, it is necessary to drive large-capacity data lines at high voltage accuracy and at high speed, and various data line drive circuits have been developed to satisfy this demand. . Among them, a drive circuit using an operational amplifier in a driver (buffer) unit has enabled high-precision output and high-speed drive. A typical circuit example is shown in FIG.
o et al. , "A 6-bit Digital
DataPrinter for Color TF
T-LCDs ", SID95 Digest, pp. 2
57-260, 1995).

In FIG. 43, a driving circuit of a liquid crystal display device for driving a data line includes a gradation voltage generator 101,
It comprises a decoder 102 and a driver 103 connected to the data line DL. FIG. 43 is a configuration diagram for one data line. The data line DL is connected to a liquid crystal cell via a TFT. The gradation voltage generator 101 includes resistors R1, R2,
─, R64 are connected in series, and a gradation voltage is generated by voltage division. Also, the decoder 102 outputs the video data signals D0, D
1, the grayscale voltage is selected according to D6, and the driver 10
3 is supplied with a gradation voltage.

In FIG. 43, a driver 103 is constituted by an operational amplifier, amplifies current of a gray scale voltage selected by a decoder 102, and outputs the amplified voltage to a data line DL. Since the operational amplifier has a high current supply capability, it can drive the data line DL having a large capacity at high speed. Further, even if the threshold voltage of the transistor in the operational amplifier slightly fluctuates, the variation in the output voltage _Vout of the operational amplifier is relatively small, and a highly accurate output voltage _Vout can be obtained.

[0008]

However, in the above-described drive circuit of the conventional liquid crystal display device, when the data line drive circuit for driving a large number of data lines is constituted by a single integrated circuit, the number of data lines is reduced. The required number of operational amplifiers is required. Since a high-precision operational amplifier is composed of a large number of elements, if a large number of operational amplifiers are used, the required area of the integrated circuit increases, and as a result, there is a problem that the manufacturing cost increases. In addition, since it is necessary to constantly supply a current inside the operational amplifier, there is a problem that power consumption increases.

Accordingly, an object of the present invention is to reduce the manufacturing cost and power consumption of a driving circuit of a liquid crystal display device.

[0010]

According to the present invention, there is provided a driving circuit for a liquid crystal display device which receives an input voltage and drives a data line with an output voltage.
A first MOS transistor having a power supply terminal, an input terminal for receiving an input voltage, an output terminal for outputting an output voltage, a drain and a gate connected to the first MOS transistor, and a source connected to the output terminal; A second MOS transistor having the same voltage as the first MOS transistor and having the same conductivity type as the first MOS transistor; and a first MOS transistor connected between the input terminal and the source of the first MOS transistor. Switch, first power supply terminal and first MOS
A second switch connected between the drain (gate) of the transistor, a third switch connected between the first power supply terminal and the drain of the second MOS transistor, and a second power supply terminal And a fourth terminal connected between the
Switch. Thereby, the first and second switches are controlled to bias the gate voltage of the second MOS transistor to a voltage shifted from the input voltage by the threshold voltage of the first MOS transistor. 4 to operate the second MOS transistor as a source follower, and output a voltage shifted from the gate voltage of the second MOS transistor by the threshold voltage of the second MOS transistor to the output terminal as an output voltage. It is intended to be.

That is, by utilizing the source follower operation of the MOS transistor for the driver (buffer) of the driving circuit of the liquid crystal display device, the required area of the integrated circuit can be reduced with a simple circuit configuration, and at the same time, high precision output and high speed driving can be achieved. And achieve low power consumption.

[0012]

FIG. 1 is a circuit diagram showing a first embodiment of a driver of a drive circuit of a liquid crystal display device according to the present invention. In FIG. 1, two P-channel MOS transistors 1 and 2 having a common gate electrode are provided.

The input voltage V _in is connected via a switch SW1 to the source of the transistor 1, the voltage drain and gate of the transistor 1 via the switch SW2 E1
Is connected to the power supply terminal T1 of the power supply.

The output voltage V _out is taken out from the source of the transistor 2 and outputted to the data line DL. The source of the transistor 2 is connected to the voltage E2 (>
E1) is connected to the power supply terminal T2, and the drain of the transistor 2 is connected to the terminal T1 via the switch SW4.

The operation of the driver shown in FIG. 1 will be described with reference to FIG. FIG. 2 shows one data output period. First, at time t0, the switches SW3 and SW4 are turned on and off, respectively, and enter the precharge mode ((C) and (D) in FIG. 2). As a result, the output voltage V _out rises to the voltage E2 ((E) in FIG. 2). In this state, switches SW1, SW2 are respectively turned off, since it is turned on, the bias voltage V ₁ of the gate of the transistor 1 is V ₁ = E1 _(1).

Next, at time t1, the switches SW1, S
W2 is turned on and off, respectively (FIGS. 2A and 2B). As a result, by the action of the transistor 1, the bias voltages V ₁ changes from the input voltage V _in to the threshold voltage V _thp1 (<0) shifted by the voltage of the transistor 1. That is, the bias voltage V ₁ is as follows: V ₁ = V _in + V _thp1 (2)

Next, at time t2, the switches SW3, S
W4 is turned off and on, respectively ((C) in FIG. 2,
(D)), the precharge mode ends. In this state, since the transistor 2 acts as a source follower, the output voltage V _out is more than the threshold voltage V _{1 of the} transistor 2 from the bias voltage V ₁ of the gate of the transistor 2.
_The voltage changes by _thp2 (<0). That is, the output voltage V _out is as follows: V _out = V ₁ −V _thp2 = V _in + V _thp1 −V _thp2 (3) If V _thp1 ≒ V _thp2 , (3)
The equation is: V _out outV _in (4), and the output voltage V _out is approximately equal to the input voltage V _in . In the actual LSILSI manufacturing process, the MO
Although the threshold voltage of the S transistor may have some variation, the transistors 1, 2
_Are formed close to each other and of the same size, V _thp1
≒ V _thp2 can be realized relatively easily.

[0018] Thus, in the first embodiment of the present invention, the output voltage V _out can equal to the input voltage V _in the data line DL at a higher current supply capability by the transistor 2 to operate as a source follower Can be driven.

FIG. 3 is a circuit diagram showing a modification of the driver shown in FIG. In FIG. 3, the switch SW4 of FIG. 1 is provided between the switch SW3 and the source of the transistor 2, and the output voltage V _out is changed by the switches SW3 and SW4.
It is taken out from the connection terminal. In this case, the switch S
W4 is constituted by a CMOS switch.

The operation of the driver shown in FIG. 3 will be described with reference to FIG. FIG. 4 shows one data output period.

First, at time t0, the switches SW3,
SW4 is turned on and off, respectively, and enters a precharge mode ((C) and (D) in FIG. 4). As a result, the output voltage V _out rises to the voltage E2 ((E) in FIG. 4). In this state, the switches SW1, SW2
Are turned off and on, respectively, so that the bias voltage V ₁ of the gates of the transistors 1 and 2 is V ₁ = E1 (5).

Next, at time t1, the switches SW1, S
W2 is turned on and off, respectively (FIGS. 4A and 4B). As a result, the bias voltage V ₁ becomes V ₁ = V _in + V _thp1 (6) due to the operation of the transistor 1.

Next, at time t2, the switches SW3 and S
W4 is turned off and on, respectively, and the precharge mode ends. In this state, the transistor 2 acts as a source follower, but the bias voltage V ₁ increases by α due to the gate-source capacitance coupling of the transistor 2. As a result, the output voltage V _out is as follows: V _out = V ₁ + α−V _thp2 = V _in + V _thp1 −V _thp2 + α ≒ V _in + α (7) Here, α> 0.

Here, the difference between the operation of FIGS. 1 and 3 will be described. In FIG. 1, when the switch SW4 is turned on at time t2, the drain of the transistor 2 is connected to the power supply terminal T1, so that the drain voltage of the transistor 2 drops sharply to E1. However, since immediately the charge through the transistor 1 is supplied to the gate of the transistor 1 by the input voltage V _in, without bias voltages V ₁ is vary little, (2) the voltage represented by the formula (V _in + V _thp1) Is stably maintained. Therefore, the driver 1 may output equal to the input voltage V _in the output voltage V _out.

On the other hand, in FIG. 3, when the switch SW4 is turned on at time t2, the source voltage of the transistor 2 rises rapidly because the source of the transistor 2 is connected to the data line DL precharged to the voltage E2. I do. At this time, the bias voltage V ₁ also slightly increases due to the gate-source coupling of the transistor 2. However, the transistor 1 when a bias voltage V ₁ is increased so turned off, the bias voltages V ₁ does not return to the original value. For this reason,
When the transistor 2 acts as a source follower, the output voltage V _out increases by variation α bias voltage than the input voltage V _in.

Thus, in the driver of FIG.
An output voltage V _out with higher accuracy can be obtained than the driver shown in FIG.

In FIGS. 1 and 3, the voltage condition for operating the transistor 1 is as follows: V _in ≧ E 1 −V _thp1 (8) Therefore, the output voltage V when V _out ≒ V _in is satisfied.
_out is a _{E2 ≧ V out ≧ E1-V} thp1 (9).

Another operation of the driver shown in FIG. 1 will be described with reference to FIG. FIG. 5 shows two data output periods, in which the dot inversion driving method is executed. In the dot inversion driving method, the positive output and the negative output must be alternately output. Therefore, in FIG.
_in is a period in which a positive polarity output operation is performed when there between the power supply voltage E2 and the counter electrode voltage V _c, time t3~t6
Has a period negative polarity output operation is performed when the input voltage V _in 'is between the counter electrode voltage V _c and the power supply voltage E1.

The operation at time t0 to t3 is performed at time t0 to t3 in FIG.
This is the same as the operation at t3.

[0030] In time t3, the input voltage V _in the V _in '
Switch to. As shown in FIGS. 5C and 5D, since the switches SW3 and SW4 are both turned off, the precharge operation is not performed. As a result, the output voltage _Vout does not change, as shown in FIG. In this state, switches SW1, SW2 are respectively turned off, since it is turned on, is (in FIG. 5 (A), (B) ) bias voltages V ₁ of V ₁ = E1 (10).

Next, at time t4, the switches SW1, S
W2 is turned on and off, respectively (FIGS. 5A and 5B). As a result, the bias voltage V ₁ becomes V ₁ = V _in '+ V _thp1 (11) due to the operation of the transistor 1.

Next, at time t5, the switch SW4 is turned on (in FIG. 5 (D)), the transistor 2 acts as a source follower, the output voltage V _out is, V _out = V ₁ -V _thp2 = V _in '+ V _thp1 -V _thp2 (12) Here, if V _thp1 ≒ V _thp2 , (1
The expression 2) is as follows: V _out ≒ V _in ′ (13), and the output voltage V _out is substantially equal to the input voltage V _in ′.

Also in the dot inversion driving method shown in FIG. 5, the output voltage V _out can be made equal to the input voltage V _in (V _in '), and the transistor 2 operates as a source follower, so that the data line DL has a high current supply capability. Can be driven. Further, by performing the precharge only during the positive polarity output period, the power consumption accompanying the precharge can be suppressed, and the dot inversion drive can be easily performed.

FIG. 6 is a circuit diagram showing a second embodiment of the driver of the drive circuit of the liquid crystal display device according to the present invention.
In FIG. 6, two N-channel MOS transistors 1 'and 2' having a common gate electrode are provided.

The input voltage V _in is connected 'via the transistor 1' switch SW1 to the source of the transistor 1 'drain and gate of the switch SW2' is connected via a the power supply terminal T2 of the voltage E2. Output voltage V
_out is taken out from the source of the transistor 2 'and output to the data line DL. The source of the transistor 2 'is connected to the power supply terminal T1 of the voltage E1 (<E2) via the switch SW3', and the drain of the transistor 2 'is connected to the terminal T2 via the switch SW4'.

The operation of the driver driving circuit of FIG. 6 will be described with reference to FIG. FIG. 7 shows one data output period.

First, at time t0, switch SW3,
SW4 is turned on and off, respectively, and enters the precharge mode ((C) and (D) in FIG. 7). As a result, the output voltage _Vout decreases to the voltage E1 ((E) in FIG. 7). In this state, the switches SW1 ', SW1
Since 2 ′ is turned off and on, respectively, the bias voltage V ₂ of the gates of the transistors 1 ′ and 2 ′ is V ₂ = E2 (14).

Next, at time t1, the switches SW1 ',
SW2 'is turned on and off, respectively (FIGS. 7A and 7B). As a result, 'the action of the bias voltage V ₂ from the input voltage V _in the transistor 1' transistor 1 changes the threshold _V thn1 (> 0) shifted by voltage. That is, the bias voltage V ₂ is as follows: V ₂ = V _in + V _thn1 (15)

Next, at time t2, the switches SW3 ',
SW4 'is turned off and on, respectively, and the precharge mode ends. In this state, since the transistor 2 'acts as a source follower, the output voltage V
_out it is changed to the threshold voltage _V thn2 (> 0) shifted by voltage of the transistor 2 'transistor 2 than the bias voltage V ₂ of the gate of the'. That is, the output voltage V _out is as follows: V _out = V ₂ −V _thn2 = V _in + V _tnn1 −V _thn2 (16) If V _thn1 ≒ V _thn2 here, (16)
The equation is: V _out outV _in (17), and the output voltage V _out is substantially equal to the input voltage V _in . In the actual LSILSI manufacturing process, the MO
Although the threshold voltage of the S transistor may have some variation, the transistors 1 ',
2 'are close to each other and if they are formed in the same size, V
_thn1 ≒ _Vthn2 can be realized relatively easily.

[0040] Thus, in the second embodiment of the present invention, the output voltage V _out can equal to the input voltage V _in, the data line at a higher current supply capability by the transistor 2 'operates as a source follower DL can be driven.

FIG. 8 is a circuit diagram showing a modification of the driver shown in FIG. In FIG. 8, the switch SW4 'in FIG. 6 is provided between the switch SW3' and the source of the transistor 2 ', and the output voltage _Vout is taken out from a connection terminal between the switch SW3' and the switch SW4 '. In this case, the switch SW4 'is constituted by a CMOS switch.

The operation of the driver shown in FIG. 8 will be described with reference to FIG. FIG. 9 also shows one data output period.

First, at time to, switch SW
3 ′ and SW4 ′ are turned on and off, respectively, and enter the precharge mode ((C) and (D) in FIG. 9). As a result, the output voltage V _out drops to the voltage E1 ((E) in FIG. 9). In this state, the switches SW1 ', SW1
Since 2 ′ is turned off and on, respectively, the bias voltage V ₂ of the gates of the transistors 1 ′ and 2 ′ is V ₂ = E2 (18).

Next, at time t1, the switches SW1 ',
SW2 'is turned on and off, respectively (FIGS. 9A and 9B). As a result, the bias voltage V ₂ becomes V ₂ = V _in + V _thn1 (19) due to the operation of the transistor 1 ′. Note that V _thn1 is the threshold voltage of the transistor 1 ′.

Next, at time t2, the switches SW3 ',
SW4 'is turned off and on, respectively, and the precharge mode ends. In this state, the transistor 2 ′ acts as a source follower, but the bias voltage V ₂
Decreases by β. As a result, the output voltage V _out is as follows: V _out = V ₂ −β−V _thn2 = V _in + V _thn1 −V _thn2 −β ≒ V _in −β (20) Here, β> 0.

Here, the difference between the operations of FIGS. 6 and 8 will be described. In FIG. 6, when the switch SW4 'is turned on at time t2, the drain of the transistor 2' is connected to the power supply terminal T.
2, the drain voltage of the transistor 2 'rises sharply to the voltage E2. At this time, the bias voltage V
₂ also rises slightly due to the capacitive coupling between the gate and drain of transistor 2 '. But since the charge on the gate of the 'immediately transistor 1 via a' transistor 1 is supplied by the input voltage V _in, without bias voltage V ₂ is to be changed little voltage represented by equation (15) (V _in +
V _thn1 ). Therefore, the driver of Figure 6 out be output equal to the input voltage V _in the output voltage V _out. On the other hand, in FIG.
When W4 'is turned on, the source of the transistor 2' is connected to the data line DL precharged to the voltage E1, so that the source voltage of the transistor 2 'drops sharply. At this time slightly decreased by capacitive coupling of the gate-source bias voltage V ₂ is also the transistor 2 '. However, since the bias voltage V ₂ drops transistor 1 'is turned off, the bias voltage V ₂ does not return to the original value.
When the the transistor 2 'acts as a source follower, the output voltage V _out is lowered by variation β of the bias voltage from the input voltage V _in.

As described above, in the driver shown in FIG.
An output voltage V _out with higher accuracy can be obtained than the driver shown in FIG.

6 and 8, the transistor 1 '
Is a condition of E2-V _thn1 ≧ V _in (21). Therefore, the output voltage V _out when V _out ≒ V _in is satisfied.
Is E2−V _thn1 ≧ V _out ≧ E1 (22).

Another operation of the driver shown in FIG. 6 will be described with reference to FIG. FIG. 10 shows two data output periods, and the dot inversion driving method is executed. Since the dot inversion drive method must output a negative polarity output and a positive polarity output alternately, in FIG. 10, time t0~t3 between the input voltage V _in the power supply voltage E1 and the counter electrode voltage V _c In a certain case, a period during which the negative polarity output operation is performed is set at time t3.
~t6 is a period positive output operation is performed when the input voltage V _in 'is between the counter electrode voltage V _c and the power supply voltage E2. The operation at time t0 to t3 is performed at time t0 to t3 in FIG.
Operation is the same as

[0050] At time t3, the input voltage V _in the V _in '
Switch to. As shown in FIGS. 10C and 10D, since the switches SW3 'and SW4' are both turned off, the precharge operation is not performed. As a result, the output voltage _Vout does not change, as shown in FIG. In this state, the switches SW1 'and SW2' are turned off and on, respectively (FIG. 10A,
(B)), the bias voltage V ₂ is V ₂ = E2 (23).

Next, at time t4, the switches SW1 ',
SW2 'is turned on and off, respectively (FIGS. 10A and 10B). As a result, the bias voltage V ₂ becomes V ₂ = V _in '+ V _thn1 (24) due to the operation of the transistor 1'.

Next, at time t5, the switch SW4 'is turned on ((D) in FIG. 10), and the transistor 2' operates as a source follower.
_out is V _out = V ₂ −V _thn2 = V _in '+ V _thn1 −V _thn2 (25) Therefore, if V _thn1 ≒ V _thn2 , equation (25) becomes V _out ≒ V _in ′ (26), and the output voltage V _out becomes equal to the input voltage V _in .

[0053] In the dot inversion driving method shown in FIG. 10, the output voltage V _out 'can equal, transistor 2 input voltage V _in (V _in)' data lines with high current supply capability by operates as a source follower DL can be driven. Furthermore, by performing the precharge only during the negative output period, the power consumption accompanying the precharge can be suppressed, and the dot inversion drive can be easily performed.

FIG. 11 is a circuit diagram showing a third embodiment of the driver according to the present invention. In FIG. 11, FIG.
And the driver of FIG. 6 are combined. However, in FIG. 11, the switch SW3 of FIG. 1 and the switch SW3 ′ of FIG.
The precharge operation by W3 and SW3 'is not performed.
The switches SW1, SW2, and SW4 perform the same operation as the switches SW1 ', SW2', and SW4 '. The output voltage V _out is taken out from the common source of the transistors 2 and 2 ′ and is outputted to the data line DL.

The operation of the driver shown in FIG. 11 will be described with reference to FIG. FIG. 12 shows two data output periods.
Time input voltage V _in the t0~t3 is input to the driver time t0'~t3 'the input voltage V _in' is input to the driver.

First, at time t0 (t0 '), switch SW4 (SW4') is turned off ((C) in FIG. 12). As a result, the output voltage V _out maintains the voltage level in the previous output period (D) (FIG. 12)). In this state, the switches SW1 (SW1 ′) and SW2 (SW
2 ′) are turned off and on, respectively (FIGS. 12A and 12B), and the bias voltage V ₁ of the gates of the transistors 1 and 2 is V ₁ = E1 (27). The bias voltage V ₂ of the transistors 1 ′ and 2 ′ is V ₂ = E2 (28).

Next, at time t1 (t1 '), the switches SW1 (SW1') and SW2 (SW2 ') are turned on and off, respectively (FIGS. 12A and 12B).
As a result, 'the action of the bias voltage V _1, V ₂ are respectively input voltage V _in (V _in' transistors 1,1 offset from) only the respective threshold voltages _{V thp1,} V thn1 transistors 1, 1 ' Voltage. That is,
The bias voltages V ₁ and V ₂ are V ₁ = V _in (V _in ') + V _thp1 (29) V ₂ = V _in (V _in ') + V _thn1 (30)

Next, at time t2 (t2 '), the switch SW4 (SW4') is turned on ((C) in FIG. 12). In this state, the transistor 2 or 2 'acts as a source follower. If the input voltage (V _in ) is lower than the output voltage in the previous output period, the transistor 2 acts as a source follower during the time t2 to t3, and the output voltage V _out is higher than the gate bias voltage V ₁ of the transistor 2 by the transistor. The threshold voltage V _thp2 changes to a voltage shifted by 2. That is, the output voltage V
_out is V _out = V ₁ −V _thp2 = V _in + V _thp1 −V _thp2 (31) Therefore, if V _thp1 ≒ V _thp2 , equation (31) becomes V _out ≒ V _in (32).

On the other hand, if the input voltage (V _in ') is higher than the output voltage in the previous output period, the time t2' to t3 '
, The transistor 2 ′ acts as a source follower, and the output voltage V _out is higher than the threshold voltage V 2 of the transistor 2 ′ by the gate bias voltage V _{2 of the} transistor 2 ′.
It changes to a voltage shifted by _thn2 . That is, the output voltage V
_out is V _out = V ₂ −V _thn2 = V _in '+ V _thn1 −V _thn2 (33) Therefore, if V _thn1 ≒ V _thn2 , equation (33) becomes V _out ≒ V _in ′ (34).

[0060] Thus, also in the third embodiment of the present invention, the output voltage V _out 'can equal, transistor 2 or second input voltage V _in (V _in)' by to operate as a source follower The data line DL can be driven with a high current supply capability. Further, in this embodiment, since it is not necessary to precharge the data line DL for each output period, power consumption can be reduced as compared with the first and second embodiments.

In FIG. 11, transistors 1, 1 '
The voltage condition for operating the 'a _{≧ E1-V thp1 (35)} , _{thus, V out ≒ V in (V} in E2-V thn1 ≧ V in (V in)' because it is),
The output voltage V _out satisfies E2-V _thn1 ≧ V _out ≧ E1-V _thp1 (36).

FIG. 13 is a circuit diagram showing a fourth embodiment of the driver according to the present invention. In FIG. 13, FIG.
1 is obtained by adding the switch SW3 of FIG. 1 and the switch SW3 ′ of FIG. 6 to one driver. Thereby, in the precharge mode, the switch SW3 or SW
3 'is turned on, and the output voltage _{Vout is changed} to E2 or E1.
To

FIG. 14 shows a specific example of the driver shown in FIG. That is, the switch SW3 is configured by a P-channel MOS transistor, and the switch SW3 ′ is configured by an N-channel MOS transistor. Also, switch S
W3 and SW3 'are controlled by the precharge signal PRE and the most significant bit signal D0 of the video data signal. FIG.
In (4), when (DO, PRE) = (0, 1),
The switch SW3 is turned on, and the output voltage V _out becomes the voltage E
2, when (DO, PRE) = (1, 1), the switch SW3 'is turned on, and the output voltage _Vout becomes the voltage E1.
Becomes If PRE = 0, the switch SW
3, SW3 'is turned off. FIG. 15 shows the relationship between the 3-bit video data signals D0, D1, and D2 and the corresponding eight gradation voltages V0, V1,.

The operation of the driver shown in FIG. 14 will be described with reference to FIG. FIG. 16 shows two data output periods. Time t
In 0~t3, the input voltage V _in the case of D0 = 0 (V0~
V3) is input to the driver, 'the input voltage V _in when the D0 = 1' time t0'~t3 (V4~V7) is input to the driver. Note that FIG. 16G shows that V _in =
Shows the case of V2 and V _in '= V5.

First, at time t0, the switches SW3 and SW3
SW3 'and SW4 (SW4') are turned on, off and on, respectively, and enter the precharge mode ((C), (D), (E) and (F) in FIG. 16). As a result, the output voltage V _out rises to the voltage E2 ((G) in FIG. 16). In this state, the switch SW1 (SW
1 ′) and SW2 (SW2 ′) are turned off and on, respectively ((A) and (B) in FIG. 16), so that the bias voltage V ₁ of the gates of the transistors 1 and 2 is V ₁ = an E1 (37), the bias voltage V ₂ is V ₂ = E2 (38).

Next, at time t1, the switch SW1 (S
W1 ′) and SW2 (SW2 ′) are turned on and off, respectively ((A) and (B) in FIG. 16). As a result, the bias voltages V ₁ ,
V ₂ is _derived from the input voltage Vin, respectively, by transistor 1,
The threshold voltages V _thp1 and V _{thn1 of} 1 ′ are shifted to voltages shifted by V _thn1 . That is, the bias voltages V ₁ and V ₂ are V ₁ = V _in + V _thp1 (39) V ₂ = V _in + V _thn1 (40)

Next, at time t2, the switches SW3, S
W4 (SW4 ') is turned off and on, respectively, and the precharge mode ends ((D) in FIG. 16,
(F)). In this state, since the transistor 2 acts as a source follower, the output voltage V _out changes to a voltage shifted from the bias voltage V ₁ of the gate of the transistor 2 by the threshold voltage V _{thp2 of the} transistor 2.
That is, the output voltage V _out is as follows: V _out = V ₁ −V _thp2 = V _in + V _thp1 −V _thp2 (41) Therefore, if V _thp1 ≒ V _thp2 , the expression (41) becomes V _out ≒ V _in (42).

Next, at time t0 ', switch SW3,
SW3′SW4 (SW4 ′) is turned off, on, and off, and enters the precharge mode ((C) in FIG.
(D), (E), (F)). As a result, the output voltage V _out
Drops to the voltage E1 (FIG. 16 (G)). In this state, the switches SW1 (SW1 ′) and SW2 (SW
2 ′) are off and on, respectively,
Of 6 (A), (B) ), the bias voltage V ₁ of the gate of the transistors 1 and 2 is V ₁ = E1 (43), the bias voltage V ₂ is V ₂ = E2 (44).

Next, at time t4, the switch SW1 (S
W1 ′) and SW2 (SW2 ′) are turned on and off, respectively ((A) and (B) in FIG. 16). As a result, the bias voltages V ₁ ,
V ₂ varies 'from transistor 1, 1' input voltage V _in each of the threshold voltages _{V thp1,} V thn1 shifted by voltage. That is, the bias voltages are V ₁ , and V ₂ is V ₁ = V _in '+ V _thp1 (45) V ₂ = V _in ' + V _thn1 (46)

Next, at time t2 ', the switch SW
3 ′ and SW4 (SW4 ′) are turned off and on, respectively, and the precharge mode ends ((E) and (F) in FIG. 16). In this state, since the transistor 2 'acts as a source follower, the output voltage V
_out is the bias voltage V ₂ of the gate of the transistor 2 ′
The voltage changes to a voltage shifted by the threshold voltage V _thn2 of the transistor 2 ′. That is, the output voltage V _out becomes _{V out = V 2 -V thn2 =} V in '+ V thn1 -V thn2 (47). Therefore, if V _thn1 ≒ V _thn2 , equation (47) becomes V _out ≒ V _in ′ (48).

[0071] Thus, also in the fourth embodiment of the present invention, the output voltage V _out 'can equal, transistor 2 or second input voltage V _in (V _in)' by to operate as a source follower The data line DL can be driven with a high current supply capability. In the driver shown in FIGS. 13 and 14, the voltage condition for operating the transistors 1 and 1 ′ is V _in (V0 to V3) ≧ E1−V _thp1 (49) E2−V _thn1 ≧ V _in ′ (V4 to V7) (50) Therefore, if V _out ≒ V _in (V _in '), (49)
From equation (50), the output voltage _Vout is E2 ≧ _Vout (V0−V3) ≧ E1- _Vthp1 (51) E2− _Vthn1 ≧ _Vout (V4−V7) ≧ E1 (52) . If the condition of V3 ≧ E1−V _thp1 (53) and the condition of E2−V _thn1 ≧ V4 (54) are satisfied, the expressions (51) and (52) are added together, and E2 ≧ V _out (V0 to V7) ≧ E1.

When the fourth embodiment of the present invention is compared with the above-described first and second embodiments, for example, in the first embodiment (FIG. 1), a voltage close to the voltage E1 is continuously changed. When outputting, the data line DL must be precharged to the voltage E2 for each output period. In the present embodiment, the precharge voltage is selected according to the output voltage, and when outputting a voltage close to the voltage E1, the voltage is selected. Since the battery is precharged to E1, the power consumption accompanying the precharge is small. Further, since the potential difference between the precharge voltage and the output voltage is small, the driving speed of the transistor 2 or 2 ′ by the source follower operation is increased. Similarly, when this embodiment is compared with the second embodiment, this embodiment consumes less power and has a higher driving speed. Also, comparing this embodiment with the above-described first to third embodiments with respect to the output voltage range,
In the first to third embodiments, the output voltage range is greater than the power supply voltage range by the transistor threshold voltages (V _thp1 , V _thn1 ).
However, in the present embodiment, the output voltage range can be the same as the power supply voltage range.

Switches SW3 and SW in FIG.
The operations of 3 ', SW4, and SW4' are summarized as shown in the table of FIG. That is, the time t2 (t
2 ′) to (t3 ′), the switches SW4 and SW
4 'are both turned on. At time t2 to t3, the transistor 2 operates as a source follower, and the output voltage V
_out becomes V _out = V _in + V _thp1 −V _thp2 (55), while from time t2 ′ to t3 ′, the transistor 2 ′ operates as a source follower, and the output voltage V _out becomes V _out = V _in + V _thn1 − V _thn2 (56).

In the description of the fourth embodiment, the threshold voltages V _thp1 and V _thp2 of the transistors 1 and 2 are set to V _thp1
≒ V _thp2, transistor 1 ', 2', but the threshold voltage _V thn1, V thn2 of was _V thn1 ≒ V thn2, actual LS
V _thp1 and V _thp2 or V _thp2
thn1 and V _thn2 may be different. And, for example, V
_{When thp1} < _Vthp2 and _Vthn1 > _Vthn2 , (55)
Equations (56) and (56) are respectively V _out <V _in and V _out > V _in , and the transistor 2 outputs the output voltage V _out to the input voltage V
acts to pull down the voltage lower than _in, the transistor 2 'acts to pull the voltage higher than the input voltage V _in the output voltage V _out. Time t2 (t2 ') to t3
At (t3 ′), since the switches SW4 and SW4 ′ are both on, the output voltage V _out becomes the precharge voltage E
When approaching the input voltage V _in from 2 or E1, the transistor 2, 2 'to operate the source follower together. As a result, a through current flows from the voltage E2 to the voltage E1 due to the operation of the transistors 2, 2 ′, which causes an increase in power consumption.

To prevent the above through current, FIG.
In FIG. 14, the switches SW4 and SW4 'are controlled as shown in FIGS. That is, as shown in FIG. 18A, the output voltage _Vout is changed to the voltage E2.
, The switches SW4 and SW4 'are turned on and off, respectively, from time t2 to t3, and only the transistor 2 is operated. On the other hand, as shown in FIG. 18B, when the output voltage _Vout is precharged to the voltage E1, the switches SW4 and SW4 'are turned off and on from time t2' to t3 ', respectively, and the transistor 2 'Just make it work. Note that the switch SW
3. The control of SW3 'is the same as that of FIG. Thereby, at time t2 (t2 ′) to t3 (t3 ′),
Since the transistors 2 and 2 'do not perform a source follower operation at the same time, a through current can be prevented.

In order to prevent the display contrast from lowering, the switches SW4 and SW4 'in FIG.
9 (A), (B), (C), and (D). In the following description, FIG. 15, FIG. 17, and FIG. 18 are also referred. 17 and 18, the switch S
One of W3 and SW3 'is turned on from time t0 (t0') to t2 (t2 '), and time t2 (t2') to t3 (t
In 3 '), both are off. For example, when a voltage equal to the voltage E2 or E1 is input to the driver, the same switch control is performed. However, time t2 (t2 ')
From t3 (t3 '), when the input voltage is equal to the precharge voltage, the source follower operation of the transistors 2, 2' is not normally performed. However, in an actual LSI manufacturing process, the threshold voltage V
_thp1 and V _thp2 is, or threshold voltage V _Thn1 and V _Thn2 transistor 1 'and 2' may differ respectively. In such a case, when the gray scale voltage V0 equal to the voltage E2 is input from time t2 (t2 ') to t3 (t3'), the output voltage slightly decreases from the voltage E2 or equals to the voltage E1. When the gray scale voltage V7 is input, the output voltage may slightly increase from the voltage E1.
In addition, during the precharge period from time t0 (t0 ′) to t2 (t2 ′), if writing of the grayscale voltage V0 or V7 from the data line to the pixel electrode via the TFT is not performed sufficiently quickly, From t2 (t2 ′) to t3 (t3 ′), the output voltage V _out slightly drops below the voltage E2 or slightly drops below the voltage E1 due to the movement of charges between the data line and the pixel electrode via the TFT. And may rise. If the output voltage range is narrowed for such reasons, the liquid crystal applied voltage range is narrowed, which may lead to a decrease in display contrast.

Therefore, as shown in FIG. 19A, when the video data signal is (D0, D1, D2) = (0, 0, 0) and the gradation voltage V0 is input to the driver, the time is t
The switch SW3 is turned on for one output period from 0 to t3, and the switches SW3 ′, SW4, and SW4 ′ are turned off. As a result, the output voltage _Vout is reliably maintained at the voltage E2 (= V0). Similarly, when the video data signal is (D0, D
When (1, D2) = (1, 1, 1) and the grayscale voltage V7 is input to the driver, the switch SW3 ′ is output over one output period from time t0 ′ to t3 ′ as shown in FIG.
Is turned on, and the switches SW3, SW4, and SW4 'are turned off. As a result, the output voltage V _out becomes the voltage E1 (= V
7) is reliably maintained. When the video data signal is D0 = 0
And (D0, D1, D2) ≠ (0,0,0),
FIG. 19C shows the control of each switch corresponding to the gradation voltages V1, V2, and V3. When the video data signal is D0 = 1
And (D0, D1, D2) ≠ (1,1,1),
FIG. 19D shows control of each switch corresponding to the gradation voltages V4, V5, and V6. FIGS. 19C and 19D are the same as FIGS. 18A and 18B. FIG. 19 (A)-
By controlling SW3, SW3 ', SW4, and SW4' shown in (D), the output voltage range can be kept at a maximum, and a decrease in display contrast can be prevented.

FIG. 20 shows a modification of the driver shown in FIG.
In FIG. 20, a capacitor 3 is inserted between the common gates of the transistors 1 and 2 and the power supply terminal T1 to substantially increase the gate capacitance of the transistors 1 and 2. Thus, improving the retention characteristic of the bias voltage V _1. Note that when the gate capacitance of the transistors 1 and 2 is small, the gate and the source (drain) of the transistors 1 and 2
Bias voltage V ₁ is varied due to a leakage current or the like between the accuracy of the output voltage V _out is lowered.

FIG. 21 shows a modification of the driver shown in FIG.
In FIG. 20, a capacitor 3 'is inserted between the common gate of the transistors 1' and 2 'and the power supply terminal T2 to substantially increase the gate capacitance of the transistors 1' and 2 '. Thus, improving the retention characteristic of the bias voltage V _2. When the gate capacitance of the transistors 1 ′ and 2 ′ is small, the gates of the transistors 1 ′ and 2 ′
Bias voltage V ₂ varies due to leakage current between source (drain), the accuracy of the output voltage V _out is lowered.

FIGS. 22 and 23 show modifications of the driver shown in FIGS. 11 and 13. 22 and 23, a capacitor 3 is inserted between the common gate of the transistors 1 and 2 and the power supply terminal T1 to substantially increase the gate capacitance of the transistors 1 and 2, thereby increasing the bias voltage V ₁ Improve the retention characteristics of On the other hand, the transistor 1 ', 2''Insert the transistor 1' capacitor 3 between the common gate and the power supply terminal T2, and made to increase the gate capacitance of 2 'in real-valued, thereby, the bias voltage V ₂ Improve the retention characteristics of

FIG. 24 shows a modification of the driver shown in FIG.
In FIG. 24, instead of the transistor 2 in FIG.
Two parallel P-channel MOS transistors 2A, 2A
B is provided. FIG. 25 shows a modification of the driver shown in FIG. In FIG. 25, two parallel P-channel MOS transistors 2′A and 2′B are provided instead of the transistor 2 ′ in FIG.

FIGS. 26 and 27 correspond to FIGS. 11 and 13, respectively.
Here is an example of changing the driver. 26 and 27, two parallel P-channel MOS transistors 2A and 2B are provided instead of the transistor 2, and two parallel N-channel MOS transistors 2'A and 2 'instead of the transistor 2'. 'B is provided.

24, 25, 26 and 27, transistors 2A and 2B (2'B and 2'B) have the same size and the same threshold voltage as transistor 2 (2 '). . That is, if the transistors 1, 2A, 2B (1 ', 2'A, 2'B) are formed close to each other and have the same size in the integrated circuit, the threshold voltages of the transistors 1 and 2A and 2B become substantially equal. 6, FIG. 11, FIG.
While maintaining the same output accuracy as in (3), it is possible to have twice the driving capability. Further, the required area in the integrated circuit is only increased to about 1.5 times the area occupied by the transistors 1 and 2 (1 ′, 2 ′). On the other hand, when doubling the channel width of the transistor 2 (2 ′) and doubling the driving capability, L
In order to minimize the variation in the threshold voltage of the transistors in the SI manufacturing process, the transistors need to have the same size.
The channel width of (1 ′) must also be doubled. In this case, the area occupied by the transistors 1 and 2 (1 ′, 2 ′) in the integrated circuit increases about twice. Therefore, rather than doubling the channel width of the transistor,
Transistor 2 of the same conductivity type and size as (2 ')
A, 2B (2′A, 2′B) can increase the driving capability of the driver with a minimum increase in required area.

In FIGS. 24, 25, 26, and 27, the same effect can be obtained even if the number of transistors sustained in parallel is three or more.

FIGS. 28, 29, 30, and 31 show modified examples of FIGS. 1, 6, 11, and 13, respectively. 28, 29, 30, and 31, the input voltage V
_A switch SW5 is provided between the input terminal of in and the output terminal of the output voltage _Vout.
When the threshold voltage shifts between (1 ′, 2 ′), the difference between the output voltage V _out and its optimum value (V _in ) is compensated.

For example, FIG. 32 shows the operation of the driver of FIG. 28 during one output period. The operation at times t0 to t3 is almost the same as in FIG. At time t2 to t3, when the transistor 2 acts as a source follower, the output voltage V _out becomes _{V out = V in + V thp1} -V thp2 ( see (3) below). In this case, the threshold values V _thp1 , V
If differences exist between _thp2, the output voltage V _out deviates by △ V than the optimum value, i.e. V _in. Next, at time t3, the switch SW4, SW5, respectively off, when turned on, even if large input impedance input voltage V _in, since ΔV is small, the output voltage V _out is equal to quickly input voltage V _in Become. Similarly, FIG. 28 and FIG.
9, FIG. 30, also in FIG. 31, by providing a switch SW5 between the output terminal of the input terminal and the output voltage V _out of _the input voltage V _in, thereby improving the accuracy of the output voltage V _out.

FIG. 33 is a circuit diagram showing a fifth embodiment of the driver of the drive circuit of the liquid crystal display device according to the present invention. In FIG. 33, a block 341A using the power supply voltages E1A and E2A as power supplies and a block 341B using the power supply voltages E1B and E2B as voltages are provided. These blocks 341A and 341B have the same configuration as the driver of FIG. 14 and use the same driving method as that of the fourth embodiment (see FIG. 16) to obtain the respective input voltages _VinA and _VinB.
And the output voltages V _outA and V _outB equal to. When the relationship between the video data signals used in the blocks 341A and 341B and the gradation voltages V0 to V7 is the same as in the fifth embodiment, when the most significant bits D0A and D0B of the video data signal are at low level, 341A
And any one of V0B to V3B is input to the block 341B. When D0A and D0B are at a high level, any one of V4A to V7A is input to the block 341A. One gradation voltage is applied to the block 341B by any one of V4B to V7B.
Gray voltages are input. Also, block 341A,
341B is connected to the data lines DL1 and DL2 via the switches 342, 343, 344 and 345, and the polarity signal P
The switches 342, 343, _344, and 345 are controlled by the OL, and the output voltage V _outA of the block 341A and the output voltage V _outB of the block _341B are switched to the data lines DL1 and DL2 and output. The voltages output to the data lines DL1 and DL2 are V _out1 and V _out 2, respectively. The power supply voltages of the blocks 341A and 341B are E1A and E1.
2A, E1B, and E2B, where E2A (= V0A)> E1A (= V7A) E2B (= V0B)> E1B (= V7B) E1A = E2B.

The operation of the driver shown in FIG. 33 will be described with reference to FIG. In FIG. 34, blocks 341A, 34
Although the control of each switch of 1B is not shown, the same control as in the fourth embodiment (see FIG. 16) is performed.

In the first output period, as shown in FIGS. 34B and 34C, D0A and D0B are each at the low level. As a result, blocks 341A, 3
Reference numerals 41B denote gradation voltages V0A to V3A and V0B
Any one of V3B is input. When the precharge signal PRE shown in (A) of FIG. 34 is at the high level, the output voltages V _outA and V _{outB become} the voltages E2A and E2A, respectively.
When E2B is precharged and the precharge signal PRE becomes low level, the output voltages _VoutA and _VoutB become equal to the input gradation voltage. As shown in FIG. 34 (D),
The polarity signal POL is at a high level. As a result, the switches 343 and 344 are turned on, and the output voltages V _outA and V _outB become the output voltage V _outB , respectively, as shown in FIG.
_out1 and _Vout2 are output.

In the second output period, as shown in FIGS. 34B and 34C, D0A is at a low level and D0A is at a low level.
OB is at a high level. As a result, block 341A
, One of the grayscale voltages V0A to V3A is input to the block 341B, and any one of the grayscale voltages V4B to V7B is input to the block 341B. When the precharge signal PRE shown in FIG. 34A is at the high level, the output voltages _VoutA and _VoutB are precharged to the voltages E2A and E1B, respectively. When the precharge signal PRE goes to the low level, the output voltage _VoutA becomes low. _outA and V _outB become equal to the input gray scale voltage. As shown in FIG. 34D, the polarity signal PO
L is at a low level. As a result, the switches 342, 3
45 is turned on, and the output voltages V _outB and V _outA become the output voltages V _out1 and V _out2 , respectively, as shown in FIG.
Is output as

In the third output period, D0A and D0B are at the high level as shown in FIGS. As a result, blocks 341A, 3
One of the gray scale voltages V4A to V7A and V4B to V7B is input to 41B. When the precharge signal PRE shown in FIG. 34A is at a high level, the output voltages _VoutA and _VoutB are precharged to voltages E1A and E1B, respectively. _outA and V _outB become equal to the input gray scale voltage. As shown in FIG. 34D, the polarity signal P
OL is at a high level. As a result, the switch 343,
344 is turned on, and as shown in FIG. 34 (E), the output voltages V _outA and V _outB become the output voltages V _out1 and V _out1 , respectively.
Output as _out2 .

In the fourth output period, as shown in FIGS. 34B and 34C, D0A is at a high level and D0A is at a high level.
OB is at a low level. As a result, block 341A
, One of the gray scale voltages V0A to V3B is input to the block 341B. When the precharge signal PRE shown in FIG. 34A is at the high level, the output voltages _VoutA and _VoutB are precharged to the voltages E1A and E2B, respectively. When the precharge signal PRE goes to the low level, the output voltage Vout _outA and V _outB become equal to the input gray scale voltage. As shown in FIG. 34D, the polarity signal PO
L is at a low level. As a result, the switches 342, 3
45 is turned on, and the output voltages V _outB and V _outA become the output voltages V _out1 and V _out2 , respectively, as shown in FIG.
Is output as

In the driver of FIG. 34, the output voltage range can be expanded by combining blocks 341A and 341B having different output voltage ranges. In addition, by using a plurality of power supply voltages (E1A, E2A, E1B, E2B), the potential difference for precharging in each of the blocks 341A and 341B is reduced, so that power consumption due to precharging can be suppressed and driving speed can be increased. . In FIG. 33, the polarity signal POL is inverted every output period, so that the output voltages V _out1 and V _out2 to adjacent data lines become the median value E1B and E2A of E1B and E2A.
Not only are the voltage polarities for 1A (= E2B) different from each other, but also the voltage polarities change for each output period. Therefore, the driver of FIG. 33 can be used for the dot inversion driving method.

Next, each of the above-described embodiments will be concretely implemented by simulation, and the effects of the present invention will be verified by analyzing output voltage and power consumption. In the simulation, one data line load corresponding to a video graphics array (VGA) panel having a diagonal angle of 25.4 cm (10 inches) is connected to the driver of the present invention, and the output voltage at the data line end and the power consumption of the driver are evaluated. .

FIG. 35 shows an equivalent circuit of one data line load used in the simulation. The driver is a driver in each embodiment of the present invention, and one data line load is an equivalent circuit including a liquid crystal capacitance, a wiring resistance, and a wiring capacitance of one pixel. The output period to one data line load is 35 μs in accordance with the driving cycle of the VGA panel. In the following simulations, evaluations are made on the case where the driver in FIGS. 1 and 14 is used as the driver in FIG. 35. However, the operation is the same for other drivers of the present invention, and the effect verification by the simulation is omitted.

FIG. 36 shows a circuit configuration when the driver of FIG. 1 is used as the driver of FIG. 36 are all configured using MOS transistors.
The ratio W / L of the channel length L and the channel width W of each MOS transistor is shown in FIG. The P-channel transistor 2 is designed to have a large channel width so that high-speed driving can be performed. The P-channel transistor 1 has the same element size as the P-channel transistor 2 in order to make the threshold voltage equal. The transistor size of the switch SW3 also has a large channel width in order to increase the precharge speed. Further, the N-channel transistor of the switch SW4 has a P
The element size is designed to have the same current supply capability as the channel transistor 2. Switches SW1, S
Since each transistor of W2 does not need a high current supply capability, the element size is made relatively small. Note that the switch SW
1, SW2, SW3, and SW4 perform the same control as in FIG. The voltages E1 and E2 are set to 0V and 5V, respectively.

FIG. 37 is a timing chart of the output voltage _{Vout at} the end of the data line as a result of performing the simulation by introducing the driver of FIG. 36 into the circuit of FIG.
FIG. 37 is a diagram showing a change in the output voltage V _{out in} one output period when the input voltage V _in = 1 V, and is an enlarged view of the vicinity of the voltage 1 V. In Figure 37, from the start of the output period, after 13μs including precharge period of 5μs is reached 10mV accuracy of the output voltage V _out is input voltage V _in, it is shown that can operate at high speed I have. The final output accuracy of the output voltage _Vout in one output period is about 2 mV, which is sufficient output output to drive one data line load of the VGA panel. Further, FIG. 37 shows the deviation of the threshold voltage of each P-channel transistor from the standard value by ΔVth, and ± 0.2 V
The output voltage _Vout at the time of the change is also shown.
Even if the threshold voltage of each P-channel transistor is changed, there is almost no variation in the output voltage _Vout , which indicates that the driver in FIG. 36 can output a stable voltage independent of the variation in the threshold voltage.

FIG. 38 is also a timing chart of the output voltage V _out (solid line) and the power consumed by the 5V power supply E2 (dotted line) as a result of simulation by introducing the driver of FIG. 36 into the circuit of FIG. Note that FIG. 38 shows a change in output voltage V _out and the power consumption of 2 output period in the case of a continuous V _in = 1V input voltage. In FIG. 38, since one data line load is precharged to 5 V every output period, power is consumed by charging and discharging at that time. When the output voltage is stabilized by the action of the source follower of the P-channel transistor 2 after the precharge, the power consumption during that time becomes almost zero. The power consumption during the entire output period is represented by an area surrounded by a power consumption curve (dotted line) and a zero power straight line (horizontal axis in the figure). The data line load shown in FIG. The power consumption per data line for driving is about 16 μW in the driver of FIG.

[0099] Furthermore, the conventional driver constituted by an operational amplifier as shown in (A) of FIG. 39 is introduced into the circuit of Figure 35, in the case of a continuous V _in = 1V input voltage simulation results of FIG. 39 It is shown in (B). In the operational amplifier, when the same voltage is continuously driven, the output voltage does not change. Therefore, although no charge / discharge power is generated for the data line, the waveform of the power consumption (dotted line) is about 40 μW on average. This is because the operational amplifier constantly supplies current inside the circuit. In the case of the operational amplifier shown in FIG.
μA DC current is constantly flowing inside the circuit. FIG.
The power consumption per data line when the data line load shown in FIG. 5 is constantly driven at an output voltage of 1 V is shown in FIG.
In the conventional driver of (A), the power is about 41 μW. In addition,
The driving condition of the output voltage of 1 V in the driver of FIG.
When the power consumption is large and the output voltage is higher than 1 V, the charging / discharging power of the precharge becomes small.
The power consumption per data line is even smaller than 16 μW. When driving a 10-inch VGA panel in this manner, the driver of FIG. 36 can reduce power consumption more than the operational amplifier of FIG. Also, this 10 inch VGA
With a small liquid crystal display device having a smaller data line load than the panel, the driver in FIG. 36 can further reduce the power consumption.

FIG. 40 shows the driver of FIG.
This is a circuit configuration in a case where the driver is used. All the drivers in FIG. 40 are configured using MOS transistors. The ratio W / L of the channel length L and the channel width W of each MOS transistor is shown in FIG. The switch SW1 (S
W1 '), SW2 (SW2'), SW3, SW3 ', SW
4 (SW4 ') performs the same control as in FIG. The voltages E1 and E2 are set to 0V and 5V, respectively.

FIG. 41 is a timing chart of the output voltage V _out (solid line) and the power consumed by the 5V power supply E2 (dotted line) as a result of simulation by introducing the driver of FIG. 40 into the circuit of FIG. . FIG. 41 shows the input voltage V
₇ shows changes in output voltage _Vout and power consumption during four output periods when in is input in the order of 3V, 2V, 5V, and 0V. FIG.
1 indicates that the output voltage _Vout can output a voltage in the power supply voltage range. In FIG. 41, one data line load is precharged to 5 V during the first and third output periods, and is precharged to 0 V during the second and fourth output periods.
That is, in the driver of FIG. 40, the potential difference between the output voltage V _out and the precharge voltage is smaller than that of the driver of FIG. 36, and thus the consumption of charge / discharge power by the precharge is smaller than that of the driver of FIG. In FIG. 41, when the output voltage is stabilized by the action of the source follower of the P-channel transistor 2 or the N-channel transistor 2 ′ after the precharge, the power consumption thereafter becomes almost zero.

[0102] Further, 4 output when introduced into the circuit of Figure 35 a conventional driver constituted by an operational amplifier as shown in (A) of FIG. 42, inputs the input voltage V _in 3V, 2V, 5V, in order of 0V FIG. 42B shows a simulation result of the output voltage V _out and the power consumption in the period. In the comparison between FIG. 41 and FIG. 42 (B), the power consumption in the entire output period is represented by an area surrounded by a power consumption curve (dotted line) and a zero power straight line (horizontal axis in the figure). In FIG. 42B, the operational amplifier constantly consumes electric power because the operational amplifier constantly supplies current inside the circuit. On the other hand, in FIG. 41, the driver in FIG. 40 consumes almost no power except during the precharge period. Therefore, the driver of FIG.
The power consumption is smaller than that of the operational amplifier of FIG. Also,
In the case of a small-sized liquid crystal display device having a smaller data line load than the 10-inch VGA panel, the charge / discharge power of the data lines is reduced, so that the driver of FIG.

As described above, the power consumption of the operational amplifier shown in FIGS. 39A and 42A has a predetermined value irrespective of the data line load, whereas the power consumption of the driver shown in FIGS. The power is due to charging and discharging of the data line load, and depends on the capacity of the data line load. Therefore, FIG.
In the driver of FIG. 40, the effect of reducing power consumption increases as the data line load capacitance decreases. In each of the embodiments of the present invention, a case has been described in which the driver is constituted by a MOS transistor. However, the same operation and effect can be obtained even if the driver is constituted by another gate insulating transistor.
Further, each driver can be used not only for driving data lines of a liquid crystal display device but also for driving other capacitive loads.

[0104]

As described above, according to the present invention, since there is no operational amplifier composed of a large number of terminals, the chip size of the driving circuit of the liquid crystal display device can be reduced, and the manufacturing cost can be reduced. Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a driver of a drive circuit of a liquid crystal display device according to the present invention.

FIG. 2 is a timing chart showing an operation of the circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a modification of FIG. 1;

FIG. 4 is a timing chart showing the operation of the circuit of FIG. 3;

FIG. 5 is a timing chart showing another circuit operation of FIG. 1;

FIG. 6 is a circuit diagram showing a second embodiment of the driver of the drive circuit of the liquid crystal display device according to the present invention.

FIG. 7 is a timing chart showing the operation of the circuit of FIG. 6;

FIG. 8 is a circuit diagram showing a modification of FIG. 6;

FIG. 9 is a timing chart showing the operation of the circuit of FIG. 8;

FIG. 10 is a timing chart showing another circuit operation of FIG. 6;

FIG. 11 is a circuit diagram showing a third embodiment of the driver of the drive circuit of the liquid crystal display device according to the present invention.

FIG. 12 is a timing chart showing the operation of the circuit of FIG. 11;

FIG. 13 is a circuit diagram showing a fourth embodiment of the driver of the drive circuit of the liquid crystal display device according to the present invention.

FIG. 14 is a circuit diagram showing a specific circuit of FIG.

FIG. 15 is a table showing a relationship between eight gradation voltages and video data signals.

FIG. 16 is a timing chart showing the operation of the circuit in FIG. 13;

FIG. 17 is a table showing the operation of the switches shown in FIGS. 13 and 14;

FIG. 18 is a table showing the operation of the switches in FIGS. 13 and 14;

FIG. 19 is a table showing the operation of the switch in FIG. 13;

FIG. 20 is a circuit diagram showing a modification of FIG. 1;

FIG. 21 is a circuit diagram showing a modification of FIG. 6;

FIG. 22 is a circuit diagram showing a modification of FIG. 11;

FIG. 23 is a circuit diagram showing a modification of FIG. 13;

FIG. 24 is a circuit diagram showing a modification of FIG. 1;

FIG. 25 is a circuit diagram showing a modification of FIG. 6;

FIG. 26 is a circuit diagram showing a modification of FIG. 11;

FIG. 27 is a circuit diagram showing a modification of FIG. 13;

FIG. 28 is a circuit diagram showing a modification of FIG. 1;

FIG. 29 is a circuit diagram showing a modification of FIG. 6;

FIG. 30 is a circuit diagram showing a modification of FIG. 11;

FIG. 31 is a circuit diagram showing a modification of FIG. 13;

FIG. 32 is a timing chart showing an operation of the circuit of FIG. 28;

FIG. 33 is a circuit diagram showing a fifth embodiment of the driver of the drive circuit of the liquid crystal display device according to the present invention.

FIG. 34 is a timing chart showing an operation of the circuit of FIG. 33;

FIG. 35 is a circuit diagram of a circuit to be simulated;

FIG. 36 is a circuit diagram in which a size is introduced into FIG. 1;

FIG. 37 is a timing chart showing a result of a simulation performed by introducing the circuit of FIG. 36 into the circuit of FIG. 35;

FIG. 38 is a timing chart showing a result of a simulation performed by introducing the circuit of FIG. 36 into the circuit of FIG. 35;

FIG. 39 is a timing chart showing a result of a simulation performed by introducing a conventional driver into the circuit of FIG. 35;

FIG. 40 is a circuit diagram in which a size is introduced in FIG.

41 is a timing chart showing a result of a simulation performed by introducing the circuit of FIG. 40 into the circuit of FIG. 35;

42 is a timing chart showing a result of a simulation performed by introducing a conventional driver into the circuit of FIG. 35;

FIG. 43 is a circuit diagram showing a driving circuit of a conventional liquid crystal display device.

[Explanation of symbols]

1, 2, 2A, 2B @ P-channel MOS transistors 1 ', 2', 2'A, 2'B @ N-channel MOS transistors SW1, SW2, ─, SW5, SW1 ', SW2',
─, SW4'─ switch V _in ─ input voltage V _out ─ the output voltage 101─ dividing circuit 102─ decoder 103─ driver (buffer)

Claims (15)

[Claims] 1. A data line (D) receiving an input voltage (V _in ).
L) driven by an output voltage (V _out ), a first and second power supply terminals (T1, T2), an input terminal receiving the input voltage, and 0 outputting the output voltage. A first MOS transistor (1, 1 ') having a drain and a gate connected to each other, and a gate having a source connected to the output terminal and having a voltage equal to the gate of the first MOS transistor. Have
A second MOS transistor (2, 2 ′) having the same conductivity type as the first MOS transistor; and a first switch (SW1) connected between the input terminal and a source of the first MOS transistor. , SW
1 ′), and a second switch (SW2, SW2) connected between the first power supply terminal and the drain of the first MOS transistor.
SW2 ′) and a third switch (SW4, SW4) connected between the first power supply terminal and the drain of the second MOS transistor.
SW4 ′), and a fourth switch (SW3, SW3 ′) connected between the second power supply terminal and the output terminal, and controlling the first and second switches to control the first and second switches. Second MOS
The gate voltage of the transistor is changed from the input voltage to the first voltage.
Threshold voltage (V _thp1 ,
V _thn1 ), and the third and fourth switches are operated to operate the second MO.
An S transistor is operated as a source follower, and the voltage of the second MOS transistor is determined based on the voltage of the gate of the second MOS transistor.
Threshold voltage (V _thp2 ,
A driving circuit for a liquid crystal display device, wherein a voltage shifted by V _thn2 ) is output to the output terminal as the output voltage. 2. The device according to claim 1, further comprising a capacitor connected between at least one of the gates of the first and second MOS transistors and the first power supply terminal. Drive circuit for liquid crystal display device. 3. A source connected to the source of the second MOS transistor, a gate connected to the gate of the second MOS transistor, and the second MOS transistor.
2. The driving circuit according to claim 1, further comprising at least one third MOS transistor having a drain connected to a drain of the S transistor and having the same conductivity type as the second MOS transistor. 4. A fifth switch (SW5) connected between the input terminal and the output terminal, wherein the fifth switch is operated after the second MOS transistor operates as a source follower. 2. The driving circuit for a liquid crystal display device according to claim 1, wherein the switch is turned on. 5. A data line (D) receiving an input voltage (V _in ).
L) driven by an output voltage (V _out ), a first power supply terminal (T1) to which a first power supply voltage (E1) is applied, and a first power supply terminal higher than the first power supply voltage. A second power supply terminal (T2) to which a second power supply voltage (E2) is applied; an input terminal for receiving the input voltage; an output terminal for outputting the output voltage; One P-channel MO
An S transistor (1), a second P-channel MOS transistor (2) having a source connected to the output terminal and having a gate having a voltage equal to the gate of the first P-channel MOS transistor
And a first switch (SW) connected between the input terminal and the source of the first P-channel MOS transistor.
1) a second switch (SW2) connected between the first power supply terminal and the drain of the first P-channel MOS transistor; and the first power supply terminal and the second P-channel. A third switch (SW4) connected between the drain of the MOS transistor, and a first N-channel MO having the drain and the gate connected.
An S transistor (1 '); a second N-channel MOS transistor (2') having a source connected to the output terminal and having a gate having a voltage equal to the gate of the first N-channel MOS transistor; A fourth switch (SW) connected between the terminal and the source of the first N-channel MOS transistor
1 '), a fifth switch (SW2') connected between the second power supply terminal and the drain of the first N-channel MOS transistor, and a second switch connected to the second power supply terminal. And a sixth switch (SW4 ') connected between the drain of the N-channel MOS transistor and a gate voltage of the second P-channel MOS transistor by controlling the first and second switches. _Is biased from the input voltage by a threshold voltage (V _thp1 ) of the first P-channel MOS transistor, and the second and N-channel MOS transistors are controlled by controlling the fourth and fifth switches. biasing the gate voltage to the threshold voltage _(V thn1) shifted by the voltage of the first N-channel MOS transistor from the input voltage, prior to controlling said third switch The second P-channel M
An OS transistor is operated as a source follower, and a voltage shifted by a threshold voltage (V _thp2 ) of the second P-channel MOS transistor from a gate voltage of the second P-channel MOS transistor is used as the output voltage. To the second N-channel M by controlling the sixth switch.
An OS transistor is operated as a source follower, and a voltage shifted by a threshold voltage (V _thn2 ) of the second N-channel MOS transistor from a gate voltage of the second N-channel MOS transistor is used as the output voltage. A driving circuit for a liquid crystal display device, which outputs the signal to a terminal. 6. The semiconductor device according to claim 1, further comprising a second power supply terminal connected between the second power supply terminal and the output terminal.
A seventh switch (SW3) for charging the output terminal using the second power supply voltage when the input voltage is higher than a predetermined value, and between a first power supply terminal and the output terminal. Connected
The liquid crystal display device according to claim 5, further comprising: an eighth switch (SW3 ') for charging the output terminal using the first power supply voltage when the input voltage is not higher than a predetermined value. Drive circuit. 7. After the control of the seventh switch to charge the output terminal with the second power supply voltage, the third switch is turned on and the sixth switch is turned off, and the second switch is turned off. Operating the P-channel MOS transistor as a source follower, and controlling the eighth switch to connect the output terminal to the first terminal.
7. The liquid crystal display device according to claim 6, wherein after charging by the power supply voltage, the sixth switch is turned on and the third switch is turned off to operate the second N-channel MOS transistor as a source follower. Drive circuit. 8. When the input voltage is equal to the second power supply voltage, the seventh switch is kept on and the third, sixth, and eighth switches are kept off, and the input voltage is 7. The driving circuit for a liquid crystal display device according to claim 6, wherein when equal to the first power supply voltage, the eighth switch is kept on and the third, sixth, and seventh switches are kept off. 9. A capacitor (3) connected between at least one of the gates of the first and second P-channel MOS transistors and the first power supply terminal; and the first and second P-channel MOS transistors. 6. The driving circuit for a liquid crystal display device according to claim 5, further comprising: a capacitor connected between at least one gate of the N-channel MOS transistor and the second power supply terminal. 10. A source connected to a source of the second P-channel MOS transistor, a gate connected to a gate of the second P-channel MOS transistor, and a drain connected to the drain of the second P-channel MOS transistor. At least one third P-channel MOS transistor having a connected drain; a source connected to the source of the second N-channel MOS transistor; a gate connected to the gate of the second N-channel MOS transistor And at least one third N-channel MOS having a drain connected to the drain of the second N-channel MOS transistor
6. The driving circuit for a liquid crystal display device according to claim 5, comprising a transistor. 11. A ninth switch (SW5) connected between the input terminal and the output terminal, wherein the second P-channel MOS transistor and the second switch are connected to each other.
6. The driving circuit for a liquid crystal display device according to claim 5, wherein the ninth switch is turned on after at least one of the N-channel transistors operates as a source follower. 12. The first and second input voltages (V _inA ,
V _inB) receiving the data lines (DL _1, DL ₂₎ the output voltage (V _outA, in the driving circuit of the liquid crystal display device driven by V _outB), the first power supply voltage (E1A) is applied 1 And a second power supply voltage (E2A) higher than the first power supply voltage.
A third power supply terminal to which a third power supply voltage (E1B) is applied; and a fourth power supply voltage (E2B) higher than the third power supply voltage.
And a first power supply terminal connected to the first and second power supply terminals and receiving the first input voltage to generate a first output voltage (V _outA ).
And a second driver block (341A) that is connected to the third and fourth power supply terminals and receives the second input voltage to generate a second output voltage (V _outB ).
And a switch circuit (342) connected to the first and second driver blocks and selectively supplying the first and second output voltages to the first and second data lines. , 343, 344,
345), wherein each of the driver blocks comprises: an input terminal for receiving one of the first and second input voltages; an output terminal for outputting one of the first and second output voltages; First P-channel MO having drain and gate connected
An S transistor (1A, 1B); a second P-channel MOS transistor (2) having a source connected to the output terminal and having a gate having a voltage equal to that of the gate of the first P-channel MOS transistor.
A, 2B) and a first switch (SW1) connected between the input terminal and the source of the first P-channel MOS transistor.
A, SW1B), a second switch (SW2A, SW2B) connected between the first power supply terminal and a drain of the first P-channel MOS transistor, and a first power supply terminal and the second switch. A third switch (SW4A, SW4B) connected between the drain of the second P-channel MOS transistor and a first N-channel MO having the drain and the gate connected to each other.
An S transistor (1′A, 1′B); and a second N-channel MOS transistor (2 ′) having a source connected to the output terminal and having a gate having a voltage equal to the gate of the first N-channel MOS transistor.
A, 2'B) and a fourth switch (SW) connected between the input terminal and the source of the first N-channel MOS transistor.
1′A, SW1′B), a fifth switch (SW2′A, SW2′B) connected between the second power supply terminal and the drain of the first N-channel MOS transistor, And a sixth switch (SW4′A, SW4′B) connected between a second power supply terminal and a drain of the second N-channel MOS transistor. The first and second switches And biasing the gate voltage of the second P-channel MOS transistor to a voltage shifted from the input voltage by the threshold voltage of the first P-channel MOS transistor, and setting the fourth and fifth switches Controlling the gate voltage of the second N-channel MOS transistor to a voltage shifted from the input voltage by the threshold voltage of the first N-channel MOS transistor; Wherein by controlling the pitch second P-channel M
An OS transistor is operated as a source follower, and a voltage shifted from a gate voltage of the second P-channel MOS transistor by a threshold voltage of the second P-channel MOS transistor is output to the output terminal as the output voltage. Controlling the sixth switch to control the second N channel M
An OS transistor is operated as a source follower, and a voltage shifted from a gate voltage of the second N-channel MOS transistor by a threshold voltage of the second N-channel MOS transistor is output to the output terminal as the output voltage. A driving circuit for a liquid crystal display device, comprising: 13. The first and second driver blocks are connected between one of the second and fourth power supply terminals and the output terminal, and the input voltage is higher than a predetermined value. A seventh switch (SW3) for charging the output terminal using the one terminal of the second and fourth power supply voltages when the voltage is high.
A, SW3B), and one of the first and third power supply terminals is connected between the output terminal and the output terminal. When the input voltage is not higher than a predetermined value, the output terminal is connected to the first or third power supply terminal. An eighth switch (S) for charging using the one terminal having a power supply voltage of 3
The driving circuit for a liquid crystal display device according to claim 12, further comprising: W3'A, SW3'B). 14. After the seventh switch is controlled to charge the output terminal with one of the second and fourth power supply voltages, the third switch is turned on and the sixth switch is turned on. After turning off the second P-channel MOS transistor to operate as a source follower and controlling the eighth switch to charge the output terminal with one of the first and third power supply voltages, 14. The driving circuit according to claim 13, wherein the sixth switch is turned on and the third switch is turned off to operate the second N-channel MOS transistor as a source follower. 15. The driving circuit according to claim 12, wherein the first power supply voltage is equal to the fourth power supply voltage.