JPH11118552A - Adjusting circuit for sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an adjusting circuit for sensor in which a wide adjusting range and high accuracy can be attained easily through small circuit scale. SOLUTION: The adjusting circuit for the sensor comprises an analog/digital converter, an operating unit 4 for processing the output from the analog/digital converter according to a preloaded program, and a writable memory 8 for holding an adjustment data wherein the analog/digital converter is an over sampling type analog/digital converter comprising an analog integrator 1, a comparator 2 and a digital/analog converter 7. When an over sampling type analog/digital converter is employed, the number of bits of a digital signal required for keeping the adjusting range and accuracy can be decreased and the circuit scale can be limited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit which is combined with a sensor for detecting various physical quantities as electric signals and processes an output signal thereof, and is particularly suitable for a capacitance type acceleration sensor and a thermal type air flow sensor. The present invention relates to a simple sensor adjustment circuit.

[0002]

2. Description of the Related Art In a sensor for detecting a physical quantity as an electric signal, such as a capacitance type acceleration sensor, it is necessary that the magnitude of the physical quantity to be detected and the magnitude of an output signal have a desired relationship. The processing required to ensure that this desired relationship is satisfied is called calibration, and the circuit associated with the sensor for this is the sensor adjustment circuit, and thus, in short, this sensor adjustment circuit The circuit does not deviate from a conversion circuit that provides predetermined input / output characteristics.

Incidentally, the contents of processing by the sensor adjustment circuit generally include span adjustment and offset adjustment. Here, span adjustment corresponds to sensitivity adjustment, and offset adjustment corresponds to zero point adjustment. . Therefore, as this sensor adjustment circuit, a memory in which data required for output is stored at a predetermined address is used, and the address of this memory is made to correspond to the level of the input signal, and the data read by this is used as an output signal. Circuits are conventionally used.

For example, in Japanese Patent Application Laid-Open No. 3-51714,
PROM by zener zapping (programmable
(Read-only memory) and a method of selecting a lead-out portion of a resistor array according to the data content of the PROM and adjusting the sensor output thereby, and in another example, information written in the PROM is disclosed. Discloses a method of changing the circuit constant of the switched capacitor circuit based on the above and thereby adjusting the sensor output.

On the other hand, for example, in JP-A-8-62010, an AD converter (analog / digital converter) and a CP
A method of adjusting the sensor output using U (Central Processing Unit) is proposed.

[0006]

As described below, the prior art described above has a limitation in that, on the one hand, there is a limit to the expansion of the adjustment range and the improvement of the accuracy, and on the other hand, there is a limit to the suppression of an increase in the circuit scale. However, there was a problem in improving cost-effectiveness (cost performance). First, in the prior art of the method of selecting the lead portion of the resistor array and changing the circuit constant of the switched capacitor circuit, it is easy to make the circuit configuration on-chip, but if the adjustment range is increased and the accuracy is increased, This causes an exponential increase in circuit scale, which limits the expansion of the adjustment range and the improvement of accuracy.

Next, in the prior art using the AD converter and the CPU, the adjustment range can be expanded relatively easily and the accuracy can be increased relatively easily. However, the function is reduced when the general-purpose AD converter and the CPU are used. Overlapping portions (overhangs) appear, causing many useless portions in the circuit, which increases the circuit scale and limits the suppression. An object of the present invention is to provide a sensor adjustment circuit that can easily obtain a wide adjustment range and high accuracy with a small circuit scale.

[0008]

An object of the present invention is to provide an analog / digital converter.
In a sensor adjustment circuit including a digital converter, an arithmetic unit for performing an arithmetic operation on an output of the analog-digital converter by a program incorporated in advance, and a writable memory for holding adjustment data, Achieved by configuring the digital converter with an oversampling type analog / digital converter including an analog integrator, a comparison circuit, and a digital / analog converter.

By using an oversampling type analog-to-digital converter, the number of bits of a digital signal necessary for maintaining the adjustment range and accuracy can be reduced, and the circuit scale can be reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a sensor adjusting circuit according to the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 shows a first embodiment of the present invention, in which 1 is an analog integrator, 2 is a comparator, 3 is a digital integrator, 4 is an arithmetic unit, and 5 is a DA converter (digital / analog converter). , 6 is an LPF (low-pass filter), 7 is a DA converter, and 8 is a PROM.

The level adjustment circuit according to the present invention is roughly composed of three types of functional parts. In the embodiment of FIG. 1, these functional parts are respectively described below. First, the first functional part includes an analog integrator 1 and a comparator 2, a digital integrator 3 and a DA converter 7. Then, first, the difference between the input signal from the sensor and the output of the DA converter 7 is integrated by the analog integrator 1.

Next, the output of the analog integrator 1 is input to a comparator 2 and is compared with a predetermined voltage at predetermined intervals to convert it into a level 0 and level 1 signal. Further, the output of the comparator 2 is input to the digital integrator 3 for integration, and the result is output as a time-series digital signal having a predetermined number of bits.

The output of the digital integrator 3 is D
The signal is also input to the A converter 7, where it is converted to an analog signal and subtracted from the input signal. Thus, the first functional part has a function of outputting a time-series digital signal having a number of bits equal to the number of bits of the DA converter 7 and having an average value that changes in accordance with an input signal from the digital integrator 3. .

At this time, the operation cycle (reciprocal of the frequency) of the comparator 2 is set to a value (for example, ten times as large as the frequency) which is smaller than, for example, 1/10 of the operation cycle determined from the response required for the target sensor. By setting to (the above large value), this first functional part exhibits a function as a so-called oversampling type AD converter, and as a result,
Even if the number of bits of the DA converter 7 is 1 bit in principle, the necessary adjustment range and accuracy can be maintained.

This is because the sensor adjustment circuit of the present invention obtains necessary adjustment by operating the average value. Even if the number of bits of the DA converter 7 is one, the output signal In this case, the digital integrator 3 is unnecessary, and the output of the comparator 2 may be supplied to the arithmetic unit 4 and the DA converter 7 as they are.

If the number of bits of the DA converter 7 is set to 1 bit, a problem as described later occurs, which is not very practical. However, according to the present invention,
The number of bits can be considerably smaller than the number of bits calculated from the required precision, for example, about 4 to 12 bits.

Next, the second functional part is composed of the arithmetic unit 4 and the PR
OM8. The arithmetic unit 4 calculates the signal output from the digital integrator 3 and the digital data read from the PROM 8 to obtain the first data.
The average value of the output signal obtained from the functional part is changed.

Thus, this second functional part serves to substantially adjust the zero point and span of the output signal from the sensor. At this time, since the number of bits of the signal output from the first functional unit is reduced as described above, the circuit scale of the arithmetic unit 4 can be reduced accordingly. Also, at this time, since the digital arithmetic processing is performed, there is no danger of being affected by variations in the elements and changes in temperature unlike the adjustment performed by the analog circuit elements, so that highly accurate adjustment can be easily obtained.

Finally, the third functional part is the DA converter 5
And the LPF 6. The DA converter 5 converts the digital signal output from the arithmetic unit 4 into an analog signal, and the LPF 6 smoothes the analog signal output from the DA converter 5.

As a result, the third functional part is
A digital signal obtained from the functional part is converted into an analog signal, averaged, and output as an adjusted sensor signal. Also at this time, as described above, since the number of bits of the signal output from the first functional unit is reduced, the circuit scale of the DA converter 5 can be reduced.

As described above, in this embodiment, the analog integrator 1, the comparator 2, the digital integrator 3, and the DA
As a result of using the oversampling type AD converter configured with the converter 7, even if the number of bits of the digital signal is reduced, the necessary adjustment range and accuracy can be maintained.
The circuit scale can be reduced. In addition, since the adjustment process is performed using a digital signal, there is no possibility of being affected by variations in adjustment circuit elements or temperature changes, and high accuracy can be easily maintained.

Next, the optimum number of bits of the DA converter 7 will be described. This number of bits can be reduced to one bit as described above. By the way, the number of bits has a trade-off relationship with the number of input signals required for averaging for maintaining desired accuracy.If the number of bits is reduced, the number of input signals for averaging must be increased. Will not be.

In addition, since the time required to obtain the average value is restricted by the response of the target sensor, it is necessary to increase the operation speed of the sensor adjustment circuit itself as the number of input signals increases. As a result, a heavy load is particularly imposed on the arithmetic unit 4 and high performance is required, so that the cost increases.

Conversely, if the number of bits is increased to, for example, 16 bits, the operation speed of the sensor adjustment circuit itself can be reduced, but the digital integrator 3 and the arithmetic unit 4 need to process a large number of bits. As a result, the circuit scale increases. In view of the above, in the embodiment of the present invention, it is considered that the number of bits of the DA converter 7 is appropriately 4 to 8 bits. If the number of bits is set to 4 to 8 bits, the operation speed of the sensor adjustment circuit itself is within a practical range, and the circuit scale is also within an appropriate range.

Next, embodiments of the present invention will be described more specifically. According to the present invention, the above-described first functional portion can be implemented integrally with a detection circuit of a sensor to be combined. Therefore, the embodiment will be described below. First, FIG. 2 shows an embodiment in which a capacitive sensor is applied as a sensor to be combined.

Note that this capacitive sensor is a sensor of a type that detects a physical quantity to be detected as a change in capacitance, and a typical example is a capacitive acceleration sensor. In FIG. 2, 9, 10, 12, 13, 17, and 18 are analog switches, 11 is a sensor capacitor, 14 is a feedback capacitor, 15 is an operational amplifier, and 16 is a reference capacitor. It is the same as FIG.

The analog switches 9 to are composed of well-known semiconductor switches and the like, and include analog switches 9, 13, and 18 of group A and analog switches 10 and 1 of group B.
When the group A is turned on, the group B is turned off. When the group A is turned off, the group B is turned on. ing.

The capacitance of the sensor capacitor 11 is configured to change according to the physical quantity to be detected. At this time, when the sensor is an acceleration sensor, the capacitance is changed according to the acceleration acting on the sensor. Sensor capacitor 1
1 will be changed.

The operational amplifier 15 includes a feedback capacitor 1
4, the device operates as an integrator, thereby exhibiting the same function as the analog integrator 1 in the embodiment of FIG. The reference capacitor 16 is charged with the output of the DA converter 7 and functions to feed back the output of the DA converter 7.

Next, the operation of the embodiment shown in FIG. 2 will be described. In this embodiment, the first and second operations for alternately controlling the on / off of the analog switches of the groups A and B are repeated at a predetermined cycle. Thus, the capacitance value of the sensor capacitor 11 is detected. The cycle at which the first and second operations are repeated at this time may be the same as or shorter than the operation cycle of the comparator 2 described above.

First, in the first operation, the analog switches 10, 12, 17 of the B group are controlled to be turned on. Then, the sensor capacitors 11 are discharged by the analog switches 10 and 12, and the reference capacitors 16
The output of the DA converter 7 is charged via the analog switch 17.

Next, in a second operation, the analog switches 9, 13, and 18 of the group A are controlled to be turned on. Then,
This time, the sensor capacitor 11 and the reference capacitor 16 are connected in series between the power supply voltage Vcc and the ground via the analog switches 9 and 18, and the sensor capacitor 11 and the reference capacitor 16 are connected via the analog switch 13. Is connected to the inverting input of the operational amplifier 15.

Then, the sensor capacitor 11 is charged by the power supply voltage Vcc, and the reference capacitor 16 is discharged. The difference between the charging current of the sensor capacitor 11 and the discharge current of the reference capacitor 16 at this time. Is charged in the feedback capacitor 14 via the analog switch 13, and as a result, a voltage corresponding to the terminal voltage of the feedback capacitor 14 appears in the output of the operational amplifier 15.

The voltage appearing at the output of the operational amplifier 15 is supplied to the DA converter 7 via the comparator 2 and the digital integrator 3, and charges the reference capacitor 16 in the first operation in the next cycle. It becomes the value of the current. As a result, the average value output from the digital integrator 3 is
(Expression 1) is obtained.

[0035]

(Equation 1)

As is apparent from the equation (1), the output of the digital integrator 3 shown in FIG.
A digital signal representing a capacitance value of 1 is thus obtained, so that according to this embodiment, the first functional part of the sensor adjustment circuit also serves as the detection circuit of the capacitive sensor to be associated therewith. It turns out that it has become the composition.

Therefore, according to the embodiment of FIG. 2, the sensor adjustment circuit can be provided with the function of the sensor circuit to be combined with the sensor adjustment circuit. It is possible to sufficiently reduce the overall circuit scale including the circuit.

Further, according to this embodiment, it is possible to reduce the detection error. This is because errors in each circuit are added when separate circuit configurations are used. However, in the embodiment of FIG. 2, since the detection circuit of the sensor is combined with the first functional portion, feedback is performed. This is because the effect can reduce the error.

Next, FIG. 3 shows an embodiment in which a sensor to be combined is a thermal air flow meter used for controlling an engine of an automobile, and FIG.
22 is a hot wire resistance, 23 is a differential amplifier, and other components are the same as the embodiment of FIG. The four hot-wire resistors 19 to 22 form a bridge circuit, and the voltage when the bridge circuit is unbalanced due to the air flow is detected by the differential amplifier 23 and used as a detection signal of the air flow rate. At this time, by using the output of the DA converter 7 as the current source of the bridge circuit composed of the hot wire resistors 19 to 22, both the detection circuit of the hot wire air flow meter and the first functional part of the sensor adjustment circuit are configured. Will be.

Therefore, according to the embodiment shown in FIG.
The sensor adjustment circuit can be provided with the function of the sensor circuit to be combined with the sensor adjustment circuit. As a result, a wide adjustment range and high accuracy can be ensured, and the overall circuit scale including the sensor circuit can be sufficiently reduced. It is possible to further reduce the error.

Next, the operation of the arithmetic unit 4 in the above embodiment will be described with reference to the operation block diagram of FIG. As described above, the arithmetic unit 4 adjusts the cell point for the output of the target sensor by adding and multiplying a predetermined value to the average value of the input signal (the time series digital signal output from the digital integrator 3). First, the addition processing for the zero point adjustment is performed by the circuit in which the number of bits is equal to that of the DA converter 7 and is previously written in the PROM 8.
It is obtained by reading the digital processing sequence 24 whose average value is the target adjustment value and adding it to the input signal. At this time, by simply adding, the addition to the average value of the input signal is performed by the bit. It can be obtained without changing the number. However, if an overflow occurs,
A process for correcting this is required.

Next, in the multiplication process for span adjustment, the bit number DA
A digital processing sequence which is equal to the converter 7 and whose average value is a target adjustment value, and whose frequency characteristics are set so as not to overlap the frequency distribution of the input signal as shown in FIG. 25 is obtained by multiplying the input signal by reading out the signal 25. In this case, it is sufficient to simply multiply the input signal. In this case, the number of bits is doubled due to the multiplication. However, since the effective bits are only in the initial bits, the same number of bits as the input signal can be maintained by truncating the lower half bits. it can.

Here, as shown in FIG. 5, the reason why the frequency distributions are not overlapped is as follows. That is, if the frequency of the input signal and the frequency of the digital signal sequence 25 are overlapped, the signal in the band where the frequency is overlapped is converted into direct current by the multiplication process, and as a result, the average value may be disturbed. Because there is.

Next, the digital integrator 3 and the arithmetic unit 4 are set to M
An embodiment constituted by a PU (micro processor sync unit) will be described with reference to FIG. As shown in FIG. 6, the MPU shown in FIG. 6 includes a RAM 26 for temporarily storing data and a PROM 27 for storing adjustment data.
(Equivalent to the PROM 8), an accumulator 28, an arithmetic unit 29 for executing an operation, a control unit 30, a program counter 3
1. It comprises a ROM 32 for storing programs,
According to the program written in the RAM 32, the control unit 30 causes the arithmetic unit 29 and the program counter 3
1, the data bus is managed and the digital integrator 3
And processing necessary for the operation as the arithmetic unit 4 is executed.

In this embodiment, the program counter 3
1 directly accesses the program storage ROM 32 and outputs the output data of the ROM 32 directly to the control unit 30. The instruction system at this time is one instruction and one word, so that the backward branch instruction is disabled, and the maximum count value of the program counter 31 and the number of words of the program storage ROM 32 are made the same. Thereby, in this embodiment, the program operates correctly without performing the reset operation,
This eliminates the need for reset at power-on, so-called power-on reset processing.

When the power is turned on, if the reset is not performed, the count value of the program counter 31 is indefinite, so that it is not known from which address the program starts.
In the above embodiment, since there is no backward branch instruction in the program, the count value of the program counter 31 always increases when started, and returns to 0 after the count value reaches the maximum value. As a result, it is guaranteed that the program always operates by passing the address of address 0, and therefore, it is not necessary to perform the reset process.

For this reason, naturally, in this embodiment, the configuration of the program itself is limited to a so-called cyclic type program which circulates from the address 0 to the maximum count value of the program counter 31.
However, in the case of this embodiment, since only the program for obtaining the operations of the digital integrator 3 and the arithmetic unit 4 is used, there is no restriction that only a cyclic type program can be used.

Not only this, on the contrary, MPU
Means to be more resistant to runaway. This is because even if the MPU goes out of control, the destination address of the runaway is always the address of the program, and the program is a cyclic program, so that normal processing will eventually return.

As is well known, a general-purpose MPU is usually provided with a monitoring means such as a watchdog timer in order to ensure the reset operation and cope with runaway.
However, in this embodiment, as described above, the reset process can be made unnecessary, and there is no particular problem in the case of runaway of the MPU. Can be further improved.

Next, an embodiment of the PROM 8 will be described.
This will be described with reference to FIG. FIG. 7 shows the configuration of the unit storage cell of the PROM 8. In this embodiment, the unit storage cell is composed of three PROM memory cells 33, 34, 3
5, and the data read therefrom is output via the majority logic circuit 36.

In general, PROMs are susceptible to temperature, and their reliability decreases at high temperatures. Particularly, in the case of a sensor used in an engine room of an automobile, a space, or the like, since the sensor is exposed to a high temperature, the reliability is likely to be reduced. Therefore, FIG.
In the embodiment, by using data from a plurality of memory cells and taking majority logic, it has error correction logic and error detection logic, thereby eliminating erroneous data and maintaining high reliability. I did it.

Next, another embodiment of the present invention will be described. FIG. 8 shows an embodiment of the present invention, as shown in FIG.
One MPU 41 is provided in common for a plurality of sensors, for example, three sensors A, B, and C, and functions as a digital integrator and an arithmetic unit for each sensor by time division processing. Things.

Here, reference numerals 1A, 1B and 1C denote analog integrators, which are the same as the analog integrator 1 in the embodiment of FIG.
5A, 5B, and 5C are provided to the DA converter 5, 6A,
6B corresponds to the LFP 6, and 7A, 7B and 7C correspond to the DA converter 7.

The MPU 41 is the same as that described with reference to FIG. 6, but as described above, the outputs of the sensors A, B, and C are sequentially time-division-processed in a predetermined order. Like the digital integrator 3 and the arithmetic unit 4, the operation is performed such that zero point adjustment and span adjustment are provided for each sensor.

Therefore, according to the embodiment of FIG. 8, the circuit scale can be reduced as compared with the case where the digital integrator 3 and the arithmetic unit 4 are provided independently for each of a plurality of sensors. There is. In addition, since outputs from a plurality of sensors can be processed in association with each other, the output of a certain sensor can be used to compensate the output of another sensor, or the ratio or difference between the outputs of a plurality of sensors can be reduced. The advantage is that it can be easily handled when necessary.

[0056]

According to the present invention, since the oversampling type analog-to-digital converter is used, the number of bits of the digital signal required for securing the adjustment range and maintaining the accuracy can be reduced. The circuit scale can be sufficiently reduced while maintaining the adjustment range.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a sensor adjustment circuit according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the sensor adjustment circuit according to the present invention.

FIG. 3 is a block diagram showing still another embodiment of the sensor adjustment circuit according to the present invention.

FIG. 4 is an operation block diagram of a calculator according to the embodiment of the present invention.

FIG. 5 is a frequency characteristic diagram of a signal according to an embodiment of the present invention.

FIG. 6 shows a digital integrator and an arithmetic unit according to the present invention,
It is a block diagram showing one embodiment when constituted by PU.

FIG. 7 is a block diagram showing one embodiment of a PROM according to the present invention.

FIG. 8 is a block diagram showing another embodiment of the sensor adjustment circuit according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Analog integrator 2 Comparator 3 Digital integrator 4 Computing unit 5 DA converter 6 LFP 7 DA converter 8 PROM

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyomi Suzuki 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory, Ltd. (72) Inventor Akihiko Saito 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Atsushi Miyazaki, Hitachinaka City, Ibaraki Prefecture 2520 Oji Takaba Co., Ltd. Hitachi Ltd.Automotive Equipment Division (72) Inventor Keiji Hanzawa Hitachinaka City, Ibaraki Prefecture 2477 Inside Hitachi Car Engineering Co., Ltd.

Claims (7)

[Claims] An analog-to-digital converter, an arithmetic unit for performing an arithmetic operation on an output of the analog-to-digital converter according to a pre-installed program, and a writable memory for holding adjustment data. In the sensor adjustment circuit, the analog / digital converter is constituted by an oversampling type analog / digital converter including an analog integrator, a comparison circuit, and a digital / analog converter. . 2. An analog-to-digital converter, an arithmetic unit for performing an arithmetic operation on an output of the analog-to-digital converter according to a pre-installed program, and a writable memory for holding adjustment data. In the sensor adjustment circuit, the analog-to-digital converter includes an oversampling type analog-to-digital converter including an analog integrator, a comparison circuit, and a digital-to-analog converter. Is the output of the number of bits less than the precision required by the target sensor,
A sensor adjustment circuit configured to output at a cycle of 1 / th or less. 3. An analog-to-digital converter, an arithmetic unit for performing an arithmetic operation on an output of the analog-to-digital converter by a pre-installed program, and a writable memory for holding adjustment data. In the sensor adjustment circuit, the analog-to-digital converter includes an oversampling type analog-to-digital converter including an analog integrator, a comparison circuit, and a digital-to-analog converter. A sensor adjustment circuit having a conversion accuracy of 4 bits to 8 bits. 4. An analog-to-digital converter, an arithmetic unit for performing an arithmetic operation on an output of the analog-to-digital converter according to a pre-installed program, and a writable memory for holding adjustment data. In the sensor adjustment circuit, the analog-to-digital converter is constituted by an over-sampling type analog-to-digital converter including an analog integrator, a comparison circuit, and a digital-to-analog converter; The sensor adjustment circuit, wherein the converter forms a part of a detection circuit of the target sensor. 5. An analog-to-digital converter, an arithmetic unit for performing an arithmetic operation on an output of the analog-to-digital converter by a pre-installed program, and a writable memory for holding adjustment data. In the sensor adjustment circuit, the analog-to-digital converter includes an oversampling type analog-to-digital converter including an analog integrator, a comparison circuit, and a digital-to-analog converter. Is the output of the number of bits less than the precision required by the target sensor,
A sensor adjustment circuit configured to output at a cycle of 1 / th or less, and to be configured so that the average value of the output of the arithmetic unit satisfies the necessity of the sensor. 6. The invention according to claim 1, wherein the arithmetic unit operates by a cyclic program which circulates an address from address 0 to a maximum count value of a program counter, and is reset at power-on. A sensor adjustment circuit characterized in that the sensor adjustment circuit is not required. 7. The sensor adjustment circuit according to claim 1, wherein the writable memory holding the adjustment data has an error correction logic and an error detection logic.