JPH11112003A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH11112003A JPH11112003A JP10178832A JP17883298A JPH11112003A JP H11112003 A JPH11112003 A JP H11112003A JP 10178832 A JP10178832 A JP 10178832A JP 17883298 A JP17883298 A JP 17883298A JP H11112003 A JPH11112003 A JP H11112003A
- Authority
- JP
- Japan
- Prior art keywords
- gate insulating
- film
- active layer
- thin film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910004205 SiNX Inorganic materials 0.000 claims abstract description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 57
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
- 241001239379 Calophysus macropterus Species 0.000 claims description 2
- 229910016024 MoTa Inorganic materials 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、薄膜トランジスタ
に関し、特に、アクティブマトリクス型液晶表示装置に
使われる薄膜トランジスタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly, to a thin film transistor used for an active matrix type liquid crystal display device.
【０００２】[0002]
【従来の技術】一般的に、アクティブマトリクス型液晶
表示(active matrix-typeliquid crystaldisplay;ＡＭ-
ＬＣＤ) 装置は薄くて多様な表示装置に使われる。こ
うしたＡＭ-ＬＣＤ装置において、薄膜トランジスタ(th
infilmtransistor;ＴＦＴ）が各画素に対するスイッチ
ング素子として提供され、個々の画素電極等が独立的に
駆動されるため、デューティー(duty)比の低減に起因す
るコントラストが低減されず、またディスプレー容量が
増加してライン数が増加される時にも視野角が低減され
ていない。2. Description of the Related Art Generally, an active matrix-type liquid crystal display (AM-
LCD) devices are used for thin and various display devices. In such an AM-LCD device, a thin film transistor (th
An in-film transistor (TFT) is provided as a switching element for each pixel, and the individual pixel electrodes and the like are driven independently, so that the contrast due to the reduction in the duty ratio is not reduced and the display capacity is increased. Even when the number of lines is increased, the viewing angle is not reduced.
【０００３】図１はＡＭ- ＬＣＤ装置に使われる一般的
なＴＦＴを示した断面図である。図１を参照すれば、ガ
ラスのような透明な絶縁基板１１上にゲート電極１２が
形成され、ゲート電極１２が形成された絶縁基板１１上
にゲート絶縁膜１３が形成される。ゲート絶縁膜１３上
にゲート電極１２に対向する非晶質シリコンからなるア
クティブ層１４が形成される。ゲート電極１２上部のア
クティブ層１４上にエッジストッパ１５が形成される。
エッジストッパ１５の上面を露出させるソース及びドレ
イン電極１７-1、１７-２がエッジストッパ１５の両側
上部、アクティブ層１４及びゲート絶縁膜１３上に形成
される。アクティブ層１４とソース及びドレイン電極１
７-1、１７ -２間にはドーピングされた非晶質シリコン
からなる第１及び第２オーミック層１６-1、１６ -２が
介在され、基板全面にはパッシベーション層１８が形成
される。FIG. 1 is a sectional view showing a general TFT used in an AM-LCD device. Referring to FIG. 1, a gate electrode 12 is formed on a transparent insulating substrate 11 such as glass, and a gate insulating film 13 is formed on the insulating substrate 11 on which the gate electrode 12 is formed. Active layer 14 made of amorphous silicon is formed on gate insulating film 13 to face gate electrode 12. An edge stopper 15 is formed on the active layer 14 above the gate electrode 12.
Source and drain electrodes 17-1 and 17-2 exposing the upper surface of the edge stopper 15 are formed on both sides of the edge stopper 15, on the active layer 14 and the gate insulating film 13. Active layer 14 and source and drain electrodes 1
First and second ohmic layers 16-1 and 16-2 made of doped amorphous silicon are interposed between 7-1 and 17-2, and a passivation layer 18 is formed on the entire surface of the substrate.
【０００４】[0004]
【発明が解決しようとする課題】上記した従来のＴＦＴ
において、ゲート電極１２に一定の電圧が印加されれ
ば、ゲート電極１２上部のアクティブ層１４にチャンネ
ルが誘起され、電流がソース電極１７-1からチャンネル
を通じてドレイン電極１７ -２へ流れる。しかし、電流
はアクティブ層１４のチャンネルだけでなく、チャンネ
ルが誘起されない部分も通過することになる。即ち、図
１に示したように、電流はソース電極１７- １、第１オ
ーミック層１６-1、ソース電極１７ -１下部の活性層１
４、チャンネル、ドレイン電極１７-2下部の活性層１
４、第２オーミック層１６ -２、及びドレイン電極１７
- ２へ流れる。ここで、チャンネルが形成されないアク
ティブ層１４の高い非抵抗によりＴＦＴのオン電流が低
減される。The above-mentioned conventional TFTs
When a certain voltage is applied to the gate electrode 12, a channel is induced in the active layer 14 above the gate electrode 12, and a current flows from the source electrode 17-1 to the drain electrode 17-2 through the channel. However, the current passes not only in the channel of the active layer 14 but also in a portion where the channel is not induced. That is, as shown in FIG. 1, the current is applied to the source electrode 17-1, the first ohmic layer 16-1, and the active layer 1 under the source electrode 17-1.
4. Active layer 1 under channel / drain electrode 17-2
4. Second ohmic layer 16-2 and drain electrode 17
-Flow to 2. Here, the on-state current of the TFT is reduced due to the high non-resistance of the active layer 14 where no channel is formed.
【０００５】また、平面上でアクティブ層１４の面積が
ゲート電極１２の面積より大きいので、アクティブ層１
４がゲート電極１２により完全に遮断されず、アクティ
ブ層１４の一部がバックライト(図示せず )からの光に露
出される。これにより、光に起因する漏洩電流が誘起さ
れてオフ電流が増加される。Since the area of the active layer 14 is larger than the area of the gate electrode 12 on the plane, the active layer 1
4 is not completely blocked by the gate electrode 12, and a part of the active layer 14 is exposed to light from a backlight (not shown). Accordingly, a leakage current due to light is induced, and the off-state current is increased.
【０００６】これにより、上記したＴＦＴを使用するＡ
Ｍ- ＬＣＤ装置に電荷が十分に供給されなくて、結局Ｌ
ＣＤ装置の表示特性が低下される。[0006] Thereby, the A using the TFT described above is used.
The charge is not sufficiently supplied to the M-LCD device.
The display characteristics of the CD device are degraded.
【０００７】従って、本発明の目的は、上記した従来の
問題点を解決するため、ＴＦＴのオン電流を増加させる
と同時にオフ電流を低減させ、ＡＭ- ＬＣＤの表示特性
を向上させることができるＴＦＴを提供することにあ
る。Accordingly, an object of the present invention is to solve the above-mentioned conventional problems by increasing the on-current of the TFT and at the same time reducing the off-current, thereby improving the display characteristics of the AM-LCD. Is to provide.
【０００８】[0008]
【課題を解決するための手段】上記した本発明の目的を
達成するため、本発明に係る薄膜トランジスタは上部に
ゲート電極が形成された透明な絶縁基板を含む。第１ゲ
ート絶縁膜が基板上に形成され、第２ゲート絶縁膜がゲ
ート電極上部の第１ゲート絶縁膜上に形成される。アク
ティブ層がゲート電極のエッジから所定距離をおいて離
隔され第２ゲート絶縁膜上に形成される。第１ゲート絶
縁膜上にアクティブ層の上面を露出させながらアクティ
ブ層の両側と所定部分オーバーラップされる第１及び第
２オーミック層が形成される。第１及び第２オーミック
層上にソース及びドレイン電極が形成され、エッジスト
ッパがゲート電極のエッジから所定距離をおいて離隔さ
れアクティブ層上に形成される。In order to achieve the above object of the present invention, a thin film transistor according to the present invention includes a transparent insulating substrate on which a gate electrode is formed. A first gate insulating film is formed on the substrate, and a second gate insulating film is formed on the first gate insulating film above the gate electrode. An active layer is formed on the second gate insulating film at a predetermined distance from an edge of the gate electrode. First and second ohmic layers are formed on the first gate insulating layer so as to partially overlap both sides of the active layer while exposing an upper surface of the active layer. Source and drain electrodes are formed on the first and second ohmic layers, and an edge stopper is formed on the active layer at a predetermined distance from an edge of the gate electrode.
【０００９】以上に示される本発明の実施の形態におい
ては、アクティブ層はゲート電極のエッジから０．５乃
至１．５μｍに離隔される。In the above embodiment of the present invention, the active layer is separated from the edge of the gate electrode by 0.5 to 1.5 μm.
【００１０】[0010]
【発明の実施の形態】以下、添付の図面を参照しながら
本発明の実施の形態を説明する。図２Ａを参照すれば、
ガラスのような透明な絶縁基板３１上にＭｏＴａ、Ｍｏ
ＷおよびＣｒからなるグループ中から選ばれる一つの金
属膜が２、０００ないし３、０００Åの厚さに蒸着され
パターニングされゲート電極３２が形成される。その
後、図２Ｂに示したように、図２Ａの構造上にＳｉＯｘ
膜からなる第１ゲート絶縁膜３３-１がＰＥＣＶＤ（Pla
smaEnhanced Chemical Vapor Deposition）またはＡＰ
ＣＶＤ(Atmospheric Pressure Chemical Vapor Deposit
ion)により、３、０００乃至５、０００Åの厚さで形成
される。続いて、第１ゲート絶縁膜３３-1上に第１Ｓｉ
Ｎｘ膜３３-２ａ、非晶質シリコン膜３４ａ、および第
２ＳｉＮｘ膜３５ａがＰＥＣＶＤまたはＡＰＣＶＤによ
り順次的に蒸着される。この時、第１ＳｉＮｘ膜３３-
２ａの代りにＳｉＯＮ膜が使われることができ、その厚
さは第１ゲート絶縁膜３３- １に比べて相対的に薄い厚
さ、望ましくは３００Åないし５００Åの厚さで蒸着さ
れる。また、非晶質シリコン膜３４ａは４００Åないし
６００Åの厚さで薄く蒸着され、第２ＳｉＮｘ膜３５ａ
は約３、０００Åの厚さで蒸着される。Embodiments of the present invention will be described below with reference to the accompanying drawings. Referring to FIG. 2A,
MoTa, Mo on a transparent insulating substrate 31 such as glass
One metal film selected from the group consisting of W and Cr is deposited to a thickness of 2,000 to 3,000 ° and patterned to form a gate electrode 32. Thereafter, as shown in FIG. 2B, SiOx is formed on the structure of FIG. 2A.
The first gate insulating film 33-1 made of a film is made of PECVD (Pla
smaEnhanced Chemical Vapor Deposition) or AP
CVD (Atmospheric Pressure Chemical Vapor Deposit
ion) to a thickness of 3,000 to 5,000 degrees. Subsequently, the first Si film is formed on the first gate insulating film 33-1.
The Nx film 33-2a, the amorphous silicon film 34a, and the second SiNx film 35a are sequentially deposited by PECVD or APCVD. At this time, the first SiNx film 33-
An SiON film may be used instead of 2a, and the thickness of the SiON film is relatively thinner than that of the first gate insulating film 33-1. Also, the amorphous silicon film 34a is thinly deposited to a thickness of 400 to 600 degrees, and the second SiNx film 35a is formed.
Is deposited to a thickness of about 3,000 °.
【００１１】図２Ｂ及び図３Ａを参照すれば、第２Ｓｉ
Ｎｘ膜３５ａがゲート電極３２を露光マスクとして利用
する後面露光またはエッジストッパ用マスクパターンを
利用する前面露光によりパターニングされ、ゲート電極
３２上部の非晶質シリコン膜３４ａ上にエッジストッパ
３５が形成される。この時、露光条件はエッジストッパ
３５がゲート電極３２の上部エッジから１．０乃至２．
０μｍ、望ましくは１．５μｍの距離Ｄ１をおいて離隔
されるように調節される。その後、非晶質シリコン膜３
４ａがゲート電極３２を露光マスクとして利用する後面
露光またはアクティブ用マスクパターンを利用する前面
露光によりパターニングされ、ゲート電極３２上部の第
１ＳｉＮｘ膜３３- ２ａ上にアクティブ層３４が形成さ
れる。この時、露光条件はアクティブ層３４がゲート電
極３２の上部エッジから０．５乃至１．５μｍ、望まし
くは１．０μｍの距離Ｄ２をおいて離隔されるように調
節される。これにより、示されていないが、平面上でゲ
ート電極３２内にアクティブ層３４が含まれる。Referring to FIGS. 2B and 3A, the second Si
The Nx film 35a is patterned by rear exposure using the gate electrode 32 as an exposure mask or front exposure using a mask pattern for an edge stopper, and the edge stopper 35 is formed on the amorphous silicon film 34a on the gate electrode 32. . At this time, the exposure condition is such that the edge stopper 35 is 1.0 to 2.... From the upper edge of the gate electrode 32.
It is adjusted to be separated by a distance D1 of 0 μm, preferably 1.5 μm. Then, the amorphous silicon film 3
4a is patterned by back exposure using the gate electrode 32 as an exposure mask or front exposure using an active mask pattern, and an active layer 34 is formed on the first SiNx film 32-2a on the gate electrode 32. At this time, the exposure condition is adjusted such that the active layer 34 is separated from the upper edge of the gate electrode 32 by a distance D2 of 0.5 to 1.5 μm, preferably 1.0 μm. Thus, although not shown, the active layer 34 is included in the gate electrode 32 on a plane.
【００１２】また、アクティブ層３４の形成時、下部層
の第１ＳｉＮｘ膜３３- ２ａが同時にパターニングされ
第２ゲート絶縁膜３３- ２が形成される。この時、第１
ゲート絶縁膜３３-1の厚さが第２ゲート絶縁膜３３ -２
の厚さより相対的に厚いために、第１ゲート絶縁膜３３
-1に対し第２ゲート絶縁膜３３ -２のみをエッチングす
るのに充分なエッチング選択比を確保することができ
る。When forming the active layer 34, the lower first SiNx film 32-2a is simultaneously patterned to form the second gate insulating film 32-2. At this time, the first
The thickness of the gate insulating film 33-1 is equal to that of the second gate insulating film 33-2.
Is relatively thicker than the thickness of the first gate insulating film 33.
An etching selectivity sufficient to etch only the second gate insulating film 33-2 with respect to -1 can be secured.
【００１３】図３Ｂを参照すれば、図３Ａの構造上に、
ドーピングされた非晶質シリコン膜とソース及びドレイ
ン電極用金属膜が順次的に蒸着され、エッジストッパ３
５の上面が露出されるようにパターニングされ、アクテ
ィブ層３４の両側と所定部分オーバーラップされる第１
及び第２オーミック層３６-1、３６ -２と、ソース及び
ドレイン電極３７-1、３７-２とが形成される。その
後、基板全面にＰＥＣＶＤによりパッシベーション層３
８が形成される。Referring to FIG. 3B, on the structure of FIG. 3A,
A doped amorphous silicon film and a metal film for source and drain electrodes are sequentially deposited, and an edge stopper 3 is formed.
5 is patterned so that the upper surface of the first active layer 5 is exposed, and overlaps a predetermined portion with both sides of the active layer 34.
Then, the second ohmic layers 36-1 and 36-2 and the source and drain electrodes 37-1 and 37-2 are formed. Then, a passivation layer 3 is formed on the entire surface of the substrate by PECVD.
8 are formed.
【００１４】[0014]
【発明の効果】上記のようなＴＦＴのおいて、ゲート電
極３２に一定の電圧が印加されれば、アクティブ層３６
にチャンネルが誘起され、電流がソース電極３７- １か
らチャンネルを通じてドレイン電極３７- ２へ流れる。
ここで、アクティブ層３４の全領域にチャンネルが誘起
されるので、ＴＦＴのオン電流が増加する。又、アクテ
ィブ層３４がゲート電極３２により完全に遮断され、ア
クティブ層３４が光に露出されないので、オフ電流が低
減する。In the TFT as described above, if a constant voltage is applied to the gate electrode 32, the active layer 36
And a current flows from the source electrode 37-1 to the drain electrode 37-2 through the channel.
Here, since a channel is induced in the entire region of the active layer 34, the ON current of the TFT increases. Further, since the active layer 34 is completely blocked by the gate electrode 32 and the active layer 34 is not exposed to light, off current is reduced.
【００１５】従って、このようなＴＦＴをスイッチング
素子として使用するＡＭ-ＬＣＤの表示特性が向上され
る。また、本発明は前記実施例に限定されず、本発明の
技術的要旨から逸脱しない範囲内で多様に変形させ実施
できる。Therefore, the display characteristics of an AM-LCD using such a TFT as a switching element are improved. In addition, the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the technical scope of the present invention.
【図面の簡単な説明】[Brief description of the drawings]
【図１】一般的なＴＦＴを示した断面図である。FIG. 1 is a cross-sectional view illustrating a general TFT.
【図２】（Ａ）乃至（Ｂ）は、本発明の実施例に係るＴ
ＦＴの製造方法を説明するための断面図である。FIGS. 2A and 2B show T according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view for explaining a method for manufacturing an FT.
【図３】（Ａ）乃至（Ｂ）は、本発明の実施例に係るＴ
ＦＴの製造方法を説明するための断面図である。FIGS. 3A and 3B are diagrams illustrating T according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view for explaining a method for manufacturing an FT.
３１ 絶縁基板 ３２ ゲート電極 ３３−１ 第１ゲート絶縁膜 ３３−２ 第２ゲート絶縁膜 ３４ アクティブ層 ３５ エッジストッパ ３６−１、３６−２ 第１及び第２オーミック層 ３７−１、３７−２ ソース及びドレイン電極 31 Insulating substrate 32 Gate electrode 33-1 First gate insulating film 33-2 Second gate insulating film 34 Active layer 35 Edge stopper 36-1, 36-2 First and second ohmic layers 37-1, 37-2 Source And drain electrode
Claims (12)
使われる薄膜トランジスタであって、 上部にゲート電極が形成された透明な絶縁基板；前記基
板上に形成された第１ゲート絶縁膜；前記ゲート電極上
部の前記第１ゲート絶縁膜上に形成された第２ゲート絶
縁膜；前記第２ゲート絶縁膜上に形成され前記ゲート電
極のエッジから所定距離をおいて離隔されたアクティブ
層と、前記第１ゲート絶縁膜上に形成され前記アクティ
ブ層の上面を露出させながら前記アクティブ層の両側と
所定部分オーバーラップされた第１及び第２オーミック
層；及び前記第１及び第２オーミック層上に形成された
ソース及びドレイン電極を含むことを特徴とする薄膜ト
ランジスタ。1. A thin film transistor used for an active matrix type liquid crystal display device, comprising: a transparent insulating substrate having a gate electrode formed thereon; a first gate insulating film formed on the substrate; A second gate insulating film formed on the first gate insulating film; an active layer formed on the second gate insulating film and separated by a predetermined distance from an edge of the gate electrode; First and second ohmic layers formed on the film and partially overlapping both sides of the active layer while exposing the upper surface of the active layer; and a source formed on the first and second ohmic layers; A thin film transistor including a drain electrode.
ッジから０．５乃至１．５μｍに離隔されたことを特徴
とする請求項１記載の薄膜トランジスタ。2. The thin film transistor according to claim 1, wherein the active layer is separated from an edge of the gate electrode by 0.5 to 1.5 μm.
なることを特徴とする請求項２記載の薄膜トランジス
タ。3. The thin film transistor according to claim 2, wherein said active layer is made of amorphous silicon.
Ｃｒからなるグループの中で選ばれる一つの物質からな
ることを特徴とする請求項１記載の薄膜トランジスタ。4. The thin film transistor according to claim 1, wherein said gate electrode is made of one material selected from the group consisting of MoTa, MoW, and Cr.
はＳｉＯｘ膜からなることを特徴とする請求項１記載の
薄膜トランジスタ。5. The thin film transistor according to claim 1, wherein the first gate insulating film is formed of a SiON film or a SiOx film.
ないし５,０００Å であることを特徴とする請求項５記
載の薄膜トランジスタ。6. The thickness of the first gate insulating film is 3,000.
The thin film transistor according to claim 5, wherein the thickness is in the range of 5,000 to 5,000 degrees.
ることを特徴とする請求項１記載の薄膜トランジスタ。7. The thin film transistor according to claim 1, wherein the second gate insulating film is a SiNx film.
いし５００Åであることを特徴とする請求項７記載の薄
膜トランジスタ。8. The thin film transistor according to claim 7, wherein the thickness of the second gate insulating film is 300 to 500 degrees.
はＳｉＯｘ膜であり、前記第２ゲート絶縁膜はＳｉＮｘ
膜であることを特徴とする請求項１記載の薄膜トランジ
スタ。9. The first gate insulating film is a SiON film or a SiOx film, and the second gate insulating film is a SiNx film.
The thin film transistor according to claim 1, wherein the thin film is a film.
０乃至５,０００Å であり、前記第２ゲート絶縁膜の厚
さは３００乃至５００Åであることを特徴とする請求項
９記載の薄膜トランジスタ。10. The first gate insulating film has a thickness of 3,000.
10. The thin film transistor according to claim 9, wherein the thickness of the second gate insulating film is in a range of 0 to 5,000 degrees, and the thickness of the second gate insulating film is in a range of 300 to 500 degrees.
ート電極のエッジから所定距離をおいて離隔されたエッ
ジストッパをさらに含むことを特徴とする請求項１記載
の薄膜トランジスタ。11. The thin film transistor according to claim 1, further comprising an edge stopper formed on the active layer and separated from an edge of the gate electrode by a predetermined distance.
極の上部エッジから１．０乃至２．０μｍに離隔された
ことを特徴とする請求項１１記載の薄膜トランジスタ。12. The thin film transistor according to claim 11, wherein the edge stopper is separated from the upper edge of the gate electrode by 1.0 to 2.0 μm.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1997/P27382 | 1997-06-25 | ||
| KR1019970027382A KR100272266B1 (en) | 1997-06-25 | 1997-06-25 | Thin film transistor and method of manufacturing same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11112003A true JPH11112003A (en) | 1999-04-23 |
Family
ID=19511233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10178832A Pending JPH11112003A (en) | 1997-06-25 | 1998-06-25 | Thin film transistor |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH11112003A (en) |
| KR (1) | KR100272266B1 (en) |
| TW (1) | TW388994B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090009728A (en) * | 2007-07-20 | 2009-01-23 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Liquid crystal display device |
| JP2009049384A (en) * | 2007-07-20 | 2009-03-05 | Semiconductor Energy Lab Co Ltd | Light emitting device |
| JP2010129859A (en) * | 2008-11-28 | 2010-06-10 | Hitachi Displays Ltd | Display |
| KR101323539B1 (en) * | 2006-11-27 | 2013-10-29 | 엘지디스플레이 주식회사 | Poly silicon thin film transistor substrate and manufacturing method thereof |
| JPWO2015107606A1 (en) * | 2014-01-15 | 2017-03-23 | 株式会社Ｊｏｌｅｄ | Display device and thin film transistor substrate |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030061586A (en) * | 2002-01-15 | 2003-07-22 | 비오이 하이디스 테크놀로지 주식회사 | Thin film transistor and fabricating method thereof |
| KR20060026278A (en) * | 2004-09-20 | 2006-03-23 | 주식회사 히타치엘지 데이터 스토리지 코리아 | Pick-up driving apparatus for disk drive |
| KR100752367B1 (en) * | 2004-10-22 | 2007-08-27 | 삼성에스디아이 주식회사 | Thin film transistor and method for fabricating thereof |
| KR101824651B1 (en) | 2011-08-30 | 2018-02-02 | 엘지디스플레이 주식회사 | oxide semiconductor thin film transistor and method of manufacturing of the same |
| KR102045730B1 (en) * | 2012-12-28 | 2019-12-03 | 엘지디스플레이 주식회사 | Inverter and driving circuit and display device using the same |
| DE202013008907U1 (en) | 2013-10-07 | 2014-01-21 | Chung-Yen Ho | Combination socket and screwdriver construction |
-
1997
- 1997-06-25 KR KR1019970027382A patent/KR100272266B1/en not_active IP Right Cessation
-
1998
- 1998-06-22 TW TW087110033A patent/TW388994B/en not_active IP Right Cessation
- 1998-06-25 JP JP10178832A patent/JPH11112003A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101323539B1 (en) * | 2006-11-27 | 2013-10-29 | 엘지디스플레이 주식회사 | Poly silicon thin film transistor substrate and manufacturing method thereof |
| KR20090009728A (en) * | 2007-07-20 | 2009-01-23 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Liquid crystal display device |
| JP2009049384A (en) * | 2007-07-20 | 2009-03-05 | Semiconductor Energy Lab Co Ltd | Light emitting device |
| US8896778B2 (en) | 2007-07-20 | 2014-11-25 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| US9142632B2 (en) | 2007-07-20 | 2015-09-22 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| JP2016006549A (en) * | 2007-07-20 | 2016-01-14 | 株式会社半導体エネルギー研究所 | Liquid crystal display device |
| JP2010129859A (en) * | 2008-11-28 | 2010-06-10 | Hitachi Displays Ltd | Display |
| JPWO2015107606A1 (en) * | 2014-01-15 | 2017-03-23 | 株式会社Ｊｏｌｅｄ | Display device and thin film transistor substrate |
| US10204973B2 (en) | 2014-01-15 | 2019-02-12 | Joled Inc. | Display device and thin-film transistors substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100272266B1 (en) | 2000-11-15 |
| TW388994B (en) | 2000-05-01 |
| KR19990003501A (en) | 1999-01-15 |
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