JPH11111948A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve mechanical strength by providing a tubular stacked capacitor having a tapered lower layer electrode, capacitive insulating film on the surface of the lower layer electrode and an upper layer electrode formed on the upper layer electrode through this insulation film. SOLUTION: A manufacturing method comprises the steps of depositing a borophosphatesilicate glass(BPSG) film 2w on an Si substrate 1, annealing it, depositing a CVD Si oxide (TEOS) film 3, patterning after coating a resist, etching the TEOS and the BPSG films 3, 2 respectively, depositing a P-doped first conductive polysilicon (DPS) film 5 and a BPSG film 6, patterning after coating a resist 7, dry etching the BPSG film into a cylindrical shape, and etching to make the pattern of the DPS film 5 laterally thinner than that of the BPSG film 6, thereby improving the mechanical strength while ensuring adequate capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a structure of a cylindrical stack capacitor of a semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the cell size has been reduced and the area of a capacitor has been reduced in accordance with the high integration of DRAM.
Therefore, in order to secure a sufficient capacity, a cylindrical stack capacitor as disclosed in Japanese Patent Application Laid-Open No. 6-196649 is used. This cylindrical stack capacitor is formed by processing a silicon oxide film for electrode shape processing (BPSG film) into a cylindrical shape,
A cylindrical lower electrode is formed around the BPSG film by depositing a phosphorus-doped polysilicon film (hereinafter abbreviated as DPS film) and etching back using anisotropic etching. After that, the BPSG film is removed by gas phase HF treatment, and both the inside and outside of the lower electrode are used as electrodes of the capacitor.

[0003] Such a structure is an important structure that is very effective in ensuring a sufficient surface area of the electrode and a sufficient capacity even if the cell area is reduced.

[0004]

[Problems to be Solved by the Invention] However, 64Mbit
In the case of DRAM (third generation), the cell size is expected to be 1 μm ² or less, and in order to secure sufficient capacity, the height of the cylindrical lower electrode becomes 500 nm or more, while the thickness of the lower electrode increases. Is expected to be around 100 nm. At this time, the pattern of the silicon oxide film (BPSG film) for electrode shape processing is thinned during hydrofluoric acid (HF) treatment included in the cleaning process, and the lower portion has a forward taper, and the lower electrode lower portion formed by using it is reverse tapered. And a constriction of about 40 nm is formed. This is not negligible compared to the thickness, and leads to a problem of a decrease in mechanical strength such that the lower part of the lower electrode is broken during cleaning and the capacitor falls.

As a method of improving the mechanical strength, a method of increasing the thickness or lowering of the lower electrode, or a method of reducing the B and P concentrations of the BPSG film to reduce the thinning due to hydrofluoric acid treatment are considered. Can be However, in order to increase the thickness of the lower layer electrode, it is necessary to secure a space corresponding to the thickness, and it is necessary to reduce the capacity or increase the cell size. Also, when the height of the lower electrode is reduced, the capacity is reduced. These methods are undesirable because they go against the direction of current development.

In the method of lowering the B and P concentrations of the BPSG film, the etching selectivity in the gas phase HF treatment step for removing the BPSG film is reduced, and the underlying CVD silicon oxide film (hereinafter abbreviated as TEOS film) is obtained. Is rough. If the roughness of the TEOS film is large, then in the process of forming the NO film of the capacitance insulating film,
A portion where the nitride film does not deposit on the TEOS film surface, that is, a pinhole of the nitride film is generated. After that, nitride oxidation is performed.At this time, oxygen diffuses through the pinhole of the nitride film, diffuses in the TEOS film and the oxide film between the layers under the TEOS film, and converts the silicide film used for wiring to an oxygen atmosphere. The problem of exposure to oxidation occurs.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device capable of securing a sufficient capacity and improving mechanical strength and preventing a TEOS film from being roughened, and a method of manufacturing the same.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor memory device, comprising: a cylindrical lower electrode having a forward tapered lower inner periphery; a capacitor insulating film provided on a surface of the lower electrode; A cylindrical stack capacitor having an upper electrode provided on a lower electrode with an insulating film interposed therebetween is provided.

Note that a silicon film containing impurities is used as the lower electrode. According to the semiconductor memory device of the first aspect, since the lower portion of the lower periphery of the lower electrode has a forward taper, there is no problem that the lower portion of the lower electrode is broken and the capacitor falls down, and the mechanical strength is improved while securing sufficient capacity. it can. According to a third aspect of the present invention, in the method of manufacturing a semiconductor memory device, a first conductive film is deposited on a silicon oxide film laminated on a substrate, and a pillar-shaped electrode forming silicon oxide film is deposited on the first conductive film. And
The first conductive film is etched so as to be thinner in the lateral direction than the silicon oxide film for electrode shaping, a reverse taper is formed below the silicon oxide film for electrode shaping, a second conductive film is deposited, and the second conductive film is deposited. Etching the conductive film to form a cylindrical lower electrode around the silicon oxide film for electrode shape processing, removing the silicon oxide film for electrode shape processing, forming a capacitive insulating film,
An upper electrode is formed by depositing a third conductive film to form a cylindrical stacked capacitor.

As a method of etching the first conductive film so as to be thinner in the lateral direction than the silicon oxide film for processing the electrode shape, the first conductive film is formed by vertically patterning the silicon oxide film for processing the electrode shape using anisotropic etching. A method in which the first conductive film is thinned in the lateral direction using anisotropic etching, and the first conductive film is vertically etched using anisotropic etching, or an electrode shape processing is performed using anisotropic etching. There is a method of vertically patterning a silicon oxide film for use and a first conductive film thereunder and then narrowing the first conductive film in the lateral direction by using isotropic etching.

The lower part of the silicon oxide film for processing the electrode shape may be reverse tapered by hydrofluoric acid treatment, and the silicon oxide film for processing the electrode shape may be removed by gas phase HF processing. Note that a silicon film containing impurities is used as the first conductive film. As the silicon oxide film for electrode shape processing, silicate glass containing boron and / or phosphorus is used. Further, a silicon film containing impurities is used as the lower electrode.

According to the method of manufacturing a semiconductor memory device of the present invention, the first conductive film below the silicon oxide film for processing the electrode shape is etched to narrow in the horizontal direction, and then the silicon for processing the electrode shape is formed. By providing a reverse taper at the lower portion of the oxide film, the lower inner peripheral portion of the cylindrical lower electrode formed around the silicon oxide film for electrode shape processing has a forward taper. Accordingly, there is no problem that the lower part of the lower electrode is broken and the capacitor falls down, and the mechanical strength can be improved while securing sufficient capacity.

In the method of manufacturing a semiconductor memory device according to the present invention, the silicon oxide film for electrode shaping is removed by vapor phase HF treatment, and then the silicon oxide film for non-electrode shaping is subjected to hydrofluoric acid treatment. It is characterized by applying. The silicon oxide film not used for electrode shape processing may be etched by a total of 30 nm or more by the gas-phase HF treatment and the hydrofluoric acid treatment.

According to the method of manufacturing a semiconductor memory device according to the eighth and ninth aspects, it is possible to alleviate the roughness of the underlying silicon oxide film not used for processing the electrode shape by performing the hydrofluoric acid treatment after the gas phase HF treatment. In addition, the mechanical strength can be improved while suppressing the oxidation of the silicide film and securing a sufficient capacity.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an overall structure of a semiconductor memory device including a transistor and a capacitor. In FIG. 1, 1 is a silicon substrate, 2 is an interlayer film, 11 is a cylindrical stack capacitor, 12 is a LOCOS oxide film, 13 and 14 are interlayer films, 15 and 16 surface protection films, 17
Is a metal wiring, 18 is a memory cell transistor, 1
9, 20 are polycide wirings, 21, 22, 23, 24 are contacts, and 25, 26, 27 are peripheral circuit transistors.

FIG. 2 is a sectional view of a circular cylindrical stack capacitor 11 of the semiconductor memory device. The manufacturing process of the cylindrical stack capacitor 11 will be described with reference to FIGS. First, as shown in FIG. 3, a 800 nm borophosphosilicate glass film (hereinafter abbreviated as BPSG film) 2 was deposited on a silicon substrate 1 and annealed at 800 ° C. for 30 minutes in nitrogen. On top of this, a 200 nm CVD silicon oxide film (hereinafter abbreviated as TEOS film) 3 was deposited by LVCVD. A resist 4 is applied thereon and patterned, and then the TEOS film 3 and the BP are dry-etched as shown in FIG.
The SG film 2 was etched.

Thereafter, as shown in FIG. 5, a P of 1.5E20 / cm ³
A phosphorus-doped polysilicon film (hereinafter, abbreviated as DPS film) 5 serving as a first conductive film doped with P is deposited by LPCVD.
Deposited 00nm, B concentration 3.8wt%, P concentration 5.5wt%
Was deposited to a thickness of 700 nm. A resist 7 was applied thereon and patterned. Using this as a mask, first, as shown in FIG. 6, the BPSG film 6 was dry-etched and processed into a cylindrical shape. This BPSG film 6 is used for electrode shape processing.

Next, the pattern of the DPS film 5 was etched so as to be thinner in the lateral direction than the pattern of the BPSG film 6 using isotropic etching using Cl ₂ plasma, as shown in FIG. Other isotropic etching methods at this time include a wet etching method using 0.5% HF and 45% nitric acid and a dry etching method using Cl ₂ and SF ₆ plasma. Further, it can be combined with an anisotropic etching method using HBr, Cl ₂ plasma. For example, after the BPSG film 6 is vertically patterned using anisotropic etching, the DPS film 5 is thinned in the horizontal direction using isotropic etching, and the DPS film 5 is vertically drawn using anisotropic etching. BPSG using anisotropic etching
There is a method of vertically patterning the film 6 and the underlying DPS film 5 and then narrowing the DPS film 5 in the lateral direction using isotropic etching. Thereafter, when a hydrofluoric acid treatment was performed for HF: H ₂ O = 1: 250 for 180 seconds, the lower portion of the BPSG film (silicon oxide film for electrode shape processing) 6 became an inverse taper 6 ′ as shown in FIG.

In the etching of the DPS film 5, a wafer which was not subjected to isotropic etching for comparison but was subjected only to anisotropic etching using HBr and Cl ₂ plasma was also prepared. did. Comparative Example 1 A phosphorus-doped polysilicon film (DPS film) 8 serving as a second conductive film was further deposited thereon to a thickness of 100 nm as shown in FIG. 9, and the DPS film 8 was subjected to anisotropic etching. This
Although the DPS film 8 above the BPSG film 6 and the TEOS film 3 was removed, the cylindrical DPS film 8 around the BPSG film 6 remained with a gentle upper corner as shown in FIG. The remaining side wall portion is hereinafter referred to as a lower electrode 8 '.

Next, the BPSG film (silicon oxide film for electrode shape processing) 6 was removed by using a gas phase HF treatment to form a cylindrical lower electrode 8 'as shown in FIG. At this time, the lower portion of the inner periphery of the lower electrode 8 'had a forward taper 8 ". The TEOS film 3 was roughened by the gas phase HF treatment.
₂ O = 1: Hydrofluoric acid treatment was performed for 100,120 seconds. Also, here, for comparison, a wafer treated in the same manner as described above without performing the hydrofluoric acid treatment was prepared. (Comparative Example 2) A wafer having a forward taper 8 ″ at the lower portion of the inner periphery of the lower electrode 8 ′ had no problem that the lower portion of the lower electrode 8 ′ was broken during hydrofluoric acid treatment or subsequent cleaning, and the capacitor fell. However, for comparison, a wafer in which the isotropic etching was not performed by etching the DPS film 5 (Comparative Example 1) had the lower portion of the lower electrode broken several times in a 128 kbit block and the capacitor fell. From this, it was confirmed that the mechanical strength was improved by forming the forward taper 8 ″ below the lower electrode 8 ′.

On this, a capacitor insulating film 9 of a NO film was formed.
At this time, oxidation of the silicide film used for the bit line and the word line was not observed on the wafer subjected to the hydrofluoric acid treatment after removing the BPSG film (silicon oxide film for electrode shape processing) 6 by the gas phase HF treatment. . However, oxidation of the silicide film was observed on the wafer not subjected to the hydrofluoric acid treatment (Comparative Example 2).

Further, a 200 nm thick phosphorus-doped polysilicon film (DPS film) serving as a third conductive film is deposited and processed to form an upper electrode 10, thereby forming a cylindrical stack capacitor 11 as shown in FIG. did. When the operation of the memory cell using the cylindrical stack capacitor 11 configured as described above was confirmed, a sufficient capacity of 32 fF could be secured per cell. In addition, since normal operation was confirmed for all bits, it was again confirmed that the mechanical strength was improved and the capacitor did not fall.

As the silicon oxide film 6 for processing an electrode shape, a silicate glass containing only one of boron and phosphorus may be used. Further, the TEOS film 3 may be etched by a total of 30 nm or more by the gas phase HF treatment and the hydrofluoric acid treatment. Further, the cylindrical stack capacitor 11 is not limited to a cylindrical type, but may be any type as long as it is a cylindrical type.

[0024]

According to the semiconductor memory device of the present invention, since the lower portion of the lower portion of the lower electrode has a forward taper, there is no problem that the lower portion of the lower electrode is broken and the capacitor falls down, and a sufficient capacity is secured. The mechanical strength can be improved. According to the method of manufacturing a semiconductor memory device according to claim 3, after the first conductive film below the silicon oxide film for processing an electrode shape is etched to narrow in the horizontal direction, the silicon oxide film for processing an electrode shape is formed. By forming a reverse taper on the lower portion, the lower portion of the inner periphery of the cylindrical lower electrode formed around the silicon oxide film for electrode shape processing has a forward taper. Accordingly, there is no problem that the lower part of the lower electrode is broken and the capacitor falls down, and the mechanical strength can be improved while securing sufficient capacity.

According to the method of manufacturing a semiconductor memory device according to the eighth and ninth aspects, it is possible to alleviate the roughness of the underlying silicon oxide film not used for processing the electrode shape by performing the hydrofluoric acid treatment after the gas phase HF treatment. In addition, the mechanical strength can be improved while suppressing the oxidation of the silicide film and securing a sufficient capacity.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a step of manufacturing the cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

FIG. 4 is a cross-sectional view showing a step of manufacturing the cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

FIG. 5 is a cross-sectional view showing a step of manufacturing the cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a step of manufacturing the cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a step of manufacturing the cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a step of manufacturing the cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

FIG. 9 is a cross-sectional view showing a step of manufacturing the cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

FIG. 10 is a sectional view illustrating a manufacturing process of the cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

FIG. 11 is a cross-sectional view showing a step of manufacturing the cylindrical stacked capacitor in the semiconductor memory device according to one embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 BPSG film 3 TEOS film (silicon oxide film) 4 resist 5 DPS film (first conductive film) 6 BPSG film (silicon oxide film for electrode shape processing) 6 'reverse taper 7 resist 8 DPS film (second 8 'lower layer electrode 8 "forward taper 9 capacitive insulating film 10 upper layer electrode (third conductive film) 11 cylindrical stack capacitor

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Keiichi Matsunaga 1-1, Komachi, Takatsuki City, Osaka Prefecture Matsushita Electronics Corporation

Claims (13)

[Claims] 1. A cylindrical lower electrode having a forward tapered lower portion on an inner periphery, a capacitor insulating film provided on a surface of the lower electrode, and an upper electrode provided on the lower electrode with the capacitor insulating film interposed therebetween. A semiconductor memory device comprising a cylindrical stack capacitor having: 2. The semiconductor memory device according to claim 1, wherein a silicon film containing impurities is used as the lower electrode. 3. The method according to claim 1, wherein a first layer is formed on the silicon oxide film laminated on the substrate.
A step of depositing a conductive film, a step of depositing a pillar-shaped electrode forming silicon oxide film on the first conductive film, and a step of moving the first conductive film laterally from the electrode shape processing silicon oxide film. Etching in a direction narrowing, forming a reverse taper on a lower portion of the silicon oxide film for electrode shape processing, depositing a second conductive film, and etching the second conductive film. Forming a cylindrical lower electrode around the electrode shaping silicon oxide film, removing the electrode shaping silicon oxide film, forming a capacitive insulating film, and forming a third conductive film. Depositing to form an upper electrode to form a cylindrical stacked capacitor. 4. After forming a silicon oxide film for electrode shape processing vertically by using anisotropic etching, the first conductive film is thinned in the lateral direction by using isotropic etching. 4. The method according to claim 3, wherein the first conductive film is vertically etched by etching. 5. A silicon oxide film for processing an electrode shape and a first conductive film thereunder are vertically formed by using anisotropic etching, and then the first conductive film is laterally formed by using isotropic etching. 4. The method for manufacturing a semiconductor memory device according to claim 3, wherein the width is reduced in a direction. 6. The method of manufacturing a semiconductor memory device according to claim 3, wherein a reverse taper is formed at a lower portion of the silicon oxide film for electrode shape processing by hydrofluoric acid treatment. 7. A silicon oxide film for processing an electrode shape is formed by vapor phase H.
4. The method according to claim 3, wherein the semiconductor device is removed by an F process. 8. A silicon oxide film for electrode shape processing is formed of a gaseous phase H
A method for manufacturing a semiconductor memory device having a cylindrical stack capacitor, wherein a silicon oxide film not used for electrode shape processing is subjected to a hydrofluoric acid treatment after being removed by an F treatment. 9. The method according to claim 9, wherein the silicon oxide film for electrode shape processing is formed of a gas phase H.
8. The method of manufacturing a semiconductor memory device according to claim 7, wherein after the removal by the F treatment, the silicon oxide film not used for electrode shape processing is subjected to a hydrofluoric acid treatment. 10. The method according to claim 3, wherein a silicon film containing impurities is used as the first conductive film. 11. The method according to claim 3, wherein a silicate glass containing boron and / or phosphorus is used as the silicon oxide film for electrode shape processing. 12. The method according to claim 3, wherein a silicon film containing impurities is used as the lower electrode. 13. The method for manufacturing a semiconductor memory device according to claim 8, wherein a silicon oxide film not used for electrode shape processing is etched by a total of 30 nm or more by vapor phase HF treatment and hydrofluoric acid treatment.