JPH11111944A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate operating speed without increasing the division number of a sub word line, in a hierarchical word line structure. SOLUTION: A sub array S1 for which a memory array of 8 Mbits is divided by the memory capacity of a 128 Mbit unit is provided on a right side with the center part of a memory array 2 as a boundary, and a sub array S2 for which the memory array of 8 Mbits is divided by the memory capacity of a 64 Kbit unit is provided on the left side. The sub array S2 of the 128 Kbit unit on the left side of the memory array 2 realizes acceleration since the wiring length of the sub word line is shortened, and the sub array S1 positioned on the right side of the memory array 2 substantially reduces the number of sub word drivers SWDs. Also, since the sub array S1 is close to a main word driver MWD, a problem will not occur in the delay of access time, and the area of a semiconductor chip CH is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a DRAM (Dynamic Ramd).
Om Access Memory (DWD: Divided Word Drive)
er) The present invention relates to a technique which is effective when applied to the area saving of a semiconductor chip having a structure.

[0002]

2. Description of the Related Art According to studies made by the present inventors, for example, a large-capacity DRAM (Dynamic Ramd) has been proposed.
om Access Memory) or the like, and a hierarchical word line (DWD: Divided Word Dr)
The iv) configuration employs a hierarchical structure in which one word line is divided into a plurality of sub-word lines in the row direction, and the plurality of word lines are controlled by a set of main word lines having a complementary relationship.

As an example describing this type of semiconductor integrated circuit device in detail, see, for example, Baifukan Co., Ltd., 19
Published on November 5, 1994, "Advanced Electronics I-9 Ultra LSI Memory" Kiyoo Ito (Author), P142
This document describes the circuit configuration of a readout circuit in a DRAM.

[0004]

However, the present inventor has found that the semiconductor integrated circuit device having the hierarchical word line structure as described above has the following problems.

That is, in order to increase the operation speed,
It is necessary to shorten the wiring length of the sub-word line and increase the number of divisions, and accordingly, the number of sub-word drivers for driving the sub-word line also increases, which hinders high integration of the semiconductor integrated circuit device. There is a problem that there is.

An object of the present invention is to provide a semiconductor integrated circuit device capable of increasing the operation speed without increasing the number of sub word lines divided in a hierarchical word line structure.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device of the present invention, the memory array includes at least two sub-array regions each including a plurality of sub-arrays divided into different memory capacities for each region. The memory capacity of the sub-array decreases as the distance from the main word driver that drives the main word line of the memory array decreases.

Thus, the number of sub-word drivers can be reduced in the sub-array region near the main word driver without signal delay, and the wiring length of the sub-word line can be reduced in the sub-array region far from the main word driver. High-speed access can be performed.

Further, in the semiconductor integrated circuit device according to the present invention, the sub-array region includes two regions, and a plurality of sub-arrays formed in each of the sub-array regions have the same memory capacity.

Further, according to the semiconductor integrated circuit device of the present invention,
The sub-array region includes three regions, and a plurality of sub-arrays formed in each sub-array region have the same memory capacity.

Accordingly, since the sum of the memory capacities of the respective areas is the same, the control of the memory array can be easily performed.

As described above, since the area of the semiconductor chip can be reduced, the size of the semiconductor integrated circuit device can be further reduced.
In addition, the operation of the semiconductor integrated circuit device can be speeded up.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of a layout of a semiconductor chip in a memory having a hierarchical word line structure according to an embodiment of the present invention, and FIG. 2 is a memory having a hierarchical word line structure according to an embodiment of the present invention. FIG. 3 is a timing chart of a data read operation of a memory in a memory having a hierarchical word line structure according to an embodiment of the present invention, and FIG. 4 is a hierarchical word line structure according to an embodiment of the present invention. 5 is a timing chart at the time of a memory refresh operation in the memory of FIG.

In this embodiment, a 64 Mbit DR
As shown in FIG. 1, the layout configuration of a memory (semiconductor integrated circuit device) 1 having a hierarchical word line structure, which is an AM, is a semiconductor chip CH having semiconductor elements formed on a semiconductor wafer such as single crystal silicon. A peripheral circuit SC is formed at the center in the long side direction.

The peripheral circuit SC has a column decoder for selecting a bit line in a column direction, an address buffer for receiving an address signal in a row and a column direction, generating and outputting an internal address signal, and an input buffer. It comprises a data input buffer that takes in at a predetermined timing, a data output buffer that outputs output data at a predetermined timing, and a boosting power supply circuit that generates a boosting power supply voltage used for the word line potential.

In the memory 1, the upper and lower stages of the peripheral circuit SC are memory cell array regions,
A memory array 2 is provided in which memory cells for storing one bit of binary information are two-dimensionally arranged in a matrix structure.

Further, the memory array 2 is divided into four every 16M bits, and two memory arrays 2 are located in the upper longitudinal direction of the semiconductor chip CH, and also in the lower longitudinal direction of the semiconductor chip CH. Similarly, two memory arrays 2 are provided so as to be located.

Each memory array 2 is provided with a main word driver MWD for driving a main word line in the memory array 2. These main word drivers MWD are provided in the above-mentioned upper and lower memory cell array regions. It is formed so as to be located at the center, that is, between the two memory arrays 2.

Further, as shown in FIG. 1, the memory array 2 is a memory array 2 of 16 Mbits.
In the vicinity of the main word driver MWD, that is, on the right side of the center of the memory array 2, there is provided a subarray S <b> 1 obtained by dividing an 8 Mbit memory array by a memory capacity of 128 Kbit units.

On the other hand, at a position far from the main word driver MWD, that is, on the left side of the center of the memory array 2, a sub-array S2 obtained by dividing an 8-Mbit memory array by a memory capacity of 64K bits is provided. Is configured.

Therefore, the sub-array S1 has a configuration of 256 words.times.512 bits. In order to obtain 8M bits by this configuration, four sub-arrays S1 in the long side direction and 16 sub-arrays in the short side direction of the semiconductor chip CH are used. Are provided, and the area where these sub-arrays S1 are located is a sub-array area.

The sub-array S2 has 256 words ×
A 256-bit configuration is used. In order to obtain 8 Mbits by this configuration, eight semiconductor chips CH are arranged in the long side direction.
16 sub-arrays S2 are provided in the short side direction, and similarly, the area where these sub-arrays S2 are located is the sub-array area.

Next, a sub-word driver SWD for driving a plurality of sub-word lines divided in the row direction is located at both side ends of the sub-arrays S1 and S2. A sense amplifier SA for reading and amplifying a signal is provided at a position.

Each memory array 2 has a sub-array S on the right side with respect to the center of the memory array 2.
1 is located so that the sub-array S2 is located on the left side, so that the signal length of the main word line becomes longer, so that the far end of the memory array 2 can shorten the wiring length of the sub-word line of the sub-array S2, thereby increasing the speed. Can be realized.

Since the right side of the memory array 2 can be constituted by the sub-array S1, all of the sub-array S2
Sub-word driver SWD significantly
And the sub-array S1 is close to the main word driver MWD, so that the area of the semiconductor chip CH can be reduced without causing a problem in access time delay.

Next, a circuit diagram of the memory 1 having a hierarchical word line structure is shown in FIG. Here, FIG. 2 shows only one mat each of the above-described sub-array S1 having a configuration of 256 words × 512 bits and the sub-array S2 having a configuration of 256 words × 256 bits, and peripheral circuits thereof.

First, in FIG. 2, a memory 1 includes a main word driver MWD for driving a main word line MWL.
Sub-word driver SWD driving sub-word line SWL electrically connected to main word line MWL
Is provided. Also, the sub word driver SWD
Are also electrically connected to the selection drive lines FX and FXB, which are predecode signals.

Then, the selected main word line MWL
Sub-word driver SWD at the point of intersection between the sub-word driver SWD and the selected drive line FX, FXB is activated.
Will rise.
The other sub-word drivers SWD are inactive, and the unselected sub-word lines SWL are connected to the ground potential Vss.
It is fixed to.

Here, the far end of the main word line MWL,
That is, the sub-word driver SW of the sub-array S2 (FIG. 1) located farthest from the main word driver MWD.
D will be selected the latest, but the sub-array S2
In (2), since the wiring length of the sub-word line SWL is short, the signal transmission, that is, the rising timing of the signal can be accelerated.

On the other hand, the main word driver MWD
, Ie, the sub-word driver SWD provided in the sub-array S1 has a fast selection timing, so that the sub-word line SW
Access can be performed at high speed even if the wiring length of the WL is long.

Next, FIG. 3 shows a timing chart at the time of the read operation in the memory 1.

First, in the timing chart of FIG. 3, the signal timings of the main word line MWL, the selection drive lines FX and FXB, the sub word line SWL, the sense amplifiers SAP and SAN, and the bit line BL are shown from top to bottom. Here, for example, the word line voltage is set to the boosted level Vch.

In FIG. 3, the timing of the sub word line SWL is determined by the main word line MWL and the selection drive line F.
X and FXB, and are determined by the sense amplifiers SAP and SAP after a signal is output to the bit line BL.
Activate the AN and perform amplification.

The sub-word line SWL in the sub-array S2 located at the far end of the main word driver MWD
Since the main word line MWL has a long wiring length (shown by a dotted line), its rising timing is later than that of the sub-word line SWL (shown by a solid line) of the sub-array S1 located near the main word driver MWD.

However, the sub-word line S of the sub-array S2
In WL, as described above, 256 words × 256
Because of the bit configuration, the wiring length of the sub-word line SWL is short, and the fall time of the signal is short. Meanwhile, 2
The sub-word line SWL in the sub-array S1 having a configuration of 56 words × 512 bits has a long wiring length, so the fall time of the signal is also long, and finally the sub-word line SWL of the sub-array S1 and the sub-word line SWL of the sub-array S2 are At the same timing.

Next, FIG. 4 shows a timing chart at the time of the refresh operation in the memory 1.

Similarly, in the timing chart of FIG. 4, the main word line MW
L, signal drive timings of select drive lines FX and FXB, sub-word lines SWL, sense amplifiers SAP and SAN, and bit lines BL.

In FIG. 4, even in this case, the memory cell can be refreshed by activating the sub-word line SWL as in the read operation. Further, in the memory 1, the refresh operation is performed for each main word line. As shown in FIG. 4, even if the array division unit is two types, the refresh operation is not affected, and control can be performed in the same manner as in the case of one array division.

Thus, according to the present embodiment, the access time is shortened by the sub-array S2 in which the wiring length of the sub-word line SWL is shortened by dividing the memory array 2 to the left with respect to the central portion thereof in units of 64 K bits and shortening the wiring length. There is no problem in the access time because it is close to the main word driver MWD.
The number of sub-word drivers can be reduced by the sub-array S1 divided in units of 8K bits, and the area of the semiconductor chip CH can be reduced.

Further, in the present embodiment, two sub-array regions including sub-arrays S1 and S2 having different memory capacities have been described. However, the sub-array region includes three or more regions where sub-arrays having different memory capacities are formed. It may be provided.

For example, as shown in FIG. 5, in a memory 1 having a hierarchical word line structure which is a 64-Mbit DRAM, a sub-array S having a memory capacity of 256 K bits is provided.
The access time can be shortened by dividing the sub-array area into M1, a sub-array area of a sub-array SM2 having a memory capacity of 128 Kbits, and a sub-array area of a sub-array SM3 having a memory capacity of 64 Kbits, and the semiconductor chip CH Can be reduced in area.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0046]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the number of sub-word drivers can be reduced in the sub-array area near the main word driver without signal delay, and the wiring length of the sub-word line in the sub-array area far from the main word driver can be reduced. Since it can be shortened, high-speed access can be performed.

(2) In the present invention, the memory array can be easily controlled by making the sum of the memory capacities of the respective regions the same.

(3) Further, according to the present invention, since the area of the semiconductor chip can be reduced by the above (1) and (2), the size of the semiconductor integrated circuit device as a product can be further reduced and the semiconductor integrated circuit device can be reduced. Operation can be speeded up.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a layout of a semiconductor chip in a memory having a hierarchical word line structure according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a memory having a hierarchical word line structure according to an embodiment of the present invention;

FIG. 3 is a timing chart of a data read operation of the memory in the memory having the hierarchical word line structure according to the embodiment of the present invention;

FIG. 4 is a timing chart at the time of a memory refresh operation in a memory having a hierarchical word line structure according to an embodiment of the present invention;

FIGS. 5A and 5B are explanatory diagrams of a layout of a semiconductor chip in a memory having a hierarchical word line structure according to another embodiment of the present invention.

[Description of Signs] 1 Memory (Semiconductor Integrated Circuit Device) 2 Memory Array CH Semiconductor Chip SC Peripheral Circuit MWD Main Word Driver SWD Subword Driver S1, S2 Subarray SA Sense Amplifier MWL Main Word Line SWL Subword Line FX, FXB Selection Drive Line SM1 ~ SM3 subarray

Claims (3)

[Claims] 1. A semiconductor integrated circuit device having a hierarchical word line configuration in which word lines are divided into multiple parts, wherein a memory array is composed of a plurality of sub-arrays divided into different memory capacities for respective areas. A semiconductor integrated circuit device, comprising at least two sub-array regions, wherein a memory capacity of the sub-array in the sub-array region decreases as the distance from a main word driver for driving a main word line of the memory array decreases. 2. The semiconductor integrated circuit device according to claim 1, wherein said sub-array region comprises two regions, and said plurality of sub-arrays formed in each of said sub-array regions have the same memory capacity. Semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein said sub-array region includes three regions, and said plurality of sub-arrays formed in each of said sub-array regions have the same memory capacity. Semiconductor integrated circuit device.