JPH11111935A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce turn-around time(TAT) by moving down the ROM code write step to a later step as much as possible. SOLUTION: After the formation of a photoresist step of etching a layer insulation film 59 to form contact holes at drain regions, an Al material is deposited and photoresist step is applied to form a wiring 68 contacted to the drain regions via the contact holes. Then when a ROM code support is provided, a ROM coding mask is formed. When P ions are implanted to form n-channel diffused regions 73 at gate electrode parts 44 of selected transistors in a mask ROM 43, thus completing the ROM code write and greatly reducing TAT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique effective when applied to a one-chip microcomputer having a built-in EEPROM and a mask ROM as nonvolatile semiconductor memory devices. ,
The present invention relates to a technique for shortening a TAT (Turn Around Time) by deferring an impurity ion implantation step for writing a ROM code of a mask ROM after a wiring forming step of an EEPROM.

[0002]

2. Description of the Related Art Looking at recent one-chip microcomputers, as a nonvolatile semiconductor memory device for storing program data, an EEPROM is used instead of a mask ROM.
The tendency to incorporate is growing. This is an EEPROM
Has features not found in the mask ROM. For example,
When changing the function of a one-chip microcomputer,
If a mask ROM is used, a new mask must be designed and manufactured. Therefore, there are problems such as a high development cost and a long development period. On the other hand, if the EEPROM is used, new program data can be written using a PROM writer or the like after the old program data is electrically erased, so that the development cost can be reduced and the development period can be shortened.

A general one-chip microcomputer having such a nonvolatile semiconductor memory device will be described with reference to the drawings. First, FIG. 16 shows a configuration in which the ROM of the microcomputer is replaced with an EEPROM. As shown in FIG.
Is composed of a program area 12, a data area 13, and a control circuit 14, and 15 is a core unit including, for example, a CPU, an I / O port, and the like. Here, when the ROM of the one-chip microcomputer is simply replaced with the EEPROM as in the configuration shown in FIG. 16, access to the entire EEPROM is prohibited during the data rewriting operation of the EEPROM, and the microcomputer must read the program to be executed. Run out of control and run away.

In order to avoid this, as shown in FIG. 17, it is conceivable to provide a plurality of independent EEPROMs 17 and 18 as compared with the one-chip microcomputer shown in FIG. The first EEPROM 17 stores the program area 1
9 and a control circuit 20, and a second EEPROM 18
Is a configuration having a data area 21 and a control circuit 22,
23 is a core part.

[0005] In this case, however, a plurality of control circuits occupying a relatively large area as shown in FIG. 17 are required, which causes a problem in cost. Therefore, as shown in FIG.
It is conceivable to use an EEPROM 24 as a nonvolatile memory and a mask ROM 25 as a second nonvolatile memory. The EEPROM 24 has a first program area 26, a data area 27, and a control circuit 28, and the mask ROM 25 has a second program area 2
9, and 30 is a core part.

[0006] The mask ROM 25 stores the EEPR.
A data rewriting program of the OM 24 is stored. Then, only the data rewriting program of the EEPROM 24 required by all users is mounted on the mask ROM 25, and rewriting by the users is disabled. As a result, a data rewriting program for the EEPROM 24 is prepared in the mask ROM, and
Even if the M24 data is rewritten and access to the entire EEPROM 24 is prohibited, the microcomputer can execute the program on the mask ROM.

As described above, regarding the one-chip microcomputer, the mask ROM and the E
There is a structure in which EPROM is mixed. Hereinafter, the RO of the mask ROM in a one-chip microcomputer having such a structure in which the mask ROM and the EEPROM are mixedly mounted will be described.
The M code writing process will be described with reference to the drawings.

First, in FIG. 19, a pad oxide film 32 having a thickness of about 500.degree. Is formed by thermally oxidizing the surface of a semiconductor substrate 31, and a silicon nitride film 33 having a thickness of about 2000.degree. Form. This silicon nitride film 33 is patterned by a photoresist process to form an opening 34. In FIG. 20, after removing the photoresist film (not shown), the entire substrate 31 is subjected to steam oxidation at 1000 ° C. for several hours, so that the LOCOS for element isolation is formed in the opening 34 of the silicon nitride film 33.
An oxide film 35 is formed.

In FIG. 21, the silicon nitride film 33 used for the selective oxidation is removed, and the pad oxide film 32 thereunder is further removed by a hydrofluoric acid buffer solution to clean the surface of the substrate 31. Thickness 100 by sufficient dry oxidation
A first gate oxide film 36 of about {200} is formed. Further, on the first gate oxide film 36, a non-doped polysilicon film 37 having a thickness of about 1,000 to 2,000 is formed by a low pressure CVD method.

In FIG. 22, phosphorus (P) is applied to a polysilicon film 37 at an acceleration voltage of 40 KeV and a dose of 1.0 × 10 3.
Conductivity is given to the polysilicon film 37 by ion implantation under the condition of 15 / cm 2, and then a silicon nitride film 38 having a thickness of about 2000 ° is formed by the low pressure CVD method.
Further, the silicon nitride film 38 is patterned by a photoresist process to form an opening 39 of the silicon nitride film 38.

In FIG. 23, the entire substrate 31 is 900
By heat treatment in an oxidizing atmosphere for 1 hour
The polysilicon film 37 is selectively oxidized to form a selective oxide film 40 on the surface of the opening 39. The selective oxide film 40 is formed in such a shape that the film thickness is large at the central portion and thin at the peripheral portion. 24, after the silicon nitride film 38 used for selective oxidation is removed, the polysilicon film 37 is anisotropically etched using the selective oxide film 40 as a mask to form the floating gate 42 of the EEPROM 41. At this stage, the first gate oxide film 36 may be left.

In FIG. 25, NSG (Non-Doped Silicate Glaze) having a total thickness of about 300.degree.
After depositing an ss) film or an HTO (High Temperature Oxide) film or the like, an oxide film 80 covering the floating gate 42 is formed by thermal oxidation. Then, in a state where this step is completed, an instruction of the ROM code is issued, and the process waits until the ROM coating mask is completed.

In FIG. 26, when a ROM code is specified, a ROM coding mask is created based on the instruction. Then, using a photoresist film 82 having an opening 81 as a ROM coding mask, phosphorus (P) is accelerated at an acceleration voltage of 100 KeV and a dose of 1.0 × 1.
Ions are implanted under the condition of 014 / cm 2. Thus, an N− type channel diffusion region 83 is formed in the channel portion of the selected transistor in the mask ROM 43.

In FIG. 27, after removing the oxide film 80 on the mask ROM 43 side, the entire surface is thermally oxidized,
A tunnel oxide film 84 serving as a second gate oxide film of the EEPROM 41 and a gate oxide film 85 of the mask ROM 43 are formed. Next, a film thickness of 200
After depositing a polysilicon film having a thickness of about 0 ° to 3000 ° and phosphorus-doping the same, an EE crosses over the floating gate 42 and the substrate 31 by a photoresist process.
The control gate 46 of the PROM 41 and the mask RO
A gate electrode 86 of M43 is formed. Note that a stacked structure of a polysilicon film and a metal silicide film may be used.

In FIG. 28, after a photoresist film 51 having an opening 50 is formed on the entire surface, phosphorus (P) is ion-implanted at an acceleration voltage of 40 KeV and a dose of about 1.0 × 10 15 / cm 2, thereby floating the EEPROM 41. A common source region 52 is formed adjacent to one end of the gate 42. In FIG. 29, the film thickness is 2
After depositing a CVD oxide film 87 of about 00 °, the substrate 31
A photoresist film 56 having an opening 55 thereon is formed, and arsenic (As) is ion-implanted from above to perform EEP.
The drain region 57 is connected to one end of the control gate located on the other end side of the floating gate 42 of the ROM 41 by the gate electrode 8 in the mask ROM 43.
6 so as to be adjacent to both ends of the source / drain region 58.
To form

Referring to FIG. 30, after performing an annealing process at about 900 ° C. for several hours to activate the ion-implanted impurities, an interlayer insulating film 59 made entirely of a BPSG film or the like is deposited, and Contact hole 6
After forming 0, a wiring 68 made of an aluminum material is formed to contact the drain region 57 via the contact hole 60.

Then, a protective film such as a Si3N4 film is formed to complete a one-chip microcomputer including an EEPROM and a mask ROM.

[0018]

However, according to the above-described manufacturing method, the step for writing the ROM code is performed in the ion implantation step before the formation of the gate electrode 86, so that the number of manufacturing steps until completion is large. And therefore R
There was a drawback that TAT was long during the period from OM order to completion.

Accordingly, it is an object of the present invention to shorten the TAT by reducing the process for writing a ROM code to a process as late as possible in a one-chip microcomputer having a built-in EEPROM and a mask ROM. .

[0020]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and has been described in which a first conductive film is formed via a gate oxide film formed on a semiconductor substrate of one conductivity type. The conductive film is patterned to form a floating gate of the EEPROM and a gate electrode of the mask ROM. Next, after forming a second conductive film via an oxide film formed on the entire surface, the conductive film is patterned to form a control gate on the floating gate. Subsequently, using a photoresist film having an opening as a mask, an impurity of the opposite conductivity type is ion-implanted into the surface layer of the substrate to form a first diffusion region of the opposite conductivity type adjacent to one end of the floating gate, Further, the first diffusion region is masked with a photoresist film, and impurities of the opposite conductivity type are ion-implanted so that the opposite conductivity type is adjacent to one end of the control gate located on the other end side of the floating gate. A third diffusion region of the opposite conductivity type is formed adjacent to both ends of the second diffusion region and the gate electrode. In addition, an interlayer insulating film is formed on the entire surface, a contact hole that opens on the second diffusion region is formed, and a wiring that contacts the second diffusion region via the contact hole is formed.
Subsequently, impurities of the opposite conductivity type are ion-implanted using the ROM coding mask having an opening on the selected gate electrode in the mask ROM as a mask, so that the opposite conductivity type is penetrated into the surface layer of the substrate through the gate electrode. The fourth diffusion region is formed.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the related art are denoted by the same reference numerals, and description thereof will be simplified. First, in FIG. 1, a pad oxide film 32 having a thickness of about 500 ° is formed by thermally oxidizing the surface of a semiconductor substrate 31, and a silicon nitride film 33 having a thickness of about 2000 ° is formed thereon by low pressure CVD. This silicon nitride film 33 is patterned by a photoresist process to form an opening 34.

In FIG. 2, a photoresist film (not shown)
Then, the entire substrate 31 is subjected to steam oxidation at 1000 ° C. for several hours to form a LOCOS oxide film 35 for element isolation in the opening 34 of the silicon nitride film 33.
In FIG. 3, the silicon nitride film 33 used for the selective oxidation is removed, and the pad oxide film 32 thereunder is further removed with a hydrofluoric acid solution.
After removing the substrate 31 and cleaning the surface of the substrate 31, a first gate oxide film 36 having a thickness of about 100 to 200 ° is formed by dry oxidation at 900 ° C. for several tens minutes. Further, a film thickness of 1000 is formed on the first gate oxide film 36 by a low pressure CVD method.
Non-doped polysilicon film 3 of about {2000}
7 is formed.

In FIG. 4, phosphorus (P) is applied to the polysilicon film 37 at an acceleration voltage of 40 KeV and a dose of 1.0 × 10 15.
The polysilicon film 37 is given conductivity by ion implantation under the condition of / cm 2, and then a silicon nitride film 38 having a thickness of about 2000 ° is formed by the low pressure CVD method. Further, the silicon nitride film 38 is patterned by a photoresist process to form an opening 39 of the silicon nitride film 38.

In FIG. 5, the entire substrate 31 is 900 ° C.
By performing a heat treatment in an oxidizing atmosphere for one hour, the polysilicon film 37 is selectively oxidized to form a selective oxide film 40 on the surface of the opening 39. The selective oxide film 40 is formed in such a shape that the film thickness is large at the central portion and thin at the peripheral portion. In FIG. 6, after the silicon nitride film 38 used for selective oxidation is removed, the polysilicon film 37 is patterned with a selective oxide film 40 by a photoresist process to form a floating gate 42 of the EEPROM 41.
And the gate electrode 44 of the mask ROM 43
To form At this stage, the first gate oxide film 36 may be left.

In FIG. 7, NSG (Non Doped Silicate Glas) having a total thickness of about 300.degree.
s) After depositing a film or an HTO (High Temperature Oxide) film or the like, a second gate oxide film 45 covering the floating gate 42 and the gate electrode 44 is formed by thermal oxidation. The second on the EEPROM 41
The gate oxide film 45 constitutes a tunnel oxide film.

In FIG. 8, a film thickness of 2000 .ANG. Is formed on the second gate oxide film 45 by a low pressure CVD method so as to cover the floating gate 42 and the gate electrode 44 over the entire surface.
A polysilicon film of about 3,000 to about 3000 ° is deposited and phosphorus-doped, and then, a photoresist process is performed to extend from the floating gate 42 to the substrate 31 through the EEPR.
The control gate 46 of the OM 41, FIG.
As shown in FIG. 4, the LOCOS oxide film 3 of the mask ROM 43
An ion penetration prevention film 47 is formed on 5. Note that a stacked structure of a polysilicon film and a metal silicide film may be used.

Referring to FIG. 9, a photoresist film 51 having an opening 50 is formed, and phosphorus (P) is applied at an acceleration voltage of 40 Ke.
A common source region 52 is formed adjacent to one end of the floating gate 42 of the EEPROM 41 by ion implantation of V and a dose of about 1.0 × 10 15 / cm 2. In FIG. 10, after depositing a CVD oxide film 53 having a thickness of about 200 ° as a whole, the opening 5 is formed on the substrate 31.
5 is formed, and arsenic (As) is ion-implanted from above.
1 has a drain region 57 adjacent to one end of the control gate located on the other end side of the floating gate 42, and a mask ROM 43 has source / drain regions 58 adjacent to both ends of the gate electrode 44. Form.

In FIG. 11, after performing an annealing process for activating the implanted impurities at about 900 ° C. for several hours, an interlayer insulating film 59 such as a BPSG film is deposited on the whole. Subsequently, the interlayer insulating film 59 is formed by a photoresist process.
Is etched to form a contact hole 60 on the drain region 57. Then, a wiring 68 that contacts the drain region 57 through the contact hole 60 is formed by depositing an aluminum material and a photoresist process. Then, in a state where this step is completed, an instruction of a ROM code is issued, and the process waits until a ROM coding mask is completed.

In FIG. 12, when a ROM code is specified, a ROM coding mask is created based on the instruction. Then, after a photoresist film 72 having an opening 71 as a ROM coding mask is formed on the entire surface, phosphorus (P) is applied at an acceleration voltage of 400 KeV to 600 K.
Ion implantation is performed under conditions of eV and a dose of 1.0 × 10 14 / cm 2. As a result, phosphorus (P) penetrates through the gate electrode 44 of the selected transistor in the mask ROM 43 to form an N-type channel diffusion region 73 in the channel of the transistor. Thus, the writing of the ROM code is completed (depletion in the N-channel transistor is performed).

Incidentally, as shown in FIG.
By actively forming the wiring 68 together with the above-described ion penetration prevention film 47 on the LOCOS oxide film 35 in the inside,
Further, penetration of ions implanted for writing the ROM code under the LOCOS oxide film 35 can be prevented. Hereinafter, after removing the photoresist film 72, S
By forming a protective film made of an i3N4 film, a one-chip microcomputer having a built-in EEPROM and a mask ROM is completed.

FIGS. 13 to 15 schematically show the structure of one embodiment of a process of writing a ROM code to a selected transistor in the mask ROM 43, which is a feature of one embodiment of the present invention. This will be described based on FIG. 13 is a plan view showing a mask ROM 43 forming region, FIG. 14 is a sectional view taken along line AA of FIG. 13, and FIG. 15 is a sectional view taken along line BB of FIG.

As shown in these drawings, the mask ROM 4
An ion penetration preventing film 47 is present on the LOCOS oxide film 35 in 3 and a wiring 68 is positively present on the LOCOS oxide film 35 as shown in FIG.
The ions at the time of OM coding are LOCOS oxide film 35
It does not penetrate downward and can prevent the field inversion voltage from lowering.

As described above, in the one-chip microcomputer of the present invention, the step of writing the ROM code can be omitted after the formation of the wiring 68 contacting the drain region 57 of the EEPROM 41. The number is smaller than in the conventional example, so that the TAT can be significantly reduced. Also, mask ROM
By forming the ion penetration prevention film 47 and the wiring 68 on the LOCOS oxide film 35 in the 43, it is possible to prevent the penetration of ions implanted for writing the ROM code under the LOCOS oxide film 35.

It should be noted that, even in a multi-layer wiring of two or more layers,
The present invention can be applied. Further, in the present embodiment, a so-called split gate type flash memory structure in which a control gate is formed so that a configuration of a memory cell portion of an EEPROM extends over an upper portion and a side portion of a floating gate is illustrated. The present invention is not limited to this, and can be applied to a so-called stacked gate type flash memory structure in which a control gate is stacked on a floating gate.

Further, in the present embodiment, the step of writing a ROM code by ion-implanting an N-type impurity into a channel region of an N-channel transistor and depleting the same is illustrated. The present invention can be applied not only to P-type transistors but also to a step of writing ROM code by ion-implanting a P-type impurity such as boron (B) into a channel region in a P-channel transistor and depletion. By enhancing a specific transistor in an N-channel transistor, the transistor can be applied to a step of writing ROM code.

[0036]

As described above, according to the one-chip microcomputer having the one-layer wiring structure of the embodiment of the present invention, the step for writing the ROM code is performed by the EEPROM.
Can be moved down after the formation of the single-layer wiring, so that the number of manufacturing steps thereafter is smaller than in the conventional example, and
Can be greatly reduced.

Further, by positively forming a one-layer wiring on the LOCOS oxide film of the mask ROM, it is possible to prevent penetration of ions implanted for writing a ROM code under the LOCOS oxide film.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a seventh sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 8 is an eighth sectional view showing the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 9 is a ninth cross-sectional view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention;

FIG. 10 is a tenth cross-sectional view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention;

FIG. 11 is an eleventh cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 12 is a twelfth cross-sectional view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention;

FIG. 13 is a plan view illustrating a ROM coding method according to an embodiment of the present invention.

FIG. 14 is a sectional view taken along line AA of FIG.

15 is a sectional view taken along line BB of FIG.

FIG. 16 is a diagram showing a conventional general one-chip microcomputer.

FIG. 17 is a diagram showing a conventional general one-chip microcomputer.

FIG. 18 is a diagram showing a conventional general one-chip microcomputer.

FIG. 19 is a first cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 20 is a second cross-sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 21 is a third cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 22 is a fourth cross-sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 23 is a fifth sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 24 is a sixth sectional view showing the method for manufacturing the conventional semiconductor device.

FIG. 25 is a seventh cross-sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 26 is an eighth sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 27 is a ninth sectional view illustrating the conventional method for manufacturing a semiconductor device.

FIG. 28 is a tenth cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 29 is an eleventh cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 30 is a twelfth cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device including an EEPROM and a mask ROM, wherein a ROM coding step for a selected transistor in the mask ROM is performed after an EEPROM wiring forming step. Method. 2. An EEPROM on a semiconductor substrate of one conductivity type.
Forming an element isolation film that insulates and separates the formation region from the mask ROM formation region, and forming a gate oxide film over the EEPROM formation region and the mask ROM formation region; and forming a first conductive film via the gate oxide film. Forming a floating film for EEPROM and a gate electrode for mask ROM by patterning the conductive film; forming an oxide film on the entire surface; forming a second conductive film; and patterning the conductive film. Forming a control gate on the floating gate; and ion-implanting an impurity of the opposite conductivity type into the surface layer of the substrate using the photoresist film having the opening as a mask, thereby forming an opposite conductivity type adjacent to one end of the floating gate. Forming a first diffusion region; and masking the first diffusion region with a photoresist film to form a reverse conductivity type. Impurity is ion-implanted to form a second diffusion region of the opposite conductivity type so as to be adjacent to one end of the control gate located on the other end side of the floating gate, and a reverse conductivity type so as to be adjacent to both ends of the gate electrode. Forming a third diffusion region; and forming an interlayer insulating film on the entire surface, forming a contact hole opening on the second diffusion region, and forming the contact hole in the second diffusion region through the contact hole. Forming a wiring to be contacted, and performing ion implantation of impurities of the opposite conductivity type by using a ROM coding mask having an opening on a selected gate electrode in the mask ROM as a mask to penetrate through the gate electrode to form a substrate. Forming a fourth diffusion region of the opposite conductivity type in the surface layer.