JPH11111851A - Redundancy processing device and method, and the redundancy processing device with test function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a redundancy processing device which is capable of shortening the time necessary for judgement of relief or non-relief of a bit fail in redundancy processing. SOLUTION: As pre-prepasion, all relieve solutions for all relievable bit failures are registered beforehand in a relief database by an operator 29 for redundancy processing of an IC with a redundancy circuit. In the relief/non-relief discriminating operation in an actual function test, the same array pattern as bit fail generated is searched from the database to find a relief solution. When a bit fail of the same array pattern is not present in the relief solutions, it will be seen that the bit fail cannot be relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy processing apparatus for use in a wafer test process of an IC with a redundant circuit, and more particularly, to a redundancy processing apparatus using information on defective parts from an IC with a redundant circuit which is a device under test. The present invention relates to a redundancy processing device for determining whether or not replacement is possible with a redundant circuit of an IC with a circuit.

[0002]

2. Description of the Related Art Generally, in a wafer test process for an IC with a redundant circuit, a redundancy process is performed to determine whether or not a defective portion can be repaired by replacing the defective portion with a redundant circuit. That is, in the wafer test processing, the rescue availability determination processing is performed. The LSI tester used in the wafer test process has a buffer memory for storing information on a defective portion, and stores information on the defective portion in the buffer memory simultaneously with the function test of the IC with a redundant circuit. Then, based on the stored information on the defective portion, it is determined whether or not replacement by the redundant circuit of the IC with redundant circuit is possible.

In recent years, however, ICs with redundant circuits
Are becoming larger in capacity, and redundant circuits are becoming more complicated. For this reason, the time required for the wafer test processing is increasing. As a countermeasure against this, a redundancy processing device 3 with a test function as shown in FIG.
0 is used. That is, a redundancy processing device with a test function 30 in which an LSI tester 32 and a redundancy processing device 34 are separately provided is used. In the redundancy treatment device 30 with the test function, the LSI
A functional test of the IC with the redundant circuit is performed by the tester 32,
The information about the defective portion found as a result is transferred to the redundancy processing device 34. Redundancy processing unit 34
Then, based on the information on the defective portion, it is determined whether or not the IC with a redundant circuit can be repaired. As described above, by separately providing the redundancy processing device 34 for performing the repair availability determination process for determining the availability of the repair, the function test by the LSI tester 32 and the repair availability determination process by the redundancy processing device 34 can be performed. , So that they can be processed in parallel. That is,
Parallel processing is used to reduce the apparent wafer test processing time.

FIG. 21 shows an example of a time chart when a wafer test process is performed by the redundancy processing device 30 with a test function. As can be seen from FIG. 21, in the wafer test processing, the time required for the resiliency determination processing in the redundancy processing device 34 may be completed in a shorter time than the time required for the function test in the LSI tester 32. It is ideal. For that purpose, it is necessary to shorten the time required for the actual rescue-possibility determination processing of the redundancy processing device 34 as much as possible.

[0005]

As can be seen from FIG. 22, defective portions of an IC with a redundant circuit are roughly classified into line-fails and bit-fails. Here, line fail and bit fail refer to the following. For example, an IC with a redundant circuit has two spare columns SC
1, SC2 and two spare rows SR1, SR2. These spare columns SC1 and SC2 are 2
It is assumed that there are five defective portions on the same row address as shown by a broken line A in a state where both books can be used. As described above, when there are three or more failures on the same row address, these defective portions are replaced by the spare column SC1,
Even if both SC2s are replaced, they cannot be remedied. In other words, these defective portions can be relieved only by replacing them with the spare row SR1 or the spare row SR2. The same applies to the case where there are three or more defective locations on the same column address, as indicated by the dashed line B. Thus, the spare column S
A set of defective parts that cannot be rescued unless the spare is one of the spare rows SR1 and SR2 is called a line fail. Conversely, as shown by the dashed line C, there may be only two or less defective locations on the same row address and the same column address. In this case, the defective portion can be remedied by replacing the defective column using either the spare column SC1, SC2 or the spare row SR1, SR2. A set of such defective parts is called a bit fail.

Of these line-fails and bit-fails, for the line-fail, the spare column SC1, SC2 or the spare row SR
It has been determined which of SP1 and SR2 should be used for replacement. However, bit fail has not been decided. Therefore, these spare columns S
It is necessary to determine how to combine C1 and SC2 with spare rows SR1 and SR2 to relieve bit failure. That is, the combination relief must be performed. Comparing the time required for the line fail rescue decision processing with the time required for the bit fail rescue decision processing, the time required for the bit fail rescue decision processing is usually much larger. . This is because in the bit failure rescue determination process, the combination rescue must be performed in the following procedure.

[0007] Combination relief is generally performed according to a tree as shown in FIG. FIG. 24 shows a tree of combination relief of an IC with a redundant circuit having two spare rows and two spare columns. This combination remedy means that "rescue using a spare row" is performed for each of a plurality of existing bit failures, and if rescue is not possible, the same bit fail is remedied using a spare column. If possible, this is a method of performing rescue for the next bit fail, such as "repair using spare row". Then, this procedure is repeated until there is no usable spare row and spare column. In this way, when the user follows the tree, a rescue solution can be found in the case of a retrievable bit failure. However, if you continue to go and perform combined rescue, you will often find another remedy. In general, an optimal rescue solution determined by a certain criterion among the plurality of rescue solutions is required.
In order to obtain the optimal rescue solution, it is necessary to find all rescue solutions from the combination tree, and to do so, it is necessary to trace most of the tree and confirm each one. That is, in this case, it is necessary to perform the rescue availability determination processing for a total of 18 bit failures to confirm whether the rescue is possible. For this reason, there is a problem that the time required for the resilience determination processing of the bit fail becomes longer than the time required for the resilience determination processing of the line failure.

FIG. 25 shows a tree in the case of three spare rows and three spare columns. In this case, it is necessary to determine whether or not the rescue is possible by performing the resilience determination processing of the bit fail for a total of 58 times. In particular, considering the recent increase in the number of spares, this number will increase catastrophically. Then, the time required for the wafer test processing is increased, which may cause a significant reduction in throughput.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a redundancy processing apparatus and a redundancy processing method that can shorten the time required for the bit fail rescue determination processing. That is, it is an object of the present invention to provide a redundancy processing apparatus and a redundancy processing method that can perform the rescue decision processing in a short time even when the number of spare columns and the number of spare rows increase. Still another object of the present invention is to provide a redundancy processing apparatus with a test function that can minimize the time required for wafer test processing. That is, an object of the present invention is to provide a redundancy processing apparatus with a test function capable of reducing the time required for wafer test processing and increasing the throughput.

[0010]

In order to solve the above-mentioned problems, a redundancy processing apparatus according to the present invention relieves a defective portion of an IC with a redundant circuit having a plurality of redundant circuits by replacing the defective portion with the redundant circuit. In a redundancy processing device for performing a resilience determination process for determining whether or not rescue is possible, a repair solution as a combination of an arrangement pattern of the rescuable defective portion and the redundant circuit corresponding to the arrangement pattern is provided. Are registered in advance, and in the rescue possibility determination processing, the registered arrangement pattern is searched for the same arrangement pattern as that of the defective portion actually generated, and the registered remedy corresponding to the same arrangement pattern is searched. A database storage unit for storing a rescue processing database for performing the rescue feasibility determination processing using the solution. It is characterized in.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) In a first embodiment of the present invention, a repair processing database in which a repair solution is registered for each bit-failure bit matrix arrangement pattern in a redundancy processing apparatus is created in advance, and a function test of the IC with a redundant circuit is performed. At the time of the rescue decision process for the bit failure found at the time of the search, the same arrangement pattern is searched from the rescue process database, and the rescue decision process is performed using the rescue solution registered corresponding thereto. It is like doing it.
Thus, the time required for the rescue determination process in the actual function test is reduced.

First, an example of a configuration of a redundancy processing device with a test function according to the present invention and an outline of the processing will be described with reference to FIG. As can be seen from FIG. 1, the redundancy processing apparatus 1 with a test function according to the present invention has an LS
It comprises an I tester 10 and a redundancy processing device 20. This redundancy processor with test function 1
Is the DUT that is the device under test in the LSI tester 10.
(Device unchip test) A function test of 5 is performed. Then, the information on the defective portion found as a result of the function test is transferred to the redundancy processing device 20, and the redundancy processing which is the rescue availability determination process is performed by the redundancy processing device 20.

More specifically, the LSI tester 10 includes a test pattern generator 11. The test pattern generator 11 generates a test pattern. This test pattern is applied to the DUT 5 as an electric signal for device measurement in a function test. The output signal of the DUT 5 for the applied test pattern is
The measurement result is input to the comparator 12. The measurement result itself does not yet include information on pass or fail, that is, information on the quality of the measurement result. The signal from the expected value generator 13 is also input to the comparator 12. In the expected value generator 13, D
The UT 5 generates an expected value to be output. The comparator 12 compares the measurement result with the expected value to determine whether the measurement result is pass or fail. That is, the quality of the measurement result is determined. Then, information on the quality of the measurement result is stored in the fail memory 14 together with the row address and the column address in the DUT 5.

To the redundancy processing device 20, information relating to a defective portion is transferred from the LSI tester 10. That is, the fail information, the row address, and the column address stored in the fail memory 14 of the LSI tester 10 are transferred to the redundancy processing device 20. Of these signals, the fail information and the row address are input to the row address fail counter 21. The fail information and the column address are input to the column address fail counter 22. The row address fail counter 21 and the column address fail counter 22 count how many defective portions occur on the same line. The row line fail detector 23 and the column line fail detector 24 detect whether a line fail has occurred based on signals from the row address fail counter 21 and the column address fail counter 22. And if a line fail occurs,
The fail flag of the corresponding line in the row line fail flag 25 or the column line fail flag 26 is set. In the write controller 27, the LSI tester 1
A bit fail is extracted based on a signal related to a row address and a column address from 0 and signals from the row line fail detector 23 and the column line fail detector 24. For example, when there is a defective portion as shown in FIG. 2, the line fail D and the line fail E are removed, and only the bit fill is extracted. When the spare column and the spare row are used for the rescue of the line fail as described above, the number of the spare columns and the spare rows that can be used for the rescue of the bit fail is reduced correspondingly. In the example of FIG. 2, assuming that spare row SR1 is used for rescue of line fail D and spare column SC1 is used for rescue of line fail E, spares available for bit fail rescue are as follows. , Spare row SR2 and spare column SC2. As can be seen from FIG. 1, this bit-failed data is output to the buffer memory 28. The data of the bit failure of the buffer memory 28 is taken into the arithmetic unit 29. The arithmetic unit 29 determines whether or not the repair can be performed by replacing the previously detected line fail and bit fail with a usable spare column and spare row. That is, a rescue possibility determination process is performed.

Next, a redundancy process which is a rescue possibility determination process according to the present embodiment will be described in detail. That is,
A redundancy process for an IC with a redundant circuit having two spare rows and two spare columns as a redundant circuit will be described.

The redundancy processing in this embodiment is as follows.
The process is divided into a preliminary process as a preparation process and a main process as a rescue possibility determination process. The pre-process is a process separate from the main process, and is performed once and separately from the main process when performing a redundancy process of a new product.

This pre-processing is, as can be seen from FIG.
First, all rescuable bit matrices are listed. For example, if two spare rows and two spare columns can be used, all bit matrices that can be repaired by the spares are listed. However, they are sorted according to the following rules: That is, as can be seen from FIG. 3A, the number of defective bits in the bit matrix is counted in the horizontal direction in the bit matrix, and the bits are rearranged in descending order. In this example, rearrangement is performed in the order of Y1, Y4, Y2, Y3, and Y5. Then, a bit matrix as shown in FIG. 3B is obtained. Next, the bit matrices are rearranged so as to form a stepwise flow from the upper left to the lower right. In this example, the data is rearranged in the order of X1, X2, X4, X5, and X3.
Then, a bit matrix as shown in FIG. When rearranged according to such rules, FIG.
The bit matrix of FIG. 3A is equivalent to the bit matrix of FIG. For this reason, for the bit matrix of FIG. 3A, the rescue solution can be omitted. In other words, the bit matrix which becomes the same arrangement pattern by rearranging, except for the arrangement pattern of the defective portion in the bit fail, can be omitted.

Further, consider the number of defective portions that can be relieved using two spare columns and two spare rows. At this time, all defective parts developed in the bit matrix are bit failures. This is because, as described above, the line fail has already been removed from the defective portions. Therefore, only two defective portions are arranged on the same row address and only two defective portions are arranged on the same column address. Therefore, the number of defective portions that can be relieved by one spare is a maximum of two. From this, the maximum number of defective areas that can be remedied is (the number of spare rows × 2) + (the number of spare columns × 2) = 8.

Similarly, consider the maximum value of the size of the bit matrix. The number of defective portions that can be remedied by the spare column is up to four in the X direction, and the number of defective portions that can be remedied by the spare row is up to two in the X direction. Therefore, the maximum value of the size in the X direction in the bit matrix is six.
In the same manner, the maximum value of the size in the Y direction in the bit matrix is also six.

FIG. 4 shows a bit matrix that can be rescued based on the above. In other words, the size of the bit matrix created here is a maximum of eight defective locations, a maximum of six matrix X sizes, and a maximum of six matrix Y sizes.

Next, all the repair solutions for the bit matrix in FIG. 4 are obtained, and the bit matrix that cannot be repaired is excluded. For example, in the case of the bit matrix shown in FIG. 4, the arrangement pattern of (3) in the case where the number of defective portions is eight,
The arrangement pattern (4) in the case where the number of defective portions is seven cannot be remedied. That is, these are the arrangement patterns of defective portions that cannot be repaired with two spare columns and two spare columns. Therefore, it is excluded from the rescue processing database in advance. Here, the remedy solution is calculated by performing the combination remedy. For example, suppose that a bit matrix as shown in FIG. In this case, the bit matrix is searched from the upper left to the lower right in the X direction, and the first defective portion (1, 1) and the second defective portion (1, 2) are replaced with spare rows. The remaining defective portions (3, 2) and (4, 3) are replaced by using spare columns since there is no spare row. As a result, since no defective portion is found on the bit matrix, one remedy to be remedied in the order of RRCCC has been found. In this way, in the bit matrix shown in FIG. 5, five repair solutions are obtained. In this way, a rescue solution is obtained for all the arrangement patterns, and a rescue processing database as shown in FIG. 6 is created. That is, all rescue solutions for all rescuable bit fail arrangement patterns are registered, and a rescue processing database is created. FIG. 7 schematically shows the data structure of the rescue processing database.
become that way.

As can be seen from FIGS. 6 and 7, the rescue processing database is provided with three search keys. That is, there are provided three search keys, that is, the number of defective portions in the bit failure taken into the buffer memory, the bit matrix X size, and the bit matrix Y size. These three search keys are
This process is used for a bit matrix search in the main process, which will be described in detail later, that is, in the rescue availability determination process. As can be seen from FIG. 1, the rescue processing database is stored in a part of the arithmetic unit 29 in the redundancy processing device 20.
Thus, the rescue processing database is completed, and the pre-processing is completed.

FIG. 8 is a flowchart showing the contents of the above pre-processing. First, one rescueable bit matrix arrangement pattern is created (S10). Next, all rescue solutions corresponding to the arrangement pattern of the bit matrix are obtained (S11). Next, the arrangement pattern of the bit matrix and the rescue solution are registered in the rescue processing database (S12). Then, it is confirmed whether bit matrices of all arrangement patterns that can be relieved have been created (S13). If all the arrangement patterns have been created, the pre-processing ends. On the other hand, if not created for all the arrangement patterns, a bit matrix of the next arrangement pattern is created (S1).
4) A process for obtaining all the repair solutions corresponding to the bit matrix is performed again (S11).

Although the pre-processing has been described above, the present processing will now be described. As can be seen from FIG. 1 described above, this processing means that LS is applied to the actual wafer.
A wafer test is performed by applying the I tester 10 to perform a functional test as to whether or not a defective portion exists. And
The rescue availability determination process is performed on a defective portion found as a result of the function test.

Now, it is assumed that fail information as shown in FIG. 9A has been sent to the buffer memory 28, for example. This fail information is a bit fail as described above. In this case, however, it is assumed that there is no line failure only with a bit failure. Therefore, two spare rows and two spare columns are available.
The buffer memory 28 transfers the data of the bit failure to the arithmetic unit 29. As can be seen from FIG. 9B, the arithmetic unit 29 develops this bit failure into a bit matrix. Next, as can be seen from FIG.
No. 9 rearranges the bit matrix according to the same rule as that described in the preprocessing. That is,
The bit matrix is rearranged in descending order by looking at the value obtained by counting the number of defective portions in the horizontal direction. In the bit matrix shown in FIG. 10A, Y3, Y1, and Y2 are rearranged in this order. This results in a bit matrix as shown in FIG. Next, the bit matrix shown in FIG. 10B is rearranged so that the defective portion has a step-like shape flowing from upper left to lower right. That is, X3, X4, X1, X
Rearrange in the order of 2. This results in a bit matrix as shown in FIG.

Next, a rescue solution for the bit matrix of FIG. 10C is searched from the rescue processing database described above. That is, a search is made as to whether a bit matrix having the same arrangement pattern as the bit matrix shown in FIG. 10C is registered in the repair processing database. At this time, since the number of defective portions is 4, the matrix X size is 4, and the matrix Y size is 3, the bit matrix is searched with reference to the three search keys. In other words, limited to the range where these three search keys match in the rescue process database,
Search for the arrangement pattern of the bit matrix. As a result of this search, it is found that the arrangement pattern of the bit matrix in FIG. 10C is the same as the arrangement pattern of the bit matrix of the repair processing database shown in FIG.
Thus, it can be seen that there are five remedy solutions in this bit matrix. That is, the registered five rescue solutions can be obtained by the search.

The rescue solutions are arranged in order from the optimal one. That is, spare rows are prioritized and spares are arranged in ascending order of the number of spares used. Therefore, the first remedy solution “CRR” is selected. Therefore, the defective part (1, 1) and the defective part (1, 2) are repaired by the spare column, and the defective part (3, 2) and the defective part (4,
3) is relieved by the spare row.

FIG. 12 is a flowchart showing the contents of the above processing. First, the transferred bit matrix is rearranged in the arithmetic unit 29 according to the rearrangement rule (S21). Next, a bit matrix having the same arrangement pattern as the rearranged bit matrix is searched from the rescue processing database (S22).
Then, using the first rescue solution registered in the rescue processing database, rescue of a defective portion in the bit fail is attempted (S23). It is determined whether or not all the defective portions of the bit fail can be remedied by this remedy solution (S24), and if remedy is possible, the rescue is possible (S25), and the rescue availability determination processing is completed. I do. If the rescue is impossible, it is searched whether or not another rescue solution is registered, and it is determined whether or not another rescue solution exists (S26). Here, the case where all the defective portions in the bit fail cannot be rescued while the rescue solution exists is, for example, a case where the number of spares usable for the rescue of the bit fail is reduced due to the presence of the line fail. The case is conceivable. If there is no other remedy solution, it is concluded that rescue is impossible (S27).
This ends the rescue availability determination process. If another rescue solution exists, the next rescue solution is used (S2
8), the bit fail is rescued again (S23).
This processing is performed by repeating the above processing.

FIG. 13 is a flowchart summarizing the entire wafer test processing described above. First, in the LSI tester 10, an IC with a redundant circuit
Is performed (S31). The information on the defective part obtained by the function test is transferred to the redundancy processing device 20 (S32).

The redundancy processing device 20 determines whether or not there is too much information on the defective part (S3).
3). For example, when the number of defective portions is larger than the sum of the number of bits of the two spare columns and the number of bits of the two spare rows, the information on the defective portions is excessive, and it is determined that remedy is impossible (S38). Next, rescue availability determination processing by line fail is performed (S34). If the line fail cannot be remedied, for example, if there are five line failures, it is determined that the remedy is impossible (S
38). Next, the bit fail that is obtained by removing the line fail from the defective portion is developed into a bit matrix (S35). In the development of the bit matrix, for example, if the matrix X size is 6 or more, it is determined that relief is impossible (S38). next,
Based on the arrangement pattern of the bit matrix, a rescue processing database is searched to perform a bit failure rescue determination process (S36). At the time of this search, if a bit matrix having the same arrangement pattern is found and a remedy is found, it is a rescuable bit fail. If there is no bit matrix of the same arrangement pattern or if a bit matrix of the same arrangement pattern is found but there is no rescue solution that can remedy all defective portions, it is determined that rescue is impossible (S38). Among these processes, the line fail rescue determination process (S
34), the bit matrix expansion process (S35), and the bit failure rescue availability determination process (S36) are performed by the arithmetic unit 29 in FIG.

As described above, according to the redundancy processing apparatus 1 with the test function according to the first embodiment of the present invention, the rescue solution necessary for the bit fail rescue determination processing performed by the redundancy processing apparatus 20 is registered. Since the prepared rescue processing database is prepared in advance, it is possible to prevent unnecessary combination rescue. In other words, in the prior art, the resilience determination process for bit fail has performed combination rescue using an available spare. In this combination rescue, a combination of a spare row and a spare column has a tree structure, and a technique of finding a remedy solution while following the technique one by one has been adopted. Even in this conventional method, by predicting the end of the tree and if remedy is not possible, by avoiding that technique at that point, by performing processing to move to another technique,
Although it was trying to find a remedy solution efficiently, even a rescue procedure that could not be remedied would proceed to some extent. On the other hand, in the rescue decision processing according to the present embodiment, since the rescue solution is registered in advance, unnecessary processing unlike the conventional case does not occur, and as a result, the time required for the rescue decision processing is reduced. be able to. In other words, all rescue solutions corresponding to the bit fail arrangement pattern are registered in the rescue process database in advance in the pre-processing stage. It is possible to eliminate the necessity of performing a combination remedy. That is, the remedy of the bit failure can be completed by a single process using the optimal solution registered in advance. For this reason, the time required for the bit fail rescue determination processing can be reduced. The time required for the resiliency determination processing for this bit failure occupies a large part of the time required for the redundancy processing. As a result, the time required for the redundancy processing can be greatly reduced.

In addition, since a search key is provided in the rescue processing database, a bit matrix registered in the same arrangement pattern as the generated bit failure can be quickly searched. That is, since the rescue processing database is provided with three search keys of the number of defective portions in the bit matrix, the matrix X size, and the matrix Y size, the arrangement pattern of the bit matrix developed based on the generated bit failure can be changed. ,
A search can be performed in a short time based on these three search keys. That is, the range to be searched in the rescue processing database can be extremely limited based on the three search keys. As a result, not only can a rescue solution be obtained in a shorter time, but also it can be found in a short time that a bit matrix of the same arrangement pattern does not exist in the rescue processing database, so that it is determined in a short time that the remedy is impossible. Can be done with

In the following, a specific reduction rate of the wafer test processing time according to the present embodiment will be calculated. Here, it is assumed that the wafer test is completed by applying the redundancy processing apparatus with a test function to one wafer four times. Further, the time required for the rescue determination process per DUT is set to 5 seconds, and the D
Assume that the UT has 85%. 200 chips per wafer
And the number of simultaneous measurement is 64, and the number of DUTs to be subjected to the redundancy processing at the same time is eight. Further, it is assumed that the time required for the rescue determination process becomes 50%. In this way, the time shortened by one wafer measurement is expressed as follows.

The number of times of measurement index × repair availability judgment time × repair required DUT rate × repair time reduction rate (the number of simultaneous measurements ÷
(Simultaneous redundancy processing DUT number) Therefore, 4 × 5 × 0.85 × 0.5 ×
(64/8) = 68 seconds can be shortened. In one lot (25 wafers), 68 seconds × 25 = about 28 minutes can be reduced.

Next, the number of lots that can be measured for one required tester is determined. The required number of testers indicates how many testers are required when producing a device.
Months (30 days x 24 hours) x tester operation rate (0.8) =
Let 576 hours be the operating time for one required tester. Furthermore, the test time is 250 seconds, and the number of chips per wafer is 200.
25 pieces per lot, 64 simultaneous testers
Assume tests. Then, the number of lots that can be measured for one required tester is expressed as follows.

Operating time for one required tester ÷ Test time × 1 wafer index number × 1 lot wafer number Therefore, 576 ÷ (250 ÷ 60 ÷ 60 × 4 × 25)
And it is about 83 lots.

Further, when this is converted into cost, it becomes as follows. As described above, the processing time can be reduced by about 28 minutes per lot, so that when measuring the same 83 lots, it takes about 39 hours with 83 lots × 28 minutes. This translates into 39 hours for the required number of testers.
76 hours (operating time for one required tester) = 0.07 vehicles. $ 200,0 for one memory tester
Assuming that it is 00,000 yen, a cost reduction of $ 14,000,000 can be expected.

(Second Embodiment) As can be seen from FIG. 14, in the second embodiment, the spare columns SC1, S
An IC with a redundant circuit configured so that C2 can be used over a plurality of segments is used. This figure 1
In the case of repairing a defective portion of the IC with a redundant circuit shown in FIG.
The basic rescue is the same as the rescue availability determination process in the first embodiment described above.

For example, assume that bit failures as shown in FIG. 14 have occurred in segment 1 and segment 2, respectively. In a bit failure with such an arrangement pattern, there is no defective portion that can be repaired over a plurality of segments with one spare column. Therefore, these segments 1 and 2 are individually
Rearrange according to the rules described above. Then, Figure 1
As shown in FIG. 5, there are segment 1 'and segment 2'. When these rescue solutions are searched in the rescue process database, as can be seen from FIG. 16, the segment 1 'is rescued using the rescue solution "RRCC" registered first. In addition, although segment 2 'is to be rescued using the rescue solution "C" registered first, the remedy cannot be remedied because both spare columns are already used in segment 1'. Becomes Therefore, the rescue is performed using the next rescue solution “RR” registered in the segment 2 ′, and the rescue can be performed. As can be seen from this, it can be said that in the present embodiment, the combination relief of the repair solution is performed instead of performing the combination relief of the spare.

Assume further that a bit failure as shown in FIG. When a bit failure of such an arrangement pattern occurs, the spare columns SC1 and SC2 can be used over a plurality of segments, and a defective portion of both segments can be rescued with one spare column. Slightly different. That is, as can be seen from the rescue processing database shown in FIG.
In this case, as shown in FIG. 17, one of the defective portions of the segment 2 is simultaneously rescued when the segment 1 is rescued. , There is no defective part, and as a result, there are two defective parts, so if the bit matrix of the segment 2 is rearranged according to the rule, the segment 2 ′ shown in FIG. When the rescue solution of the bit failure of the segment 2 'is searched from the rescue process database, FIG.
As can be seen from the above, the rescue is performed by the remedy “RR”. As described above, when one spare column can be used across a plurality of segments, the next segment needs to be relieved while reflecting the rescue result of the previous segment.

The present invention is not limited to the above embodiment, but can be variously modified. For example, the number of spare columns and spare rows is not two and two, but three.
, Three, four, four,... Further, the number of spare columns and spare rows is not necessarily the same, and may be, for example, two or three. Further, in the second embodiment, the case where the spare column is used in a plurality of segments has been described, but the spare row may be used in a plurality of segments.

[0042]

As described above, according to the present invention,
Since a rescue processing database in which a rescue solution as a combination of redundant circuits corresponding to the arrangement pattern of the rescuable defective portion is registered is created in advance, the rescue solution is determined in the resilience determination processing in an actual function test. The time required for the calculation can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an entire configuration of a redundancy processing device with a test function.

FIG. 2 is a diagram showing a state in which a line fail among defective portions has been repaired.

FIG. 3 is a view for explaining a bit matrix rearrangement rule when a rescue processing database is created.

FIG. 4 is a diagram showing a part of a list of arrangement patterns of a bit matrix.

FIG. 5 is a diagram showing a remedy solution in an example of an arrangement pattern of a bit matrix.

FIG. 6 is a diagram showing an example of the contents of a rescue processing database.

FIG. 7 is a diagram conceptually showing the internal structure of a repair processing database.

FIG. 8 is a diagram showing the contents of pre-processing in a flowchart.

FIG. 9 is a diagram showing a data structure of a bit failure in a buffer memory and an arithmetic unit.

FIG. 10 is a view for explaining a bit matrix rearrangement rule during a functional test.

FIG. 11 is a diagram showing contents found as a result of searching a rescue processing database.

FIG. 12 is a diagram showing the contents of this processing in a flowchart.

FIG. 13 is a flowchart showing the contents of a wafer test process.

FIG. 14 is a diagram illustrating a state in which a bit failure has occurred in an IC with a redundant circuit having a spare column usable over a plurality of segments.

FIG. 15 is a diagram showing a state in which the bit failures shown in FIG. 14 are rearranged according to a rearrangement rule;

FIG. 16 is a diagram showing contents of a rescue process database used in rescue availability determination processing of each segment.

17 is a diagram showing a state in which bit failures of different arrangement patterns have occurred in the IC with redundant circuit shown in FIG. 14;

FIG. 18 is a diagram showing contents of a rescue process database used in the bit fail rescue availability determination process shown in FIG. 17;

FIG. 19 is a diagram showing a state in which a segment 2 is rearranged in accordance with a rearrangement rule, except for a defective portion which has been rescued in the rescue possibility determination processing of a segment 1.

FIG. 20 is a diagram showing a conventional redundancy processing device with a test function.

FIG. 21 is a timing chart of a conventional redundancy processing device with a test function.

FIG. 22 is a diagram illustrating a line fail and a bit fail.

FIG. 23 is a view for explaining combination relief using a tree.

FIG. 24 is a view for explaining combination rescue using a tree when two spare rows and two spare columns are provided as a redundant circuit;

FIG. 25 is a view for explaining combination relief using a tree in a case where three spare rows and three spare columns are provided as a redundant circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Redundancy processing apparatus with a test function 5 DUT 10 LSI tester 20 Redundancy processing apparatus SR1, SR2 Spare row SC1, SC2 Spare column

Claims (5)

[Claims] 1. A redundancy circuit for performing a repair possibility determination process for determining whether a defective portion of an IC with a redundant circuit having a plurality of redundant circuits can be repaired by replacing the defective circuit with the redundant circuit. In the processing device, an arrangement pattern of the rescuable defective portion and a rescue solution as a combination of the redundant circuit corresponding to the arrangement pattern are registered in advance, and in the resilience determination process, the registered arrangement pattern is registered. Search for the same pattern as the arrangement pattern of the defective portion actually generated from the, for performing the rescue availability determination process using the registered rescue solution corresponding to the same arrangement pattern, a rescue process database, A redundancy processing device, comprising: database storage means for storing. 2. A rescue circuit for determining whether a defective portion of an IC with a redundant circuit having a spare row and a spare column as a redundant circuit can be remedied by replacing the defective portion with at least one of the spare row and the spare column. A redundancy processing device for performing availability determination processing, wherein a repair pattern in which the defective portion can be remedied by replacing the arrangement pattern of the rescuable defective portion and the spare row and the spare column in combination with a spare solution is provided. Database storing means for storing a rescue processing database which is created and registered in advance for each, and the same arrangement pattern as the arrangement pattern of the defective portion actually found by the function test of the IC with a redundant circuit is stored in the database. Out of the rescue processing database in the storage means And search, redundancy processing apparatus according to the repair solutions registered corresponding to the same arrangement pattern by using a for performing the repairability determining process, characterized in that it comprises a repairability determining processing means. 3. The database storage means includes: a database creation developing means for developing the arrangement pattern of the rescuable defective portion into a bit matrix; and a bit matrix which rearranges the bit matrix according to a predetermined rearranging rule. And a database creation rearranging means for registering in the rescue processing database, wherein the rescue feasibility determination processing means is configured to determine an arrangement pattern of the defective portion actually found by a function test of the IC with a redundant circuit. A test expanding means for expanding into a bit matrix, and a test rearranging means for retrieving the same arrangement pattern from the rescue processing database after rearranging the bit matrix according to the predetermined rearranging rule. The method of claim 2, further comprising: Men's processing equipment. 4. A redundancy processing method for performing a repairability determination process for determining whether a defective portion of an IC with a redundant circuit having a plurality of redundant circuits can be repaired by replacing the defective circuit with the redundant circuit. In the method, the arrangement pattern of the rescuable defective portion and the rescue solution as a combination of the redundant circuit corresponding to the arrangement pattern are registered in a rescue processing database in advance, and in the rescue possibility determination processing, From the registered arrangement patterns in the processing database,
A redundancy processing method, wherein a search is made for a pattern identical to an arrangement pattern of an actually occurring defective portion, and the rescue determination processing is performed using the registered rescue solution corresponding to the same arrangement pattern. 5. A resilience determining unit that determines whether a defective portion of an IC with a redundant circuit having a spare row and a spare column as a redundant circuit can be remedied by replacing it with at least one of the spare row and the spare column. In the redundancy processing method for performing the judgment processing, the defective part can be remedied by replacing the arrangement pattern of the rescuable defective part with the spare row and the spare column in combination with the preparatory processing as a preparatory processing for each product. The rescue solution is registered in the rescue process database, and by this process as a rescue possibility determination process, the same layout pattern as the layout pattern of the defective portion actually found by the functional test of the IC with a redundant circuit is obtained. A search is made from the rescue processing database to find the same arrangement pattern. Performing the repairability determining processing using the repair solution are registered in response, redundancy processing method characterized by.