JPH11111727A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH11111727A
JPH11111727A JP9265305A JP26530597A JPH11111727A JP H11111727 A JPH11111727 A JP H11111727A JP 9265305 A JP9265305 A JP 9265305A JP 26530597 A JP26530597 A JP 26530597A JP H11111727 A JPH11111727 A JP H11111727A
Authority
JP
Japan
Prior art keywords
region
emitter
semiconductor device
emitter region
type high
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9265305A
Other languages
Japanese (ja)
Inventor
Yutaka Tajima
豊 田島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP9265305A priority Critical patent/JPH11111727A/en
Publication of JPH11111727A publication Critical patent/JPH11111727A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent the breakage of a bipolar transistor having an emitter region on the main surface of a semiconductor substrate by suppressing the current which flows into the end section of the emitter region of the transistor, even when a large current flows to the transistor. SOLUTION: A PNP bipolar transistor 110 uses an N-type well 100 formed on the main surface of a P-type semiconductor substrate 1 as a base region and a P-type high-concentration region 101 formed on the main surface of the N-type well 100 as an emitter region. A plurality of trench grooves 102, having depths which are deeper than or nearly equal to the depth of the emitter region is formed in the emitter region and each small region in the emitter region divided or partitioned by the grooves 102 is connected electrically to another, except for the end sections of the P-type high-concentration region 101.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】 この発明は半導体装置に関
する。
[0001] The present invention relates to a semiconductor device.

【0002】[0002]

【従来の技術】 従来の半導体装置に関しては、例えば
図6に示すもの(特開昭55−91171号公報参照)
がある。以下、図6をもとに従来例の構造及び動作につ
いて説明する。P型半導体基板601主面にN型ウエル
619を形成し、かつN型ウエル619主面にP型高濃
度領域650とN型高濃度領域651を設ける。そして
P型高濃度領域650の一端を入力端子608に接続す
るとともに、他端を内部回路へ至る信号線609に接続
する。さらにN型ウエル619はN型高濃度領域651
を介してウエルコンタクト622に接続され、P型半導
体基板601は基板コンタクト612に接続される。そ
の結果、入力端子608と信号線609の間にP型高濃
度領域650から成る入力保護抵抗620が接続され
る。さらにP型高濃度領域650をエミッタ、N型ウエ
ル619をベース、P型半導体基板601をコレクタと
するPNPバイポーラトランジスタ(以下トランジスタ
はTrと略す)621が接続される。
2. Description of the Related Art A conventional semiconductor device is shown in FIG. 6 (see Japanese Patent Application Laid-Open No. 55-91171).
There is. Hereinafter, the structure and operation of the conventional example will be described with reference to FIG. An N-type well 619 is formed on the main surface of the P-type semiconductor substrate 601, and a P-type high concentration region 650 and an N-type high concentration region 651 are provided on the N-type well 619 main surface. Then, one end of the P-type high-concentration region 650 is connected to the input terminal 608, and the other end is connected to a signal line 609 leading to an internal circuit. Further, the N-type well 619 has an N-type high concentration region 651.
Is connected to the well contact 622, and the P-type semiconductor substrate 601 is connected to the substrate contact 612. As a result, the input protection resistor 620 including the P-type high-concentration region 650 is connected between the input terminal 608 and the signal line 609. Further, a PNP bipolar transistor (hereinafter, transistor is abbreviated as Tr) 621 having a P-type high concentration region 650 as an emitter, an N-type well 619 as a base, and a P-type semiconductor substrate 601 as a collector is connected.

【0003】次にこの従来例の動作を説明する。通常の
回路動作においては、信号は入力保護抵抗620を経て
内部回路に印加されるが、この部分はこの半導体装置の
動作に直接関係しないので詳細な説明は省略する。次
に、入力端子608に正の過電圧サージが印加される
と、PNPバイポーラTr621のエミッタ・ベース接
合がプルアップダイオードとして機能するとともに、こ
のPNPバイポーラTr621がターンオンするので、
サージに伴う過大電流を入力端子608からウエルコン
タクト622及びP型半導体基板601へバイパスす
る。このため、信号線609が接続されている内部回路
にはサージによる過大電圧が印加されず、かつサージに
よる過大電流も注入されない。よってサージによる内部
回路の破壊が防止される。また信号線608に負の過電
圧サージが印加されると、PNPバイポーラTr621
の逆Trがターンオンすることにより、同様にしてサー
ジによる内部回路の破壊が防止される。
Next, the operation of this conventional example will be described. In a normal circuit operation, a signal is applied to an internal circuit through an input protection resistor 620. However, since this portion is not directly related to the operation of the semiconductor device, a detailed description is omitted. Next, when a positive overvoltage surge is applied to the input terminal 608, the emitter-base junction of the PNP bipolar Tr 621 functions as a pull-up diode, and the PNP bipolar Tr 621 turns on.
An excessive current caused by the surge is bypassed from the input terminal 608 to the well contact 622 and the P-type semiconductor substrate 601. Therefore, no excessive voltage due to the surge is applied to the internal circuit to which the signal line 609 is connected, and no excessive current due to the surge is injected. Therefore, destruction of the internal circuit due to the surge is prevented. When a negative overvoltage surge is applied to the signal line 608, the PNP bipolar Tr 621
By turning on the reverse Tr, the breakdown of the internal circuit due to the surge is similarly prevented.

【0004】[0004]

【発明が解決しようとする課題】 しかしながら、この
ような従来の半導体装置にあっては、以下に示す問題点
があった。PNPバイポーラTr621のベース電流は
N型ウエル619主面のN型高濃度領域651から注入
されるためベース内部に電圧降下が生じる。そのためN
型高濃度領域651に近いエミッタ領域端部ほどエミッ
タ・ベース接合の順バイアスが高くなるエミッタ電流集
中効果(詳細は、「半導体デバイス」P.123、古川
清二郎著、コロナ社発行を参照)が生じる。この効果は
Tr電流が大きくなるほど顕著になる。よって、過電圧
サージの印加によってPNPバイポーラTr621がタ
ーンオンし、サージによる大電流がこのPNPバイポー
ラTr621に流れると、前述のエミッタ電流集中効果
により、PNPバイポーラTr621のエミッタ領域で
あるP型高濃度領域650の端部に、サージによるTr
電流が集中し、その結果PNPバイポーラTr621が
破壊してしまう。この発明は、このような従来の問題点
に着目してなされたもので、半導体基板主面にエミッタ
領域を有するバイポーラTrにおいて、特にエミッタ領
域が半導体装置の入力端子もしくは出力端子、または高
電位端子あるいは低電位端子のいずれかに接続されるバ
イポーラTrにおいて、このエミッタ領域を複数のトレ
ンチ溝にて小領域に分割、もしくは区切り、かつ、これ
らの小領域を電気的に接続する構成としたため、バイポ
ーラTrに大電流が流れても、エミッタ領域の端部に流
れるTr電流が過大になることを抑えて、バイポーラT
rの破壊を防止できるという効果がある。
However, such a conventional semiconductor device has the following problems. Since the base current of PNP bipolar Tr 621 is injected from N-type high concentration region 651 on the main surface of N-type well 619, a voltage drop occurs inside the base. Therefore N
Current concentration effect that the forward bias of the emitter-base junction is higher at the end of the emitter region closer to the high-concentration region 651 (for details, see "Semiconductor Devices", page 123, Seijiro Furukawa, published by Corona Co.) . This effect becomes more pronounced as the Tr current increases. Therefore, the PNP bipolar Tr 621 is turned on by the application of the overvoltage surge, and when a large current due to the surge flows through the PNP bipolar Tr 621, the PNP bipolar Tr 621 has a P-type high concentration region 650 which is the emitter region of the PNP bipolar Tr 621 due to the emitter current concentration effect described above. At the end, a Tr
The current is concentrated, and as a result, the PNP bipolar Tr 621 is broken. The present invention has been made in view of such a conventional problem. In a bipolar Tr having an emitter region on a main surface of a semiconductor substrate, particularly, the emitter region has an input terminal or an output terminal of a semiconductor device, or a high potential terminal. Alternatively, in a bipolar Tr connected to one of the low potential terminals, the emitter region is divided or divided into small regions by a plurality of trenches, and these small regions are electrically connected. Even if a large current flows through the Tr, the Tr current flowing to the end of the emitter region is prevented from becoming excessive, and
There is an effect that the destruction of r can be prevented.

【0005】[0005]

【課題を解決するための手段】 上述の目的達成のた
め、請求項1記載の発明は、第1導電型の半導体基板主
面に形成された第2導電型ウエルをベース領域とし、前
記ウエル主面に形成された第1導電型の高濃度領域をエ
ミッタ領域とするバイポーラトランジスタにおいて、前
記エミッタ領域部分に複数のトレンチ溝を形成し、該ト
レンチ溝が前記エミッタ領域より深いか、または同等程
度の深さを有し、かつ、前記トレンチ溝で分割もしくは
区切られた前記エミッタ領域の内、該エミッタ領域を形
成する前記第1導電型高濃度領域の端部を除く、前記エ
ミッタ領域の各小領域を電気的に接続する構成とした。
In order to achieve the above object, according to the first aspect of the present invention, a well of a second conductivity type formed on a main surface of a semiconductor substrate of a first conductivity type is used as a base region, In a bipolar transistor having a first conductivity type high-concentration region formed on a surface as an emitter region, a plurality of trenches are formed in the emitter region, and the trenches are deeper than the emitter region or approximately the same. Each small region of the emitter region having a depth and excluding an end of the first conductivity type high-concentration region forming the emitter region among the emitter regions divided or separated by the trench groove Are electrically connected.

【0006】請求項2記載の半導体装置は、請求項1記
載の発明において、前記エミッタ領域が、半導体装置の
入力端子もしくは出力端子、または高電位端子あるいは
低電位端子のいずれかの端子に接続されている構成とし
た。
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the emitter region is connected to one of an input terminal or an output terminal of the semiconductor device, or a high potential terminal or a low potential terminal. Configuration.

【0007】請求項3記載の半導体装置は、請求項2記
載の発明において、前記エミッタ領域の端部近傍部分の
前記小領域を、前記基板主面に形成した抵抗領域を介し
て前記エミッタ領域中央部分の前記小領域と接続し、か
つ前記エミッタ領域中央部分の前記小領域を前記端子に
接続する構成とした。
According to a third aspect of the present invention, in the semiconductor device according to the second aspect of the present invention, the small region near the end of the emitter region is connected to the center of the emitter region via a resistance region formed on the main surface of the substrate. A portion connected to the small region, and the small region in the central portion of the emitter region is connected to the terminal.

【0008】請求項4記載の半導体装置は、請求項2ま
たは3記載の発明において、前記エミッタ領域端部近傍
の前記小領域の底面と接する前記ウエル内部で、かつ前
記底面と接する部分に第2導電型高濃度領域を形成し
た。
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the second or third aspect, wherein a second portion is provided inside the well in contact with the bottom surface of the small region near the end of the emitter region and at a portion in contact with the bottom surface. A conductive type high concentration region was formed.

【0009】請求項5記載の半導体装置は、請求項2乃
至4記載の発明において、前記エミッタ領域中央部分の
前記小領域が前記端子に接続され、かつ、前記エミッタ
領域中央部分の前記小領域から前記エミッタ領域の端部
近傍部分の前記小領域に至る電気的な経路が折れ線状
で、さらに前記エミッタ端部に近づくほどに前記経路が
長くなるように、前記エミッタ領域が前記トレンチ溝に
よって区切られている。
According to a fifth aspect of the present invention, in the semiconductor device according to any one of the second to fourth aspects, the small region in the central portion of the emitter region is connected to the terminal, and the small region in the central portion of the emitter region is connected to the small region. The emitter region is divided by the trench so that an electric path to the small region in the vicinity of the end of the emitter region is a polygonal line, and the path becomes longer as approaching the emitter end. ing.

【0010】[0010]

【発明の実施の形態】 以下、この発明を図面に基づい
て説明する。図1は実施の形態1の断面構造を示す図で
ある。まず図1をもとに断面構造を説明する。P型半導
体基板1主面にN型ウエル100を形成し、このN型ウ
エル100主面にP型高濃度領域101とN型高濃度領
域103を設ける。そしてP型高濃度領域101を複数
のトレンチ溝102により複数の小領域に分割するとと
もに、これらP型高濃度領域101の各小領域主面をA
l電極106にオーミック接続する。Al電極106
は、入力端子104に接続されるとともに、信号線10
5にも接続される。ここで信号線105は保護抵抗(図
示せず)を介して、内部回路に接続される。またN型高
濃度領域103は、ウエルコンタクト107を介して所
定の電圧、例えば半導体装置の高電位を供給するVdd
端子に接続される。またP型半導体基板1は、半導体装
置に低電位を供給するVss端子に接続される。
Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a cross-sectional structure of the first embodiment. First, the sectional structure will be described with reference to FIG. An N-type well 100 is formed on the main surface of the P-type semiconductor substrate 1, and a P-type high concentration region 101 and an N-type high concentration region 103 are provided on the N-type well 100 main surface. Then, the P-type high-concentration region 101 is divided into a plurality of small regions by a plurality of trenches 102, and the main surface of each of the small-regions of the P-type high-concentration region 101 is defined as A.
Ohmic connection is made to the 1 electrode 106. Al electrode 106
Is connected to the input terminal 104 and the signal line 10
5 is also connected. Here, the signal line 105 is connected to an internal circuit via a protection resistor (not shown). The N-type high-concentration region 103 has a predetermined voltage, for example, Vdd for supplying a high potential of the semiconductor device through the well contact 107.
Connected to terminal. The P-type semiconductor substrate 1 is connected to a Vss terminal that supplies a low potential to the semiconductor device.

【0011】次に、回路構成を説明する。トレンチ溝1
02で分割されたP型高濃度領域101の各小領域をエ
ミッタ、N型ウエル100をベース、P型半導体基板1
をコレクタとする複数のPNPバイポーラTr110が
形成され、かつこれらPNPバイポーラTr110は、
互いに並列接続される。ここでP型高濃度領域101内
部の各小領域にはそれぞれのPNPバイポーラTr11
0のエミッタ抵抗111が形成されるとともに、N型ウ
エル100内部にPNPバイポーラTr110のベース
抵抗112が形成される。
Next, the circuit configuration will be described. Trench groove 1
02, each small region of the P-type high-concentration region 101 is an emitter, the N-type well 100 is a base, and the P-type semiconductor substrate 1 is
Are formed as a plurality of PNP bipolar Trs 110, and these PNP bipolar Trs 110 are
They are connected in parallel with each other. Here, each PNP bipolar Tr11 is provided in each small region inside the P-type high concentration region 101.
A zero emitter resistance 111 is formed, and a base resistance 112 of the PNP bipolar Tr 110 is formed inside the N-type well 100.

【0012】次に作用を説明する。通常の回路動作時
は、入力端子104に印加された信号は信号線105を
経て内部回路に伝達される。この部分は本発明に直接係
わる部分ではないので、詳細な説明は省略する。
Next, the operation will be described. During normal circuit operation, a signal applied to the input terminal 104 is transmitted to the internal circuit via the signal line 105. Since this part is not directly related to the present invention, a detailed description is omitted.

【0013】入力端子104に正の過電圧サージが印加
されると、PNPバイポーラTr110がターンオンし
て、サージに伴う過大電流を入力端子104からP型半
導体基板1にバイパスすることにより、内部回路に過大
電圧の印加や過大電流の注入を防ぐ。このためサージに
よる内部回路の破壊が防止される。
When a positive overvoltage surge is applied to the input terminal 104, the PNP bipolar Tr 110 is turned on, and an excessive current caused by the surge is bypassed from the input terminal 104 to the P-type semiconductor substrate 1, thereby causing an excessive circuit in the internal circuit. Prevents voltage application and excessive current injection. Therefore, the destruction of the internal circuit due to the surge is prevented.

【0014】ここで本実施の形態で、サージ印加による
PNPバイポーラTrの破壊も防止できる理由を説明す
る。入力端子に正の過電圧サージが印加されると、サー
ジ電流は、N型ウエル100内部に形成され互いに並列
に接続されているPNPバイポーラTr110を流れて
いく。この際前述のエミッタ電流集中効果により、バイ
ポーラTr電流は、ベースコンタクトであるN型高濃度
領域103に近い部分のPNPバイポーラTr110ほ
ど大きくなる。この場合、トレンチ溝102がエミッタ
領域であるN型高濃度領域101を複数の小領域に分割
しているので、 大電流が流れるPNPバイポーラTr110ほどエミ
ッタ抵抗111での電圧降下により、エミッタベース接
合での順バイアスの増加が抑制され、Tr電流の増加が
抑えられる。 PNPバイポーラTr110のエミッタベース接合
は、N型高濃度領域101の底面のみである。このため
エミッタベース接合の一部分に集中することなく、大き
なTr電流が流れ、PNPバイポーラTr110は高水
準注入状態になる。この結果、より一層Tr電流の増加
が抑えられる。 以上より、サージ電流が一部のバイポーラTr、すなわ
ちP型高濃度領域101とN型ウエル100が成すpn
接合の一部分に集中しにくくなるので、PNPバイポー
ラTr110ひいては半導体装置の破壊が起きにくくな
る。
Here, the reason why the present embodiment can prevent the destruction of the PNP bipolar transistor due to the application of a surge will be described. When a positive overvoltage surge is applied to the input terminal, the surge current flows through the PNP bipolar Tr 110 formed inside the N-type well 100 and connected in parallel with each other. At this time, due to the emitter current concentration effect described above, the bipolar Tr current increases in the portion of the PNP bipolar Tr 110 closer to the N-type high-concentration region 103 serving as the base contact. In this case, since the trench 102 divides the N-type high-concentration region 101, which is the emitter region, into a plurality of small regions, the PNP bipolar Tr 110 through which a large current flows becomes smaller at the emitter-base junction due to the voltage drop at the emitter resistor 111. , The increase in the forward bias is suppressed, and the increase in the Tr current is suppressed. The emitter-base junction of PNP bipolar Tr 110 is only at the bottom of N-type high concentration region 101. Therefore, a large Tr current flows without concentrating on a part of the emitter-base junction, and the PNP bipolar Tr 110 enters a high-level injection state. As a result, an increase in the Tr current is further suppressed. As described above, the surge current causes a part of the bipolar Tr, that is, the pn formed by the P-type high concentration region 101 and the N-type well 100.
Since it is difficult to concentrate on a part of the junction, breakdown of the PNP bipolar Tr 110 and the semiconductor device is less likely to occur.

【0015】なお、単にP型高濃度領域101の端部の
みをトレンチ溝102で囲む場合と比べても、本実施の
形態は以下の理由によりサージに起因する破壊耐量が高
くなる。P型高濃度領域101の端部だけにトレンチ溝
102を形成しても、エミッタ抵抗111はほとんど生
じないので上記の効果は生じない。かつ、Tr電流は
P型高濃度領域101の底面のみを流れるが、前述のエ
ミッタ電流集中効果によりベースコンタクトに近いP型
高濃度領域101端部近傍での電流密度が高くなる。前
記の効果が無いことと合わさって、この部分にTr電
流が集中する。よってサージによりTrが破壊に至る可
能性が高い。
In addition, compared to the case where only the end of the P-type high-concentration region 101 is simply surrounded by the trench groove 102, the present embodiment has a higher breakdown strength due to surge for the following reason. Even if the trench 102 is formed only at the end of the P-type high-concentration region 101, the above effect does not occur because the emitter resistance 111 hardly occurs. In addition, although the Tr current flows only through the bottom surface of the P-type high-concentration region 101, the current density near the end of the P-type high-concentration region 101 near the base contact increases due to the above-described emitter current concentration effect. Combined with the absence of the above effect, the Tr current concentrates on this portion. Therefore, there is a high possibility that the surge will destroy the Tr.

【0016】図2に、実施の形態2の構造を示す。本実
施の形態2では、実施の形態1の構造において、P型高
濃度領域101端部近傍部分の、トレンチ溝102で分
割された前記小領域を、この小領域主面上に形成された
抵抗領域200、例えばP+ 型ポリシリコン領域を介し
て、P型高濃度領域101中央部分の小領域と接続す
る。そして、このP型高濃度領域101中央部分の小領
域を入力端子104に接続している。実施の形態2は以
上の点が実施の形態1と異なり、その他の構造は、実施
の形態1と同じである。
FIG. 2 shows the structure of the second embodiment. In the second embodiment, in the structure of the first embodiment, the small region divided by the trench 102 near the end of the P-type high-concentration region 101 is replaced by a resistor formed on the main surface of the small region. A region 200, for example, a P + -type polysilicon region is connected to a small region at the center of the P-type high concentration region 101. The small area at the center of the P-type high-concentration area 101 is connected to the input terminal 104. The second embodiment is different from the first embodiment in the above points, and the other structure is the same as that of the first embodiment.

【0017】次に作用を説明する。本実施の形態2で
は、抵抗領域200部分の抵抗成分が実施の形態1で説
明したPNPバイポーラTr110のエミッタ抵抗11
1に直列に接続されている。このため実施の形態1での
の効果により、P型高濃度領域101端部近傍でのP
NPバイポーラTr110の破壊が起きにくくなる。こ
の結果、より一層サージ印加による半導体装置の破壊が
防止される。
Next, the operation will be described. In the second embodiment, the resistance component of the resistance region 200 is the emitter resistance 11 of the PNP bipolar Tr 110 described in the first embodiment.
1 in series. Therefore, due to the effect of the first embodiment, the P-type near the end of the P-type high-concentration region 101
Destruction of the NP bipolar Tr110 is less likely to occur. As a result, the destruction of the semiconductor device due to the application of the surge is further prevented.

【0018】図3に、実施の形態3の構造を示す。本実
施の形態3では、実施の形態1の構造において、P型高
濃度領域101端部近傍のトレンチ溝102で分割され
た小領域の底面と接するN型ウエル100内部で、か
つ、この小領域底面と接する部分に、N型高濃度領域3
00を形成している。実施の形態3は以上の点が実施の
形態1と異なり、その他の構成は、実施の形態1と同じ
である。
FIG. 3 shows the structure of the third embodiment. In the third embodiment, in the structure of the first embodiment, inside the N-type well 100 contacting the bottom surface of the small region divided by the trench 102 near the end of the P-type high-concentration region 101 and the small region N-type high concentration region 3
00 is formed. The third embodiment is different from the first embodiment in the above points, and the other configuration is the same as the first embodiment.

【0019】次に作用を説明する。本実施の形態3では
P型高濃度領域101端部近傍でのPNPバイポーラT
r110のベース濃度が上がるためRFEが低下する。
このためサージ印加によりPNPバイポーラTr110
がターンオンしても、実施の形態1と比較して、P型高
濃度領域101端部近傍でのPNPバイポーラTr11
0の電流バイアス能力が低下する。よって、この端部近
傍のPNPバイポーラTr110への過度な電流集中が
さらに抑制されて、サージによるTr電流が各PNPバ
イポーラTr110をより一層平均化して流れる。この
結果、サージによる半導体装置の破壊がより防止され
る。
Next, the operation will be described. In the third embodiment, the PNP bipolar T near the end of the P-type high concentration region 101
Since the base concentration of r110 increases, RFE decreases.
Therefore, the PNP bipolar Tr110
Is turned on, the PNP bipolar Tr11 near the end of the P-type high concentration region 101 is different from that of the first embodiment.
0 current bias capability is reduced. Therefore, excessive current concentration on the PNP bipolar Tr 110 near this end is further suppressed, and a Tr current due to a surge flows through each PNP bipolar Tr 110 in a more averaged manner. As a result, the destruction of the semiconductor device due to the surge is further prevented.

【0020】図4に、実施の形態4の構造を示す。本実
施の形態4では、実施の形態1の構造において、P型高
濃度領域をトレンチ溝にて分割するのではなく、P型高
濃度領域401をトレンチ溝402にて、P型高濃度領
域401中央部分からP型高濃度領域401端部近傍部
分に至る電気的な経路が折れ線状で、さらにP型高濃度
領域401端部に近づくほどにこの経路が長くなるよう
に区切り、かつ、P型高濃度領域401の中央部分のみ
が入力端子104に接続されている。実施の形態4は、
以上の点が実施の形態1と異なり、その他の構造は実施
の形態1と同じである。
FIG. 4 shows the structure of the fourth embodiment. In the fourth embodiment, in the structure of the first embodiment, the P-type high-concentration region 401 is not divided by the trench, but the P-type high-concentration region 401 is formed by the trench 402. The electric path from the central portion to the vicinity of the end of the P-type high-concentration region 401 is a polygonal line, and the path is divided such that the longer the closer to the end of the P-type high-concentration region 401, the longer the path. Only the central portion of the high concentration region 401 is connected to the input terminal 104. Embodiment 4
The above points are different from the first embodiment, and other structures are the same as the first embodiment.

【0021】次に作用を説明する。本実施の形態4で
は、P型高濃度領域401端部近傍でのPNPバイポー
ラTr110において、P型高濃度領域401内部の抵
抗が直列に接続され、しかもこの直列に接続される抵抗
の値は、P型高濃度領域401の端部に近づくほど大き
くなる。さらに、この抵抗の値は、トレンチ溝402に
よるP型高濃度領域401の区切り方を調整することに
より任意の値に設計できる。よって実施の形態1で述べ
たの効果により、さらにP型高濃度領域401端部近
傍のPNPバイポーラTr110への過度な電流集中が
抑制され、PNPバイポーラTr110を流れるサージ
電流がより一層平均化される。この結果、サージによる
半導体装置の破壊がさらに防止される。
Next, the operation will be described. In the fourth embodiment, in the PNP bipolar Tr 110 near the end of the P-type high-concentration region 401, the resistance inside the P-type high-concentration region 401 is connected in series, and the value of the resistor connected in series is It becomes larger as it approaches the end of the P-type high concentration region 401. Further, the value of this resistance can be designed to an arbitrary value by adjusting the way of dividing the P-type high-concentration region 401 by the trench 402. Therefore, due to the effect described in the first embodiment, excessive current concentration on PNP bipolar Tr 110 near the end of P-type high concentration region 401 is further suppressed, and surge current flowing through PNP bipolar Tr 110 is further averaged. . As a result, the destruction of the semiconductor device due to the surge is further prevented.

【0022】さらに本実施の形態4では、実施の形態2
での抵抗領域200、及び実施の形態3でのN型高濃度
領域300のような新たな領域を形成する必要がないの
で、製造コストの増大を抑えられる。
Further, in Embodiment 4, Embodiment 2
Since there is no need to form a new region such as the resistance region 200 in FIG. 1 and the N-type high-concentration region 300 in the third embodiment, an increase in manufacturing cost can be suppressed.

【0023】なお、以上述べた各実施の形態では、PN
PバイポーラTrを例に説明した。NPNバイポーラT
rの場合でも各実施の形態の作用は等しく生じる。この
場合は、各実施の形態でN型高濃度領域とP型高濃度領
域、及び高電位を供給するVdd端子と低電位を供給す
るVss端子を入れ換えれば良い。またトレンチ溝はP
型高濃度領域よりも必ずしも深く形成せずに、同程度の
深さにしても、同程度の効果が生じる。例えば図5に示
すように、実施の形態1において、トレンチ溝500を
P型高濃度領域101と同程度か若干浅く形成しても、
実施の形態1とほぼ同じ作用が生じる。実施の形態2、
3及び4でも同様である。
In each of the embodiments described above, PN
The P bipolar transistor has been described as an example. NPN bipolar T
Even in the case of r, the operation of each embodiment is equally generated. In this case, in each embodiment, the N-type high-concentration region and the P-type high-concentration region, and the Vdd terminal for supplying a high potential and the Vss terminal for supplying a low potential may be exchanged. The trench is P
The same effect can be obtained even if it is not necessarily formed deeper than the high-concentration region and is set to the same depth. For example, as shown in FIG. 5, in the first embodiment, even if the trench 500 is formed to be approximately the same as or slightly shallower than the P-type high-concentration region 101,
Almost the same operation as in the first embodiment occurs. Embodiment 2,
The same applies to 3 and 4.

【0024】[0024]

【発明の効果】 以上説明してきたように本発明の半導
体装置にあっては、エミッタ領域を複数のトレンチ溝に
て小領域に分割、もしくは区切り、かつ、これらの小領
域を電気的に接続する構成としたため、バイポーラTr
に大電流が流れても、エミッタ領域の端部に流れるTr
電流が過大になることを抑えて、バイポーラTrの破壊
を防止し、サージ印加による半導体装置の破壊を防止す
ることができる。
As described above, in the semiconductor device of the present invention, the emitter region is divided or divided into small regions by the plurality of trenches, and these small regions are electrically connected. Configuration, the bipolar Tr
Tr flows to the end of the emitter region even if a large current
It is possible to prevent the current from becoming excessive, prevent the bipolar transistor from being damaged, and prevent the semiconductor device from being damaged by the application of a surge.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 実施の形態1の断面構造を示す図である。FIG. 1 is a diagram showing a cross-sectional structure of a first embodiment.

【図2】 実施の形態2の断面構造を示す図である。FIG. 2 is a diagram illustrating a cross-sectional structure according to a second embodiment;

【図3】 実施の形態3の断面構造を示す図である。FIG. 3 is a diagram illustrating a cross-sectional structure according to a third embodiment;

【図4】 実施の形態4の断面構造を示す図である。FIG. 4 is a diagram showing a cross-sectional structure according to a fourth embodiment.

【図5】 実施の形態1の第2の断面構造を示す図であ
る。
FIG. 5 is a diagram illustrating a second cross-sectional structure according to the first embodiment;

【図6】 従来例の断面構造を示す図である。FIG. 6 is a diagram showing a cross-sectional structure of a conventional example.

【符号の説明】[Explanation of symbols]

1 P型半導体基板 100 N型ウエル 101 P型高濃度領域 102 トレンチ溝 103 N型高濃度領域 104 入力端子 105 信号線 106 Al電極 107 ウエルコンタクト 110 PNPバイポーラTr 111 エミッタ抵抗 112 ベース抵抗 200 抵抗領域 300 N型高濃度領域 401 P型高濃度領域 402 トレンチ溝 500 トレンチ溝 601 P型半導体基板 608 入力端子 609 信号線 612 基板コンタクト 619 N型ウエル 620 入力保護抵抗 621 PNPバイポーラTr 622 ウエルコンタクト 650 P型高濃度領域 651 N型高濃度領域 Reference Signs List 1 P-type semiconductor substrate 100 N-type well 101 P-type high concentration region 102 Trench groove 103 N-type high concentration region 104 Input terminal 105 Signal line 106 Al electrode 107 Well contact 110 PNP bipolar Tr 111 Emitter resistance 112 Base resistance 200 Resistance region 300 N-type high-concentration region 401 P-type high-concentration region 402 Trench groove 500 Trench groove 601 P-type semiconductor substrate 608 Input terminal 609 Signal line 612 Substrate contact 619 N-type well 620 Input protection resistor 621 PNP bipolar Tr 622 Well contact 650 P-type high Concentration area 651 N-type high concentration area

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 第1導電型の半導体基板主面に形成され
た第2導電型ウエルをベース領域とし、前記ウエル主面
に形成された第1導電型の高濃度領域をエミッタ領域と
するバイポーラトランジスタにおいて、 前記エミッタ領域部分に複数のトレンチ溝を形成し、該
トレンチ溝が前記エミッタ領域より深いか、または同等
程度の深さを有し、 かつ、前記トレンチ溝で分割もしくは区切られた前記エ
ミッタ領域の内、該エミッタ領域を形成する前記第1導
電型高濃度領域の端部を除く、前記エミッタ領域の各小
領域を電気的に接続したことを特徴とする半導体装置。
1. A bipolar having a second conductivity type well formed on a main surface of a semiconductor substrate of a first conductivity type as a base region and a high concentration region of the first conductivity type formed on the main surface of the well as an emitter region. In the transistor, a plurality of trench grooves are formed in the emitter region portion, the trench grooves are deeper than or equal to the emitter region, and the emitter is divided or divided by the trench grooves. A semiconductor device, wherein each of the small regions of the emitter region, except for the end of the high-concentration region of the first conductivity type forming the emitter region, is electrically connected.
【請求項2】 請求項1記載の半導体装置において、 前記エミッタ領域が、半導体装置の入力端子もしくは出
力端子、または高電位端子あるいは低電位端子のいずれ
かの端子に接続されていることを特徴とする半導体装
置。
2. The semiconductor device according to claim 1, wherein the emitter region is connected to an input terminal or an output terminal of the semiconductor device, or one of a high potential terminal and a low potential terminal. Semiconductor device.
【請求項3】 請求項2記載の半導体装置において、 前記エミッタ領域の端部近傍部分の前記小領域を、前記
基板主面に形成した抵抗領域を介して前記エミッタ領域
中央部分の前記小領域と接続し、 かつ前記エミッタ領域中央部分の前記小領域を前記端子
に接続したことを特徴とする半導体装置。
3. The semiconductor device according to claim 2, wherein the small region near an end of the emitter region is connected to the small region at a central portion of the emitter region via a resistance region formed on the main surface of the substrate. A semiconductor device, wherein the small region at the center of the emitter region is connected to the terminal.
【請求項4】 請求項2または3記載の半導体装置にお
いて、 前記エミッタ領域端部近傍の前記小領域の底面と接する
前記ウエル内部で、かつ前記底面と接する部分に第2導
電型高濃度領域を形成したことを特徴とする半導体装
置。
4. The semiconductor device according to claim 2, wherein a high-concentration region of the second conductivity type is provided inside the well in contact with the bottom surface of the small region near the end of the emitter region and in a portion in contact with the bottom surface. A semiconductor device characterized by being formed.
【請求項5】 請求項2乃至4記載の半導体装置におい
て、 前記エミッタ領域中央部分の前記小領域が前記端子に接
続され、 かつ、前記エミッタ領域中央部分の前記小領域から前記
エミッタ領域の端部近傍部分の前記小領域に至る電気的
な経路が折れ線状で、さらに前記エミッタ端部に近づく
ほどに前記経路が長くなるように、前記エミッタ領域が
前記トレンチ溝によって区切られていることを特徴とす
る半導体装置。
5. The semiconductor device according to claim 2, wherein the small region in the central portion of the emitter region is connected to the terminal, and the small region in the central portion of the emitter region is connected to an end of the emitter region. An electric path leading to the small region in the vicinity is a polygonal line, and the emitter region is separated by the trench groove such that the path becomes longer as approaching the emitter end. Semiconductor device.
JP9265305A 1997-09-30 1997-09-30 Semiconductor device Pending JPH11111727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9265305A JPH11111727A (en) 1997-09-30 1997-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9265305A JPH11111727A (en) 1997-09-30 1997-09-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH11111727A true JPH11111727A (en) 1999-04-23

Family

ID=17415360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9265305A Pending JPH11111727A (en) 1997-09-30 1997-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH11111727A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010239119A (en) * 2009-03-11 2010-10-21 Renesas Electronics Corp Esd protection element
JP2015029103A (en) * 2009-03-11 2015-02-12 ルネサスエレクトロニクス株式会社 Esd protection element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010239119A (en) * 2009-03-11 2010-10-21 Renesas Electronics Corp Esd protection element
US8860139B2 (en) 2009-03-11 2014-10-14 Renesas Electronics Corporation ESD protection element
JP2015029103A (en) * 2009-03-11 2015-02-12 ルネサスエレクトロニクス株式会社 Esd protection element
US9177949B2 (en) 2009-03-11 2015-11-03 Renesas Electronics Corporation ESD protection element

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