JPH11111689A - Etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a substantially vertical anisotropic etching of a tungsten or tungsten silicide layer by exposing the underlying surface in first step and then etching an objective layer in second step, using a second kind of etching gas having composition different from that of a first kind of etching gas. SOLUTION: An etching mask having an isolated pattern formed between wide space parts and a plurality of fine patterns arranged through a narrow space part is formed on a layer of tungsten or tungsten silicide to be etched which is formed on the underlying surface. The layer to be etched is then etched with a first gas via the etching mask to expose the underlying surface at the wide space part and further etched with second gas having composition different from that of the first gas. According to the method, substantially vertical anisotropic etching of a tungsten or tungsten silicide layer is made available using first gas of Cl2 or O2 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method, and more particularly to an etching method for etching a layer to be etched including a tungsten layer or a tungsten silicide layer.

[0002]

2. Description of the Related Art In recent years, tungsten and tungsten silicide have been widely used in semiconductor devices. Tungsten silicide is used as a kind of silicide to form a polycide electrode (wiring) by being stacked on a polycrystalline (poly) silicon layer, or used alone as a local wiring. Tungsten is deposited by chemical vapor deposition (CV).
In D), it can be selectively grown on a conductive region or can be grown on a blanket over the entire surface of a base, and is widely used as a conductive plug or a lower wiring. Note that tungsten can also be sputtered. The tungsten silicide layer is generally formed by CVD or by sputtering using tungsten silicide as a target.

Fine MOS in a highly integrated semiconductor integrated circuit
Many of the transistors have a polycide structure as a gate electrode. The threshold characteristic of the MOS transistor is secured by the lower silicon layer, and the resistance value of the gate electrode (wiring) is reduced by the upper silicide layer. The characteristics of the MOS transistor, particularly the operation speed, are greatly affected by the gate length. In order to produce a transistor with a narrow gate length with high precision, a technique for etching a polycide stack with high precision is desired.

Hereinafter, WSi is used for the gate electrode._Two/ PolyS
patterning process when using polycide lamination of i
explain. WSi_TwoIs a gas containing chlorine and oxygen gas
Etching is generally performed with a mixed gas of example
If the chlorine-containing gas is Cl _TwoIs used. Add oxygen gas
Addition of WOCl with relatively high vapor pressure_FourGenerate and etch
This is done to make it easier to use. Also, polySi
SiO2 etching_TwoWith gate oxide film
Often, oxygen gas is added to improve the selectivity.
No.

[0005] FIG. 5 shows Cl according to such a conventional technique.
₃ illustrates the etching of a WSi ₂ / polySi stack using ₂ / O ₂ plasma. A thin SiO ₂ layer 102 serving as a gate oxide film is formed on a Si substrate 101, and a polycrystalline (poly) Si layer 103 and a WSi ₂ layer 104 are stacked thereon. A resist mask 107 is formed on WSi ₂ layer 104. The resist mask 107 has a pattern corresponding to the gate shape. As the wiring of the LSI becomes finer, the aspect ratio (height / width) of the space S between the wirings increases.

A Cl ₂ / O ₂ gas is supplied to an upper space in the drawing, and a microwave of, eg, 2.45 GHz is supplied to supply Cl ₂ / O ₂ gas.
_{A 2} / O ₂ plasma 108 is generated. The wafer susceptor on which the silicon substrate 101 is placed is, for example, 1
A high frequency (RF) of 3.56 MHz is applied.

The etching conditions are, for example, pressure = 2 mTo
rr, microwave power = 1400 W, RF power = 4
0 W, the flow rate of the etching gas is Cl ₂ / O ₂ = 25/9
sccm.

According to the shape of the resist 107, the underlying WSi ₂ layer 104 is first etched substantially vertically. Eventually, the etching of the WSi ₂ layer 104 ends in a wide space where a wide space is exposed outside the resist mask 107. Even at this point, in the region where the space between the patterns is narrow, the etching rate of the WSi ₂ layer does not end because the microloading effect lowers the etching rate.

As the etching is continued, the etching of the WSi ₂ layer 104 further progresses in the narrow space portion, and the polling under the WSi ₂ layer in the wide space portion.
The etching of the ySi layer 103 proceeds. Eventually, the etching of the WSi ₂ layer 104 is completed even in the narrow space portion, and the underlying polySi layer 103 is etched. Pol in a narrow space following a wide space
When the etching of the ySi layer 103 is completed, the shape becomes as shown in the figure.

At this time, WSi_TwoNarrow space of layer 104
The side wall facing the part has an inverse tapered shape as shown in the figure.
Would. This is due to the etching and over-
Excessive oxygen and WSi during etching_TwoLayer of
The side wall reacts with WOCl _xTo form and evaporate
To WSi_TwoIt is thought that the side wall of the layer is etched.
Have been.

As described above, when the side wall of the WSi ₂ layer has an inversely tapered shape, in the subsequent ion implantation step, impurities are also implanted immediately below the gate electrode, and the effective gate length changes. Further, since the shape and dimensions of the side wall spacers are different from those in the case where the gate side walls are vertical, there is a possibility that the gain and the life of the MOS transistor do not become desired values.

It is conceivable to increase the ion energy in order to prevent the occurrence of the reverse tapered shape, thereby increasing the etching anisotropy. However, when the ion energy is increased, the etching selectivity of the resist is reduced, so that the resist film thickness must be increased. When the resist film is thickened, the resolution of photolithography is impaired, and the processing accuracy is reduced.

Japanese Patent Application Laid-Open No. 1-239932 discloses a method of etching a stack of a tungsten silicide layer and a polysilicon layer using an etching gas obtained by mixing chlorine gas (Cl ₂ ) and nitrogen gas (N ₂ ). is suggesting.
It is reported that when this etching gas is used, the tungsten silicide layer is etched in a forward tapered shape, and the polysilicon layer is etched vertically (page 3, lower right column to page 4, upper right column).

Further this publication, when etching the underlying polysilicon layer, followed main etch to over-etching using a mixed gas of chlorine gas and nitrogen gas and SiCl ₄ gas to etch the remaining film technology (Upper right column of page 4 to lower right column of page 4).

US Pat. No. 5,219,485 discloses various etching steps for polycide electrodes.
As one of them, a method of etching a stacked structure of a tungsten silicide layer and a polysilicon layer with a mixed gas of BCl ₃ / Cl ₂ / NF ₃ has been proposed. NF ₃
When etching the WSi ₂ layer, a fluoride (WF ₆ ) of W having a high vapor pressure is formed and used to increase the etching rate (FIG. 15, column 9, line 1 to line 19).

[0016]

As described above,
When the stacked structure of the tungsten silicide layer and the polysilicon layer is etched with Cl ₂ / O ₂ gas, the tungsten silicide layer is etched in a reverse taper shape. Instead of Cl ₂ / O _2, the use of Cl ₂ / N _2, although the WSi ₂ layer is reversed taper shape can be prevented, resulting in a forward tapered shape in reverse. In the etching of a fine pattern, it is desirable that the sidewall can be formed almost vertically in order to improve the pattern accuracy of the etching.

An object of the present invention is to provide a method of anisotropic etching capable of etching a tungsten or tungsten silicide layer almost vertically.

Another object of the present invention is to provide an anisotropic etching method capable of substantially vertically etching a stack of a tungsten or tungsten silicide layer and a polysilicon layer.

[0019]

According to one aspect of the present invention, an isolated pattern sandwiched between wide spaces is formed on an etching target layer formed on a base surface and formed of tungsten or tungsten silicide. Forming an etching mask including a plurality of dense patterns arranged via a narrow space portion; and etching the etching target layer with a first type of gas via the etching mask, thereby forming the wide space. A first etching step of exposing a base surface of a portion, and a second etching step following the first etching step, etching the remaining etching target layer with a second type of etching gas having a composition different from the first type. And an etching method comprising:

The tungsten or tungsten silicide layer can be substantially vertically anisotropically etched with a first type of gas, such as Cl ₂ / O ₂ .

When a high-pattern-density region having a narrow space portion and a low-pattern-density region having a wide space portion coexist on the same substrate, even if etching is completed in a low-pattern-density region due to a microloading effect. Etching is not yet finished in a region having a high pattern density. In order to complete the etching in the region having a high pattern density, a second gas different from the first type gas is used.
When the remaining tungsten or tungsten silicide layer is over-etched using an etching gas of the type described above, the whole tungsten or tungsten silicide layer can be anisotropically etched substantially vertically.

When a silicon layer exists under the tungsten or tungsten silicide layer, it is desired that the silicon layer is also vertically etched. By selecting the second type of gas, the silicon layer can also be etched substantially vertically.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, Japanese Patent Application Laid-Open
No. 932 proposes a method of dry-etching a gate laminated film having a polycide structure using an etching gas containing a chlorine-based gas containing a chlorine atom in a molecule and a nitrogen gas. However, according to this method, the silicide film is etched in a forward tapered shape. The polysilicon layer below the silicide layer necessarily has a wider width than the resist pattern. Therefore, when a MOS transistor or the like having an extremely short gate length is produced, this method has limitations. In addition, if the forward taper shape cannot be accurately controlled, the pattern accuracy in the etching step will be reduced.

Judging from the RIE lag data of WSi _2, a pattern in which the aspect ratio (height / width) of the space portion of the line-and-space pattern exceeds 1 is defined as a dense pattern (high-density pattern). be able to. In an actual semiconductor device, a wiring pattern or the like in a memory cell region can be defined as a high-density pattern or a region with dense wiring.

When the etching is completed, the upper end of the cross-sectional shape of the wiring coincides with the lower end of the resist mask,
If there is obtained a state where there is no side-etched portion from the end of the resist mask, the etching can be defined as taper etching. According to this definition, the anisotropic etching for forming a wiring having vertical side walls is also a taper etching.

The forward taper means that the elevation angle of the cross section of the etched wiring layer as viewed from the underlying surface is 0 ° to 90 °.
° refers to the etched shape.

In the cross-sectional shape of the etched wiring layer, the elevation angle as viewed from the substrate side exceeds 90 ° and is 180 °.
In such a case, such a taper can be defined as a reverse taper. As for the structure of the semiconductor device, it is preferable that the etching be taper etching and a forward tapered shape be formed. Even if a cross-sectional shape of a forward taper can be created, it is difficult to achieve high pattern accuracy in the case where erosion occurs at the mask edge (non-taper etching).

From the end of the etching of the target layer in the low-density pattern region having a wide space portion outside the pattern, it is targeted in the high-density pattern region having only a narrow space portion between the patterns. Etching until the layer is completely removed is defined as overetching.

The present inventors have examined in more detail the properties of anisotropic etching using Cl ₂ / N ₂ as an etching gas.

FIG. 3 is a cross-sectional view schematically showing the configuration of an electron cyclotron resonance (ECR) plasma etcher used in this preliminary experiment and also used in the embodiment of the present invention. The housing 20 of the etcher device is formed of metal and defines a waveguide 26 and a reaction chamber 21 therein.

At the boundary between the waveguide 26 and the reaction chamber 21, a transmission window 27 for transmitting microwaves such as quartz glass is provided in an airtight manner. 2.45 GH from above waveguide 26
The microwave of z is supplied to guide the microwave into the reaction chamber 21. The reaction chamber 21 has a two-stage structure of a narrow part and a wide part, and is provided with electromagnets 24 and 25 on the outside thereof. By introducing microwaves into the magnetic field generated by these electromagnets 24 and 25, the ECR condition is satisfied. A gas supply hole (not shown) and an exhaust hole 33 are connected to the reaction chamber 21.

A lower portion of the reaction chamber is provided with a wafer susceptor 28 which is airtightly connected to the housing and serves as a lower electrode. The wafer susceptor 28 has, for example, 1
A 3.56 MHz high frequency power supply 29 is connected. A silicon wafer 31 is placed on the wafer susceptor 28, an ECR plasma is generated in the reaction chamber 21, and an etching experiment is performed.

FIG. 4A shows one of the samples used in the experiment.
One configuration is shown schematically. On the Si substrate 40, WSi
_Two layers 41 are formed, and a resist pattern 42 is formed thereon. E using this resist pattern 42 as an etching mask and Cl ₂ / N ₂ as an etching gas.
CR plasma etching was performed. The etching conditions are as follows.

Pressure = 2 mTorr, microwave power = 1400 W, RF (13.56 MHz) power = 40 W, Cl ₂ + N ₂ = 30-100 sccm When the WSi ₂ layer 41 is etched under these conditions,
As shown in FIG. 4A, the WSi ₂ layer 41 was etched in a forward tapered shape. The taper angle between the forward tapered side wall and the Si substrate 40 is represented by θ. The WSi ₂ layer 41 was etched by changing the total gas flow rate of the etching gas and the N ₂ flow rate ratio (%) in the etching gas. The results are shown in FIG.

As is clear from the graph of FIG.
As the N ₂ flow rate is increased, the forward taper angle gradually decreases. The taper angle θ shows a continuous change with respect to the change of the total gas flow rate. Such a change in the forward taper angle causes the nitride of W (WN _x ) as the etching proceeds.
This is considered to be because nitride of Si and Si adhere to the sidewall of the WSi ₂ layer 41. It is considered that the result of FIG. 4B indicates that when the flow rate ratio of N ₂ is increased, the amount of nitride deposited on the sidewall protective film is increased.

The present inventor further conducted experiments in which the pattern density of the resist pattern was changed.

FIG. 4C schematically shows the shape of the sample used in the experiment. As with the sample of FIG.
A WSi ₂ layer 41 was deposited on a substrate 40, and a resist pattern 42 was formed thereon. Resist pattern 42
Is a pattern having a narrow space in which patterns with a line width of 0.5 μm are arranged in parallel at intervals of 0.5 μm (left side in the figure), and an isolated pattern in which a pattern with a width of 0.5 μm is isolated in a wide space. It has a wiring portion (right side in the figure). The etching conditions were the same as in the above experiment: pressure = 2 mTorr, microwave power = 1400 W, RF power = 40 W, and Cl ₂ / N ₂ = 27/3 sccm. The etching depth of the WSi ₂ layer in the open space was set to 250 nm.

When the WSi ₂ layer 41 was etched under these conditions, a forward tapered shape with an elevation angle of 36 ° was formed in the isolated wiring pattern, and an etched shape having a forward tapered shape with an elevation angle of 53.5 ° was obtained in the dense wiring pattern. . That is, it has been found that the taper angle of the forward taper shape depends on the density of the pattern. The taper angle is expected to increase as the pattern density increases.

Interpreting the results of this experiment, it can be seen that a large amount of nitride sidewall protection film is deposited on the sidewalls of the isolated wiring pattern, and a small amount of sidewall protection film is deposited on the sidewalls of the dense wiring pattern arranged at a narrow interval. Presumed. In the case of dense wiring patterns arranged at narrow intervals, even if a sidewall protective film is deposited, the amount thereof is smaller than that of a wide open space, and it is presumed that the sidewall after etching approaches vertical.

In the above experiment, Cl ₂ was used as the gas containing chlorine, but Cl ₂ ,
HCl, BCl ₃ , SiCl ₂ , S ₂ Cl ₂ , CCl ₄
Or any combination of these could be used. Similar results would be obtained using tungsten instead of tungsten silicide.

When the tungsten or tungsten silicide layer is etched with a mixed gas of a chlorine-containing gas such as Cl ₂ and a nitrogen gas, it is unavoidable that the etched tungsten or tungsten silicide layer has a forward tapered cross section.

If an etching gas such as Cl ₂ / O ₂ is used, the etching can be performed with the sidewall of the tungsten or tungsten silicide layer being vertical. However, if this etching is continued after the etching in the low-density pattern region is completed and is continued until the etching in the high-density pattern region is completed, the cross-sectional shape of the tungsten or tungsten silicide layer in the high-density pattern region becomes an inversely tapered shape. Is as described in the prior art.

The present inventors have found that in anisotropic etching of a tungsten or tungsten silicide layer, a main etching step using an etching gas capable of obtaining a vertical sectional shape, and an etching including a mixed gas of a chlorine-containing gas and a nitrogen gas. It is proposed to use an over-etching step using a gas.

1 and 2 are sectional views of a semiconductor substrate showing main steps of an etching method according to an embodiment of the present invention.

As shown in FIG. 1A, a thin silicon oxide film 2 such as a gate oxide film is formed on the surface of a Si substrate 1, and a polycrystalline Si layer 3 and a tungsten silicide layer 4 are laminated thereon. accumulate. A photoresist pattern 7 is formed on the tungsten silicide layer 4. The photoresist pattern includes a dense pattern area NS in which patterns are densely packed at small intervals and a low density pattern area WS in which a large space exists on both sides of the pattern.

As shown in FIG. 1B, first, Cl ₂ / O
The main etching step of the tungsten silicide layer 4 is performed by the Cl ₂ / O ₂ plasma 8 using _two gases. This main etching step is an etching step until the tungsten silicide layer 4 is completely etched in the low density pattern region WS.

When this step is completed, a wide opening 5 in which the surface of the polycrystalline Si layer 3 is exposed is formed in the low density pattern region WS. In the high-density pattern region NS, since the etching rate is reduced due to the microloading effect, the groove 6 is formed which has advanced to the middle part of the thickness of the tungsten silicide layer 4.

As shown in FIG. 2C, an over-etching step is performed to completely etch the tungsten silicide layer 4 in the high-density pattern region NS. In this over-etching step, the etching gas is Cl ₂ / N
Convert it to ₂ .

As apparent from the above preliminary experiment, the tungsten silicide layer 4
A large amount of nitride protective film 11 is deposited on the side wall of the substrate. On the other hand, in the high-density pattern region NS, a small amount of the nitride protective film 12 is deposited. Therefore, in the low-density pattern region WS, a sufficient amount of the protective film 11 is deposited on the side wall of the tungsten silicide layer 4, and the tungsten silicide layer 4 is less likely to be etched in the lateral direction. For this reason, the vertical shape of the side wall is maintained, and the dimensional accuracy is maintained.

In the high-density pattern region NS, the nitride protective film 12 deposited on the side wall of the tungsten silicide layer 4 is small, and the etching of the tungsten silicide layer 4 is efficiently continued. The side walls have a slightly forward tapered shape or a substantially vertical shape. High density pattern area N
By the time the overetching is completed in S,
In the low density pattern region, the polycrystalline Si layer 3 under the tungsten silicide layer 4 is etched. This C
Etching of silicon with l ₂ / N ₂ forms vertical sidewalls. That is, in the over-etching step, an inversely tapered shape does not occur in the low-density pattern region, and a substantially vertical side wall is obtained. In the high-density pattern region, a vertical side wall is obtained.

FIG. 2D shows an anisotropic etching step of the polycrystalline Si layer. After the over-etching of the tungsten silicide layer 4 is completed, the gas is switched again and the polycrystalline Si layer 3 is vertically etched. The etching gas is switched to, for example, Cl ₂ / O ₂ and ECR plasma etching is performed. The Cl ₂ / O ₂ plasma 10 is SiO _2
It has the property of maintaining a high selectivity with respect to the _two layers 2 and capable of etching the Si layer 3 vertically.

The Si layer can be vertically etched also by the Cl ₂ / N ₂ plasma etching shown in FIG. Accordingly, the switching from the plasma etching of Cl ₂ / N _{2 to} the plasma etching of Cl ₂ / O ₂ may be performed when the SiO ₂ layer underlying the Si layer is exposed. W
It may be between the end of the overetching of the Si ₂ layer and the exposure of the SiO ₂ layer. The entire Si layer may be etched with Cl ₂ / N _{2 as} long as the selectivity with respect to the base can be obtained by etching with the Cl ₂ / N ₂ gas.

When the Si layer is vertically etched,
Since the protective film remains on the side wall of the tungsten silicide layer 4, it is possible to prevent the tungsten silicide layer from being etched to form an inversely tapered shape.

According to such a process, a polycide laminated structure composed of a laminated layer of a tungsten silicide layer and a silicon layer can be etched almost vertically.

Although Cl ₂ / O ₂ is used for etching the tungsten silicide layer, another etching gas capable of vertically etching tungsten or tungsten silicide may be used.

Although the case where the WSi ₂ layer / polycide layer of the silicon layer is etched has been described, a similar process can be used for etching the tungsten silicide layer or the single layer of the tungsten layer. In the over-etching step of the tungsten or tungsten silicide layer, it is important to use an etching gas containing a mixed gas of a gas containing chlorine and a nitrogen gas.

The silicon layer can be vertically etched with a gas containing chlorine and a gas containing nitrogen (eg, Cl ₂ / N ₂ ). Therefore, even after the etching of the tungsten or the tungsten silicide layer is completed, the etching may be continued with the mixed gas containing the gas containing chlorine and the nitrogen gas to etch the silicon layer below the tungsten or the tungsten silicide layer.

In addition to the etching of the polycide structure, a single layer of a tungsten or tungsten silicide layer may be etched as described above. In this case, of course, the etching step for only the silicon layer can be omitted.

The gate length of a MOS transistor is an important factor that determines the operation speed. When a portion with a low pattern density and a portion with a high pattern density exist on a semiconductor chip, a wide space portion exists on both sides of the gate electrode pattern in the portion with a low pattern density. In a portion where the pattern density is high, the gate electrode patterns are densely arranged at small intervals. In such a pattern shape, a microloading effect (or RIE lag) in which the etching rate is delayed in a portion where the pattern density is high occurs.

According to the prior art, a forward tapered shape occurs in all the patterns, or an inverse tapered shape occurs in a portion where the pattern density is high.

According to the above-described embodiment, first, a tungsten or tungsten silicide layer is anisotropically etched at a portion having a low pattern density by performing etching with high anisotropy using an etching gas of the first type. Form substantially vertical sidewalls.

Following this main etching step, an over-etching step of the tungsten or tungsten silicide layer is performed using an etching gas containing a gas containing chlorine and a nitrogen gas. In this over-etching step, it is considered that a sidewall protective film made of WN _x is deposited on the pattern sidewall. In addition, this nitride protective film
The amount to be deposited depends on the pattern density. In a portion having a low pattern density, a large amount is deposited, and the pattern side wall is strongly protected. On the other hand, in a portion where the pattern density is high, the amount of the deposited nitride protective film is small, and the degree to which the etched shape becomes a forward tapered shape can be reduced.

When etching is performed using the second type of etching gas from the beginning of etching, a strong forward taper shape is easily formed in a region having a wide space, but a vertical shape is formed in a portion having a coarse pattern density. Since the patterning having the pattern (1) has already been completed, the forward tapered shape can be prevented.

In a region with a large pattern density having a large space, the vertical shape of the side wall of the tungsten or tungsten silicide layer is protected by a protective film, and in a high-density pattern region having a narrow space of a reverse taper shape,
By reducing the protective film deposition amount, the degree of forward taper can be reduced.

Further, in this over-etching step, if a silicon layer exists under the tungsten or tungsten silicide layer, SiN generated by etching the silicon layer in a region having a low pattern density is used.
it is possible to protect the side wall by _x Cl _y. Therefore, side etching can be prevented.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, and combinations are possible.

[0067]

As described above, according to the present invention,
The tungsten or tungsten silicide layer can be anisotropically etched substantially vertically.

In the etching of the polycide structure,
Both the silicide layer and the silicon layer can be etched substantially vertically.

The amount of side etching can be suppressed, and high pattern accuracy can be obtained.

The dimensional accuracy of the etching can be increased, and a high-performance semiconductor integrated circuit can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor substrate showing main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor substrate showing main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view schematically showing a configuration of an ECR plasma etcher device.

FIG. 4 is a cross-sectional view and a three-dimensional graph for explaining a preliminary experiment performed by the inventor.

FIG. 5 is a cross-sectional view of a semiconductor substrate for explaining a conventional technique.

[Explanation of symbols]

1 Si substrate, 2 SiO ₂ layer, 3 silicon layer, 4 tungsten silicide layer, 5, 6
Opening, 7 Resist pattern, 8, 9, 10
plasma

Claims (7)

[Claims] 1. A plurality of densely-spaced patterns formed on a surface of an underlayer and formed on an etching target layer formed of tungsten or tungsten silicide via an isolated pattern sandwiched between wide spaces and a narrow space. A step of forming an etching mask including a pattern, a first etching step of etching the layer to be etched with a first type of gas through the etching mask, and exposing a base surface of the wide space portion; A second etching step of etching the remaining etching target layer with a second type of etching gas having a composition different from the first type, following the first etching step. 2. The etching method according to claim 1, wherein the second type of gas includes a gas containing chlorine and a nitrogen gas. 3. The gas containing chlorine is Cl ₂ , HCl,
_3. The etching method according to claim 2, wherein the etching method is at least one of BCl ₃ , SiCl ₄ , S ₂ Cl ₄ and CCl ₄ . 4. The etching method according to claim 1, wherein the first type of gas includes a gas containing chlorine and an oxygen gas. 5. The method according to claim 1, wherein the underlayer has a silicon layer formed on an insulating layer as an uppermost layer, and after the second etching step, further includes a third etching step of etching the silicon layer with a first type of gas. The etching method according to claim 1, wherein the etching method comprises: 6. The etching method according to claim 5, wherein the third etching step is performed after the etching of the etching target layer in the narrow space portion is completed. 7. The etching method according to claim 5, wherein the third etching step is performed after the insulating layer is exposed in the wide space.