JPH11110297A - Built-in memory type 1 chip computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a 1 chip computer that incorporates a ferroelectric memory having the upper limit in the number of write-in times as a nonvolatile memory and at the same time is applicable even to a device requiring a long-term use and high reliability. SOLUTION: A ferroelectric memory 2 comprises a plurality of banks 2a, 2b,... and when the number of write-in times of the bank 2a almost exceeds a service life of the ferroelectrics, other banks 2b, 2c,... are switched to and a use of a nonvolatile memory is continued. Means 8 and 14 for stopping a clock are provided and stand-by condition that does not consume a power is realized. A configuration memory of a field programmable gate array(FPGA) 370 is added to by a parity bit and an error signal 16 is emitted to outside in detecting an error. The ferroelectric memory can be used for a 1 chip computer that has many memory accesses or is used for long term. Power consumption becomes extremely small under stand-by condition. A bit error is detected and safety can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip computer with a built-in memory in which a large-scale logic operation unit such as a processor and a memory are mounted, and more particularly to a ferroelectric memory having a maximum number of write times as a nonvolatile memory. And means for extending the substantial life of a one-chip computer using the same.

[0002]

2. Description of the Related Art With the development of microelectronics technology, large-scale logic such as a processor and large-capacity memory such as a DRAM can be integrated on one silicon substrate. These semiconductor elements are called a logic embedded LSI.
No. 547, “High-performance image memory LSI and a display device using the same”.

[0003] In these conventional examples, high performance is aimed at by a logic embedding technique, but volatile DRA is used.
When the power supply is cut off, the data is lost and the data must be backed up by many external circuits. Therefore, the one-chip computer is incorporated in a wider field, for example, a small machine. It becomes an obstacle when expanding to applications and information home appliances.

On the other hand, FRAM (Ferro-electric Random A)
ccess Memory), a ferroelectric memory, is being put to practical use. A ferroelectric memory has excellent characteristics such as non-volatility and low power consumption operation while having an access speed as high as that of a DRAM, and is called an ideal memory. In a logic embedded LSI, D
If a ferroelectric memory is mounted in place of the RAM, the application range of the one-chip computer can be expanded.

[0005]

However, the number of times of rewriting of a ferroelectric memory is limited to about 10 12 times to 14 times due to a limitation on the material characteristics of the ferroelectric memory. Therefore, in a device having a short rewriting cycle or a usage period of 10 years or more, such as industrial equipment, the number of rewriting times exceeds the limit value, and the ferroelectric memory cannot be used. For example, in a program that rewrites data every 100 μsec, 10 rewrites of 4 times per second occur,
It will exceed the upper limit of the number of rewrites in about 3.2 years.

[0006] In a small-sized embedded application, it is necessary to reduce the power consumption during standby to zero. In this regard, the ferroelectric memory is superior. However, in general, most of the power consumption of a one-chip computer is consumed in an internal clock circuit portion, and the power consumption cannot be reduced to zero unless the clock is completely stopped.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory-incorporated one-chip computer having means for relaxing the limit on the number of times of rewriting of a ferroelectric memory and substantially extending a substantial life.

Another object of the present invention is to provide a memory-incorporated one-chip computer having means suitable for greatly reducing the power consumption of a processor using a nonvolatile ferroelectric memory. .

Another object of the present invention is to provide a new processor architecture using a nonvolatile ferroelectric memory.

[0010]

According to the present invention, in order to achieve the above object, there is an upper limit on the number of times of writing, and an instruction and / or
Or a memory-integrated one-chip in which a non-volatile memory for storing data, a processor for reading and executing instructions from the non-volatile memory, and input / output means for performing input / output operations in accordance with instructions from the processor are integrated on a single chip In the computer, the non-volatile memory is divided into a plurality of memory banks, and the one-chip computer with a built-in memory includes a memory use measuring unit for counting a frequency of use of the non-volatile memory by the processor, and an address output from the processor. A memory-integrated one-chip computer having a memory control unit for transmitting data to any one of a plurality of memory banks is proposed.

The memory usage measuring means has an interrupt generating means for counting the number of memory accesses output from the processor and generating an interrupt for the processor when the number of memory accesses exceeds a specified number. Further, the memory use measuring means may include an interrupt generating means for counting the cumulative operation time of the processor and generating an interrupt to the processor when the cumulative time exceeds the designated time. Further, means for counting the number of times of memory access and means for counting the cumulative operation time of the processor may be provided in parallel. The memory use measuring means may have a nonvolatile counter register.

In any of the above-mentioned one-chip computers with a built-in memory, the memory control means has a non-volatile transmission table for changing an address transmission destination in accordance with an instruction from the processor. The memory control means may include means for changing the address transmission destination in accordance with an instruction from outside the chip.

According to another aspect of the present invention, there is provided a nonvolatile memory for storing instructions and / or data with an upper limit on the number of times of writing, and a processor for reading and executing instructions from the nonvolatile memory. In a one-chip computer with a built-in memory in which input / output means for performing input / output operations in accordance with instructions from a processor are integrated on one chip, all clocks or partial clocks in the chip are stopped by instructions from the processor, or A memory-incorporated one-chip computer having clock control means for changing to a low-frequency clock is proposed.

According to another aspect of the present invention, in a field programmable gate array in which a configuration memory for storing configuration data is composed of nonvolatile memory cells, the configuration data in the configuration memory is changed. Bit error detection means for detecting that
A field programmable gate array having bit error holding means for holding the detection result of the bit error detection means is proposed.

In the field programmable gate array, the bit error detecting means is set so that the value of the parity calculating means for obtaining an exclusive OR of all the bits of the configuration memory and the value of the parity calculating means are constant. Parity bit holding means. The bit error holding means may include an external pin for sending the held data to the outside.

In order to achieve the above object, the present invention provides a non-volatile memory for storing instructions and / or data with an upper limit on the number of times of writing, a processor for reading and executing instructions from the non-volatile memory, and an instruction for the processor. In a one-chip computer with a built-in memory, an input / output means for performing an input / output operation in accordance with the above and a field programmable gate array in which a configuration memory for storing configuration data is constituted by nonvolatile memory cells are integrated on a single chip. Memory is divided into a plurality of memory banks, and a one-chip computer with a built-in memory includes a memory usage measuring unit for counting the frequency of use of the memory by the processor, and an address output from the processor to one of the plurality of memory banks. Memory control means for transmitting Proposes the bit error detecting means for detecting that the configuration data in the configuration memory is changed, the memory-based one-chip computer having a bit error holding means for holding a detection result of the bit error detection unit.

According to another aspect of the present invention, there is provided a non-volatile memory for storing instructions and / or data with an upper limit on the number of times of writing, a processor for reading and executing instructions from the non-volatile memory, In a one-chip computer in which input / output means for performing input / output operations in accordance with the instruction and a field programmable gate array in which configuration memory for storing configuration data is formed of volatile memory cells are integrated on one chip, Means for transferring the configuration data stored in the non-volatile memory to the volatile configuration memory according to a reset signal of the processor or an instruction of the processor, and a bit error detecting that the configuration data has changed. Means out, we propose a memory-based one-chip computer having a bit error holding means for holding a detection result of the bit error detection unit.

In order to achieve the above object, the present invention further provides a nonvolatile memory for storing instructions and / or data with an upper limit on the number of times of writing, a processor for reading and executing instructions from the nonvolatile memory, In a one-chip computer in which input / output means for performing input / output operations in accordance with an instruction are integrated on a single chip, a nonvolatile memory is divided into a plurality of memory banks, and the frequency of use of one memory bank in the nonvolatile memory Memory use measuring means for counting the number of times of use, and memory control means for changing access to the one memory bank to access to another memory bank in the memory according to the output of the memory use measurement means We propose a one-chip computer.

According to the present invention, a non-volatile memory for storing instructions or data and a processor for reading and executing instructions from the non-volatile memory are integrated on one chip. The nonvolatile memory is composed of a plurality of memory banks. When the number of times of writing in one memory bank is about to exceed the life of the ferroelectric material constituting the nonvolatile memory, the memory is switched to another memory bank and the nonvolatile memory is replaced with another memory bank. Continue using. It has a memory usage measuring means for counting the frequency of use of the memory by the processor to check the number of times of writing to the non-volatile memory, and a memory control means for transmitting an address output from the processor to a new memory bank. With this memory control means, there is no need to change the program.

[0020] The memory bank switching timing is notified to the program by the memory usage measuring means generating an interrupt which generates an interrupt under predetermined conditions. In addition, by enabling the designation of the memory bank switching from outside the chip, the yield of the one-chip computer with a built-in memory can be increased without using the defective memory bank.

Therefore, even if a ferroelectric memory having an upper limit in the number of times of writing is used as a nonvolatile memory, a computer system that can be used for a substantially long period can be constructed. Further, by utilizing the non-volatility of the ferroelectric memory, a computer with extremely low power consumption during standby can be constructed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a one-chip computer with a built-in memory according to the present invention will be described with reference to FIGS.

FIG. 1 is a functional block diagram showing the configuration of one embodiment of a one-chip computer according to the present invention. FIG.
In the figure, the surrounding dotted lines indicate that the CPU 1, memory 2, memory control means 3, timer 4, DMA controller 5, address decoder 7, flip-flop 8, bus interface unit 10, gate 14, FPGA 370, etc. are integrated on one chip. Is expressed.

The CPU 1 may be, for example, “Hitachi, Ltd., S
H7020, SH7021 Hardware Manual ”. The memory 2 includes a plurality of memory banks 2a, 2b,
Are divided into 2c, 2d,..., And each memory bank 2a, 2b, 2c, 2d,... Is composed of a ferroelectric memory macro cell or another rewritable nonvolatile memory macro cell. At the time of writing to the memory, the memory control means 3 transfers the memory address or the write data on the memory bus 11 to one of the memory banks 2a, 2b, 2c, 2 via the signal lines 25a, 25b, 25c, 25d.
, and at the time of memory reading, the read data from any of the memory banks 2a, 2b, 2c, 2d is transmitted to the memory bus 11. The memory control means 3 has a built-in counter for measuring the number of times of memory access, and generates an interrupt to the CPU 1 via the signal line 17 when the number of times of memory access exceeds a specified number.

The accumulative timer 4 is under the control of the CPU 1. When the accumulated operation time exceeds the upper limit value of the counter set by the CPU 1, the CP 4
An interrupt is generated in U1. When a clock with a calendar function called a real-time clock is used as the accumulative timer 4, the CPU 1 periodically polls the time and, when a predetermined date and time is exceeded, employs a method of activating an interrupt process by a program. Can also.

A DMA (direct memory access) controller 5 executes data transfer between the memory 2 and a device connected to the outside of the one-chip computer shown in FIG.

When the address of the flip-flop 8 is sent from the CPU 1, the address decoder 7 detects this address and sets the flip-flop 8.

The bus interface unit 10 connects the external address / data signal 35 to the memory bus 11. It is the same as a well-known device that a serial signal line (not shown) may be included in addition to the bus signal.

The AND gate 14 outputs the reset signal 12
And an external clock signal 13 to calculate the logical product. The signal line 141 from the AND gate 14 is
It supplies an internal clock signal distributed to each element in the one-chip computer. That is, the AND gate 14 is
When the reset signal 12 is asserted and the flip-flop 8 is cleared, the external clock signal 13 is distributed as an internal clock signal of a one-chip computer. At this time, the clock skew in the chip can be reduced by using a PLL (Phase Locked Loop) circuit not shown.

The user logic unit 370 is described in, for example,
As described in Japanese Patent No. 51356, a field programmable gate array (FPGA) realizes a function that cannot be achieved by only a basic part of a one-chip computer. The signal line 15 is an input / output signal line of the user logic unit, and the error signal line 16 is an error signal line that is asserted when a failure occurs in the user logic 370.

FIG. 2 is a block diagram showing an example of the internal configuration of the memory control means 3 of FIG. Address decoder 2
2 decodes the address output from the CPU 1,
When the registers 23a, 23b, 23c and 23d are designated, the data provided via the internal bus 11 is set in the register 23. Registers 23a, 23b, 23
.., 23d... are address selection control registers. When the registers are set, the addresses of the internal bus 11 are transferred to the memory banks 2a, 2b, 2c, 2d,... The pads 26a, 26b, 26c, 26d are pads for presetting a memory bank that can be used during chip manufacture. When the pad 26 is at the H level, the selection of the memory banks 2a, 2b, 2c, 2d,... Can be controlled by the address selection control registers 23a, 23b, 23c, 23d,. , The memory banks 2a, 2b, 2c, 2d,... The pad 26 may be processed by wire bonding in the chip package, or may be connected to an external pin and controlled from outside the chip.

When detecting the memory access, the address decoder 20 increments a counter 21 for counting the number of memory accesses. When the count overflows, the counter 21 outputs a signal to the CPU 21 via the signal line 17.
An interrupt is generated at 1. Although a means for setting the count upper limit value of the counter 21 is not shown, it is known that it can be easily realized by allocating the counter to a memory space.

FIG. 3 shows the user logic unit, FP, of FIG.
FIG. 3 is a block diagram illustrating an example of an internal configuration of a GA 370.
In the user logic unit 370. A logic block 30, a configuration memory 31, and a connection matrix 32
And these are collectively referred to as logical segments. The signal lines 33 and 34 are an aggregate of signal line channels previously laid inside the user logic unit 370. The data stored in the configuration memory 31 determines what kind of logical operation is to be performed in the logic block 30 and which signal line channel is to be used as the input / output of the logic block 30 via a connection matrix. The signal line 35 is a line of an exclusive OR signal of each bit in the configuration memory 31, and is output one by one from each logical segment.

FIG. 4 is a block diagram showing an example of the internal configuration of the configuration memory 31 of FIG. Each bit 411, 4 of the configuration memory 31
12,... 41n are nonvolatile ferroelectric memory cells or EEPROM type cells or static RAMs
Consists of cells. In the case of a static RAM cell, configuration data is set from the memory 2 before the operation of the user logic unit 370 starts. When the outputs of the respective bits of the memory are serially connected by the exclusive OR gates 422,.
An exclusive OR of all bits in the configuration memory 31 can be obtained.

Returning to FIG. 3, each exclusive OR gate 36
Is input to the exclusive OR gate 37. The parity bit 38 is a parity bit that is set so that the output of the exclusive OR gate 37 is electrically low. Like the configuration memory 31, the parity bit 38 is formed of a nonvolatile ferroelectric memory cell, an EEPROM type cell, or a static RAM cell. In the case of a static RAM cell, the parity data is set from the memory 2 before the operation of the user logic unit 370 starts. Flip-flop 3
9 is a set / reset type flip-flop.
If the contents of the configuration memory 31 change during normal operation, the output of the exclusive OR gate 37 goes high, the flip-flop 39 is set, and an error signal is output to the outside of the one-chip computer via the signal line 16. Outbreak is reported. In this embodiment, a parity bit is used to detect a one-bit error in the configuration memory 31. However, it is easy to extend the configuration to use a code capable of detecting a multi-bit error.

Next, main operations of the one-chip computer will be described.

(1) Programming operation The memory bank 2 is set in advance by an external memory writing means.
The same program is written in a, 2b, 2c, 2d. Alternatively, data is written only to the memory bank used after the reset operation described below. During the following memory bank switching operation, the memory contents may be copied to a new memory bank.

(2) Reset Operation FIG. 5 is a flowchart showing a procedure of the reset operation. When a reset command is given from outside, the address selection control registers 23a, 23
Since b, 23c, 23d,... are all cleared, the memory bank 2a is selected, and the reset exception program of the memory bank 2a is executed. The reset exception program first reads the reset history data held in the memory bank 2a, and determines whether or not it is the first reset (51). In the case of the first reset, an initial startup process is executed (52). Otherwise, after restoring the in-processor registers and other in-controller registers saved in the memory bank 2a, the program jumps to the address indicated by the program counter also saved in the memory bank 2a, and returns immediately before the standby state. (53).

(3) Normal Operation In the normal operation state, the counter 21 is incremented every time the CPU 1 accesses the memory bank 2a.
When the count of the counter 21 overflows, the interrupt signal 17 is asserted. By the accumulation type timer 4,
The interrupt signal 18 may be asserted when the usage period exceeds the upper limit. Also, both can be provided side by side.

(4) Switching Operation of Memory Banks 2a, 2b, 2c,... During normal operation, when the interrupt signal 17 or 18 is asserted, the data in the currently used memory bank, for example, the memory bank 2a, is programmed. Is copied to a new memory bank, for example, the memory bank 2b. Then, a new memory bank 2b is set in the address selection registers 23a, 23b, 23c, 23d,.

(5) Operation of Standby State and Restart When the one-chip computer enters an input wait state or an event wait state for a certain period of time or more, the flip-flop 8 is set by a program and the internal clock of the one-chip computer is stopped. And make a transition to a standby state, thereby reducing power consumption. Prior to the transition to the standby state, the program saves the data in the registers of the CPU 1 and other controllers to the currently used memory bank, for example, the memory bank 2a, and also outputs a code indicating that the clock is stopped in the standby state. Memory bank 2 currently in use
Stored in a.

Further, the bus interface unit 10
By sending a power-off command 35 to an external circuit (not shown) of the one-chip computer via the CPU, power consumption can be completely reduced to zero. When a new input or event occurs, the reset signal 12 is asserted by an external circuit of the one-chip computer (not shown), and restarted according to the procedure (1).

(6) Operation at the time of an error in the user logic 370 The configuration memory 3 of the user logic unit 370
If an error such as bit inversion occurs at 0, the user logic unit 370 operates completely differently, and causes a serious obstacle to the control system. According to this embodiment, the parity bit 38 is set so that the parity of the entire configuration memory 30 is odd.
When one bit of the configuration memory 30 is inverted, the output of the exclusive OR 37 becomes high level, and the flip-flop 39 is set. By connecting the external output 16 to an external circuit of a one-chip computer (not shown), the control system is stopped to ensure safety, reset, eliminate errors,
The whole can be restarted.

[0044]

According to the present invention, it is possible to obtain a memory-incorporated one-chip computer in which a ferroelectric memory having an upper limit in the number of times of writing can be used for an application that frequently accesses a memory or an application of a controller that is used for a long time.

Further, it is possible to realize an energy-saving control system that consumes very little power in the standby state.

Further, it is possible to detect a bit error during the operation of the configuration memory of the field programmable gate array, and it is possible to enhance the security of the control system.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration of an embodiment of a one-chip computer according to the present invention.

FIG. 2 is a block diagram illustrating an example of an internal configuration of a memory control unit in FIG. 1;

FIG. 3 is a block diagram illustrating an example of an internal configuration of a user logic unit, that is, an FPGA of FIG. 1;

FIG. 4 is a block diagram illustrating an example of an internal configuration of the configuration memory of FIG. 3;

FIG. 5 is a flowchart showing a processing procedure of a reset operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Ferroelectric memory 3 Memory control means 4 Timer 5 DMA controller 7 Address decoder 8 Flip-flop 10 Bus interface unit 11 Internal bus 12 Reset pin 13 External clock 14 Logical product gate 15 External input / output pin 16 Error signal line 17 Count overflow interrupt signal line 18 Cumulative time elapse interrupt signal line 20 Address decoder 21 Counter 22 Address decoder 23 Address selection register 24 AND gate 25 Signal line 30 Logic block 31 Configuration memory 32 Connection matrix table 33 Signal line 34 Signal line 35 Signal Line 36 exclusive-OR gate 37 exclusive-OR gate 38 parity bit 39 flip-flop 41 memory bit 42 exclusive-OR gate 70 FPGA

Claims (13)

[Claims] 1. An instruction and / or an upper limit for the number of times of writing.
Or a non-volatile memory for storing data, a processor for reading and executing instructions from the non-volatile memory,
In a one-chip computer with a built-in memory, an input / output unit that performs an input / output operation in accordance with an instruction of the processor is integrated on one chip, wherein the nonvolatile memory is divided into a plurality of memory banks, A chip computer comprising: a memory usage measuring unit that counts the frequency of use of the non-volatile memory by the processor; and a memory control unit that transmits an address output from the processor to one of the plurality of memory banks. A one-chip computer with a built-in memory. 2. The one-chip computer with a built-in memory according to claim 1, wherein the memory use measuring unit counts the number of memory accesses output from the processor, and the number of memory accesses exceeds a designated number. A one-chip computer with a built-in memory, further comprising an interrupt generating means for generating an interrupt to the processor. 3. The one-chip computer with a built-in memory according to claim 1, wherein said memory use measuring means counts an accumulated operation time of said processor, and said accumulated time exceeds a designated time. A one-chip computer with a built-in memory, characterized by having an interrupt generating means for generating an interrupt to the processor when the processor is activated. 4. The one-chip computer with a built-in memory according to claim 2, wherein said memory use measuring means has a nonvolatile counter register. 5. The non-volatile transmission device according to claim 1, wherein said memory control means changes an address transmission destination in accordance with an instruction of said processor. A one-chip computer with a built-in memory, comprising a table. 6. The one-chip computer with a built-in memory according to claim 1, wherein said memory control means includes means for changing an address transmission destination in response to an instruction from outside the chip. A one-chip computer with a built-in memory. 7. An instruction and / or an upper limit on the number of times of writing.
Or a non-volatile memory for storing data, a processor for reading and executing instructions from the non-volatile memory,
In a one-chip computer with a built-in memory, in which an input / output means for performing an input / output operation in accordance with an instruction from the processor is integrated on a single chip, all clocks or partial clocks in the chip are stopped according to an instruction from the processor. A one-chip computer with a built-in memory, comprising clock control means for causing the clock to be changed to a low-frequency clock. 8. A field-programmable gate array in which a configuration memory for storing configuration data is composed of nonvolatile memory cells, wherein a bit error detection means for detecting a change in configuration data in the configuration memory; A bit error holding unit for holding a detection result of the bit error detection unit. 9. The field programmable gate array according to claim 8, wherein said bit error detecting means calculates an exclusive OR of all bits of said configuration memory, and a value of said parity calculating means. And a parity bit holding means that is set so as to have a constant value. 10. The field programmable gate array according to claim 9, wherein said bit error holding means has an external pin for sending held data to the outside. 11. A non-volatile memory that has an upper limit on the number of times of writing and stores instructions and / or data, a processor that reads and executes instructions from the non-volatile memory, and performs input / output operations in accordance with instructions from the processor. In a memory-integrated one-chip computer in which input / output means and a field programmable gate array in which configuration memory for storing configuration data is composed of nonvolatile memory cells are integrated on one chip, the nonvolatile memory includes a plurality of memories. A one-chip computer with a built-in memory, wherein the memory-incorporated one-chip computer counts the frequency of use of the memory by the processor; and a memory for transmitting an address output from the processor to one of the plurality of memory banks. Control means and front A one-chip computer with a built-in memory, comprising: a bit error detecting means for detecting a change in configuration data in a configuration memory; and a bit error holding means for holding a detection result of the bit error detecting means. . 12. A non-volatile memory for storing instructions and / or data with an upper limit on the number of times of writing, a processor for reading and executing instructions from the non-volatile memory, and performing input / output operations according to instructions from the processor. In a one-chip computer in which an input / output means and a field programmable gate array in which a configuration memory for storing configuration data is formed of volatile memory cells are integrated on a single chip, the nonvolatile memory is operated in accordance with an external reset signal or a processor instruction. Configuration means for transferring configuration data stored in volatile memory to the volatile configuration memory; bit error detection means for detecting that the configuration data has changed; Memory-based one-chip computer, characterized in that it comprises a bit error holding means for holding a detection result of the preparative error detecting means. 13. A nonvolatile memory for storing instructions and / or data with an upper limit on the number of times of writing, a processor for reading and executing instructions from said nonvolatile memory,
In a one-chip computer in which an input / output unit that performs an input / output operation in accordance with an instruction of the processor is integrated on one chip, the nonvolatile memory is divided into a plurality of memory banks, and one of the nonvolatile memories Memory use measuring means for counting the frequency of use of a memory bank, and memory control means for changing access to the one memory bank to access to another memory bank in the memory in accordance with an output of the memory use measuring means A one-chip computer with a built-in memory, comprising: