JPH11110066A - Clock control method for lsi, lsi, and hybrid lsi system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up inter-LSI data transfer by making the delay from clock input to data output which is viewed from outside an LSI appear to be small. SOLUTION: A PLL is provided in an LSI 1 and an external input clock is supplied to the reference input of the PLL, whose output is inputted to a clock distribution system; and the outputs of the clock distribution system are used as input clocks to a flip-flop(FF) group and one of the outputs of the clock distribution system is put back to the feedback input of the PLL through a delay gate. The delay quantity of a delay gate is equalized to the sum (LSI penetration delay quantity) of the delay quantity of a clock input buffer, the delay quantity from the clock input to the data output of the FFs, and the delay quantity of a data output buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock for realizing high-speed data transfer between LSIs of all devices that process data using a synchronous logic LSI, such as a computer, a communication device, and a household appliance. Related to control technology.

[0002]

2. Description of the Related Art In a synchronous logic LSI, between LSIs and L
A logic design method of transferring data in SI in synchronization with a clock is adopted. A clock input terminal of all flip-flops (FF) in the synchronous logic LSI has one type of clock or a phase synchronized with each other and / or
Alternatively, a plurality of types of clocks having different periods are supplied.
When calling each clock of multiple types of clocks distinctively,
Called the clock phase.

FIG. 6 shows an example of a general internal configuration of an LSI created by synchronous logic. 11000 to 1100n are
This is a group of FFs immediately before the output data 1501 to 15n1, and the data 1501 to 15n1 are output to the outside of the LSI 1 via one-stage output buffers 150 to 15n. 13000
To 1300n are FF groups immediately after the input data 1400 to 14n0, and data input from outside the LSI 1 receives the FF group 130 via one-stage input buffers 140 to 14n.
Latched to 00-1300n. 12000-120
0n is an FF group for exchanging data inside the LSI 1. The logic in the LSI 1 is FF group 11000-1
100n, 12000-1200n and 13000-1
The output data of 300n is passed through the combinational logic unit 10 and
It is performed in the form of returning to the groups 11000 to 1100n and 12000 to 1200n. Reference numeral 16 denotes a clock unit which generates various clocks by inputting a clock 170 from outside the LSI 1 through a single-stage clock input buffer 17, and generates FF groups 11000 to 1100 inside the LSI.
n, 12000-1200n and 13000-1300
n.

FIG. 7 shows an example of a method of distributing a clock signal supplied to each FF of a conventional synchronous logic LSI of this type. Synchronous logic employs a method of distributing clocks in a tree shape such that the gate type, the number of gate stages, and the number of loads are equal for all FFs to which one phase clock is supplied. In FIG. 7, reference numeral 160 denotes a frequency dividing and multi-phase clock generation circuit, which converts clock phases 16001 and 1601 from an input clock 171 supplied from outside the LSI 1 via the input buffer 17.
011 is created. Reference numerals 1610 and 1611 denote clock distribution systems (clock distribution circuits),
6001 and 16011 are distributed to many clock signals with the same number of stages and the same number of loads. 1800 to 1803 are FF
And the clock distribution system 161 of the clock phase 16001
One output clock signal of 0 enters the clock input terminal T. 181 to 187 are FFs 1800 to 180, respectively.
A group of FFs equivalent to 3 and similarly supplied with another output clock signal of the clock distribution system 1610. 19
180 to 1903 are supplied with one output clock of the clock distribution system 1611 of the clock phase 16011 180
FFs 191 to 197 corresponding to 0 to 1803 are a group of FFs corresponding to 181 to 187 to which another output clock signal of the clock distribution system 1611 is input. In addition,
The FFs 1800 to 1803, 1900 to 1903, and a group of FFs 181 to 187 and 191 to 197 correspond to the FFs in FIG.
11000 to 1100n, 12000 to 1200n, 1
This corresponds to any one of 3000 to 1300n.

FIG. 8 shows a simplified configuration of a conventional clock control method for a synchronous logic LSI. As shown in FIG.
Conventionally, in an LSI employing a synchronous logic system, a clock input from a clock input terminal 170 of the LSI 1 is passed through a clock input buffer 17 and a clock distribution system 161.
The data is supplied to each FF, and the output data 1501 is
From 1000, the data was output to the outside of the LSI 1 through the output buffer 150.

FIG. 9 shows the internal configuration of each LSI when data is transferred between LSIs by the conventional clock control method.
FIG. 10 shows a time chart of data transfer between LSIs.
In FIG. 9, LSI1 is a data sending side and LSI2 is a data receiving side.

In the conventional clock control method, LSI1, L1,
When performing data transfer between SI2, the data sending side LSI
FF11000 and the data receiving side LSI2 just before the output of 1
Clock 16 supplied to the FF 23000 immediately after the input of
1000 and 261000 are supplied from the external clock generation unit 3 via the clock input buffers 17 and 27 of the respective LSIs 1 and 2 and the clock distribution systems 161 and 261. Here, even when the clock input buffers 17 and 27 and the clock distribution systems 161 and 261 have the same configuration between the data sending side LSI 1 and the receiving side LSI 2, the manufacturing process and the operating Since the temperature and the applied voltage during operation are different, the clock edges of the clocks 161000 and 261000 supplied to the FF 11000 immediately before the output of the data sending LSI 1 and the FF 23000 immediately after the input of the data receiving LSI 2 shift. For this reason, as shown in FIG. 10, the setup margin and the hold margin when the data is latched by the receiving LSI 2 are reduced, and the data transfer cannot be speeded up. In FIG. 10, 2401 is
FF1100 immediately before data output of the data sending side LSI1
FF23000 immediately after data input to the data receiving LSI 2 with reference to an input clock 161000 of 0
Is the input data.

Conventionally, a clock 161000 supplied to the FF 11000 immediately before the output of the data sending side LSI 1 and the FF 23000 immediately after the input of the data receiving side LSI 2,
In order to match the clock edges of 261000, FIG.
There is a clock advance control method using a phase locked loop circuit (PLL) shown in FIG. The PLL 1 adjusts the phase of the output clock 1621 so that the phase of the input clock (reference input) 171 and the phase of the feedback input 1631 are aligned.
62, one of the output clocks (161 fb) of the clock distribution system 161 is transferred to the clock input buffer 1
7 is returned to the feedback 1631 of the PLL 162 via the delay gate 163 equal to the delay amount of the FF 11000 in the LSI 1 so that the clock input 161 of the FF 11000 in the LSI 1
The clock edge at 000 is matched with the clock edge at the clock input 170 of the LSI 1 so that the clock edges between the FFs in the two LSIs that perform data transfer are matched.

FIG. 12 shows a time chart of the clock advance control method using the conventional PLL shown in FIG. PL
L162 is the input clock 171 and the feedback input 1
The output clock 16 is adjusted so that the clock edges of 631 are aligned.
21, the output clock 16 of the PLL 162 is adjusted.
21 is a clock distribution system 161 and a delay gate 1
63 and the feedback input 163 of the PLL 162
1, the input clock 17 of the PLL 162
1, the clock distribution system 161 and the delay gate 1
The clock advanced by the amount of delay of 63 is PLL162.
Output from Input clock 171 of PLL 162
Is delayed by the delay of the clock input buffer 17 from the clock input 170 of the LSI 1, and by using a delay gate having a delay amount equal to the delay amount of the clock input buffer 17 as the delay gate 163, the Output clock 1621
Is earlier than the clock input 170 of the LSI 1 by the delay amount of the clock distribution system 161. The clocks are supplied to all the FFs in the LSI 1 through the clock distribution system 161. The clock distribution system 161 includes the clock inputs 161000 to 16100m of all the FFs and the signal 161fb before the feedback signal delay gate 163.
, The clock is distributed so that the gate type, the number of gate stages, and the number of loads are equal, so that all FFs in the LSI 1
The clock edges of the input clocks 161000 to 16100 m are aligned with the clock edges of the input clock 170 of the LSI.

[0010]

The biggest problem of the above-mentioned conventional clock advance control method using the PLL is that the LSI
From the clock input of the LSI when observed from outside,
That is, no consideration is given to variations in delay until data is output outside the SI. The delay from the clock input to the data output is the sum of the delays of the FF 11000 and the output buffer 150 as shown in FIGS. Since this delay is caused by a gate delay in the LSI, generally, the delay varies from a standard value due to a process at the time of manufacturing the LSI, a temperature at the time of operation, and an applied voltage at the time of operation. The amount of this variation is
Depending on the manufacturing process and usage conditions,
As an example, it is about 0.5 to 2 times the standard value. Due to this delay variation, when data is transferred between LSIs, the period during which data is guaranteed is narrowed. In extreme cases, if the cycle time of data transfer is reduced, the period during which data is guaranteed is lost. I will.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the delay from the clock input of an LSI to the data output of the LSI, which is observed from outside the LSI, in view of the above-described problem of the clock advance control using a PLL. Is to further increase the speed.

[0012]

According to the present invention, a delay amount of a delay gate to be put in a feedback path of a PLL used for a clock advance control in an LSI is not a delay amount of a clock input buffer but a delay amount of a clock input buffer. By setting the sum of the delay amount from the clock input to the data output of the FF and the delay amount of the data output buffer, the clock edge of the input clock of the FF is advanced so that the time when the signal is observed from outside the LSI can be obtained. This is such that there is no delay from the clock input to the data output of the LSI.

Here, the sum of the delay amount of the clock input buffer, the delay amount from the clock input to the data output of the output FF, and the delay amount of the data output buffer is determined by directly outputting the output of the clock input buffer in the LSI.
This is equal to the delay from the clock input of the LSI to the data output of the LSI when the data is output from the data output of the FF to the outside of the LSI through the output buffer. Called quantity.

In addition, although the delay of the data input buffer varies when transferring data between LSIs, the present invention uses a delay gate formed in the same LSI as the clock of the FF receiving data in the LSI, and the clock of the clock input of the LSI. By delaying the clock edge of the clock input of the FF from the edge by the delay of the data input buffer, variations in the delay of the data input buffer during data transfer between LSIs are absorbed.

The delay amount of the delay gate inserted into the feedback path of the PLL used for the clock advance control in the LSI is larger than the delay amount of the clock input buffer, and is determined from the delay amount of the clock input buffer and the clock input of the FF. When the delay amount until the data output and the delay amount of the data output buffer are set to be smaller than a part of the delay of the data output and the observation is made from outside the LSI, the delay in the LSI becomes smaller. As described above, that is, L related to delay
You may make it seem that the performance of SI improved.

[0016]

FIG. 1 shows an example of the configuration of an LSI clock control method using a PLL according to the present invention. this is,
As in FIG. 11, the FF 11 immediately before the data output of the LSI 1 is output.
FIG. 9 is a diagram showing a method of supplying a clock to the 000.

First, the operation of the PLL 162 will be described with reference to FIGS.
This will be described. The PLL 162 includes a phase comparator 162
2. Using the low-pass filter 1623 and the voltage-controlled variable frequency oscillator 1624 (FIG. 2), the output clock 1 is adjusted so that the phases of the input clock (reference input) 171 and the feedback clock (feedback input) 1631 match.
621 is changed. When the phase of the feedback clock 1631 is earlier than the phase of the input clock 171, the phase comparator 1622 outputs
25, when the phase of the input clock 171 matches the phase of the feedback clock 1631, an intermediate potential VM is output to the phase difference output 1625, and the potential of the feedback clock 1631 is higher than that of the input clock 171. When the phase is later, a higher potential VH is output to the phase difference output 1625 (FIG. 3). The low-pass filter 1623 removes high-frequency components of the phase difference output 1625 so that the PLL 162 does not react to the noise when the input clock 171 has noise. When the input potential 1626 is at the low potential VL, the low frequency FL
And outputs an intermediate frequency FM when the input potential 1626 is the intermediate potential VM, and outputs a high frequency FH when the input potential 1626 is the high potential VH (FIG. 4). By returning the output clock 1621 of the voltage controlled variable frequency oscillator 1624 to the feedback clock 1631, the PLL 162 operates to reduce the frequency of the output clock 1621 when the phase of the feedback clock 1631 is earlier than the phase of the input clock 171. When the phase of the feedback clock 1631 lags behind the phase of the input clock 171, it works to increase the frequency of the output clock 1621, and stabilizes when the phase of the input clock 171 matches the phase of the feedback clock 1631.

FIG. 1 is basically the same as FIG. 11, except that the delay amount of the delay gate (delay element) 163 is changed from the delay amount of the clock input buffer 17 and the clock input of the FF (logic element) 11000. The sum of the delay amount until data output and the delay amount of the data output buffer 150 (LSI penetrating delay amount), or at least larger than the delay amount of the clock input buffer 17 and the delay amount of the clock input buffer 17, FF11000 Is smaller than the sum of the delay amount from the clock input to the data output and the delay amount of the data output buffer 150.

A method for controlling the clock advance using the PLL of the present invention shown in FIG. 1 will be described with reference to the time chart of FIG.

In FIG. 1, an output clock 1621 of the PLL 162 is supplied to a clock distribution system (clock distribution circuit) 16.
1 and the delay gate 163, and the PLL 162
Is returned to the feedback input 1631. PLL162
The PL is adjusted so that the clock edges of the input clock (reference clock) 171 and the feedback input 1631 are aligned.
Since the output clock 1621 of L162 is adjusted, PL
L162 outputs a clock that is earlier than the input clock 171 by the sum of the delay amounts of the clock distribution system 161 and the delay gate 163. The input clock 171 of the PLL 162 lags behind the clock input 170 of the LSI 1 by the delay of the clock input buffer 17. As the delay gate 163, the delay amount of the clock input buffer 17 and the delay from the clock input of the FF 11000 to the data output are output. When a delay gate having a delay amount equal to the sum of the delay amount of the data output buffer 150 and the delay amount of the data output buffer 150 is used, the output clock 1621 of the PLL 162 is more delayed than the clock input 170 of the LSI 1 by the delay amount of the clock distribution system 161 and the FF 110
00 clock input to data output delay amount,
In addition, the delay is advanced by the sum of the delay amounts of the data output buffer 150. The clock is supplied to the FF 11000 in the LSI 1 through the clock distribution system 161, and the clock distribution system 161 supplies the clock input 161000 to all the FFs.
The clock edge of the input clock 161000 of the FF 11000 in the LSI 1 is obtained by distributing the clocks to the 16100 m and the feedback signal 161 fb before the delay gate 163 so that the gate type, the number of gate stages, and the number of loads are equal. The delay is advanced by the sum of the delay amount from the clock input of the FF 11000 to the data output and the delay amount of the data output buffer 150 from the clock edge of the input clock 170 of the LSI 1.
The data output from the LSI 1 is the FF immediately before the data output.
Since the delay from the clock edge of the input clock 161000 of 11000 to the delay time from the clock input of the FF 11000 to the data output and the delay amount of the data output buffer 150 is delayed, the clock input 1 of the LSI 1
When the delay from 70 to the data output is observed from outside the LSI 1, it appears that the data 1501 is output simultaneously with the clock edge of the clock input 170.

Here, the amount of delay of the delay gate 163 is calculated from the clock input 170 of the LSI 1 to the data output 1
Even if the delay up to 501 is not increased until it is completely eliminated (that is, it is larger than the delay amount of the clock input buffer 17, the delay amount of the clock input buffer 17, the delay amount from the clock input to the data output of the FF 11000, and the data output) This is effective in canceling a part of the delay from the clock input 170 of the LSI 1 to the data output 1501. When observed from outside the LSI 1, the delay in the LSI 1 is reduced. like,
That is, it seems that the performance of the LSI 1 with respect to the delay is improved, and it is still effective for high-speed data transfer between the LSIs.

FF 110 immediately before data output in LSI 1
00 input clock 161000 clock edge,
The advance amount of the input clock 170 of the LSI 1 with respect to the clock edge is also determined by the clock input 1610 of the FF 11000.
Since the delay amount from 00 to the data output 1501 of the LSI 1 is also obtained by the delay amount of the gate in the LSI 1, the process at the time of manufacturing the LSI 1, the temperature at the time of operation,
Although it varies from the standard value due to the applied voltage at the time of operation, since it is configured in the same LSI 1, the process at the time of manufacturing the LSI 1, the temperature at the time of operation, and the applied voltage at the time of operation are the same, so that the variation FF110
00 and the change of the delay of the data output buffer 150 are canceled by the change of the advance amount of the clock 161000, and the variation from the clock input to the data output observed from outside the LSI 1 is suppressed to be small.

However, in general, the FF and the data output buffer and the delay gate in the LSI are formed by a process during manufacturing,
Since the method of changing the delay with respect to the temperature at the time of operation and the applied voltage at the time of operation is different, data cannot be completely output at the same time as the clock edge of the input clock of the LSI, and the LSI using the clock control method of the present invention. It is necessary to allow for an uncertain data time even during data transfer between them. Min and Max in FIG. 5 show examples of data uncertain times.

FIG. 13 shows a system (composite LSI) for transferring data between LSIs using the clock control method of the present invention.
2 shows an example of the internal configuration of the system. In FIG. 13, a clock that changes at the same timing between the LSIs is supplied from the clock unit 3 to each of the LSIs 1 and 2. Each LSI
1. The clock units 16 and 26 of the LSI 2 have the configuration described with reference to FIG. 1, and when data is exchanged between the LSIs 1 and 2, the FFs 11000 and 21000 just before the data output buffers 150 and 250 of the LSIs 1 and 2
And FF1 immediately after the data input buffers 140 and 240
3000 and 23000 are latched by clocks synchronized with the clocks 170 and 270 input to the respective LSIs 1 and 2. In FIG. 13, as an example, LSI1 to L
Although only one data line 4 transferred to SI2 and one data line 5 transferred in the opposite direction are shown,
However, it is not limited to this.

The FF immediately before data output of the LSI 1 in FIG.
The method of supplying the clock to 11000 has already been described with reference to FIG. FF immediately before data output of LSI2
The same applies to 21000.

Here, a method of supplying a clock to be supplied to the FF immediately after data input in the LSI 1 will be described with reference to FIGS.
4 and FIG. The same can be said for the clock supplied to the FF immediately after the data input in the LSI 2.

In this embodiment, of the delay in the data transfer between the LSI 1 and the LSI 2, the part depending on the change in the delay of the data sending side LSI is absorbed by the control of the clock system in the data sending side LSI, and the data receiving side LSI. The amount dependent on the change in the delay is absorbed by the control of the clock system in the data receiving LSI, so that the change in the delay
Aim to secure setup margin and hold margin.

The details of the data transfer delay between the LSIs include the delay from the clock input 170, 270 to the data output 1501, 2501 of the data sending side LSI, the signal propagation delay by the wirings 4, 5 between the LSIs, and the data receiving side LSI. Of the data input buffers 240 and 140 of FIG.

Clock input 17 of data sending side LSI
The delay from 0, 270 to the data output 1501, 2501 varies depending on the process at the time of manufacturing LSI1, LSI2, the temperature at the time of operation, and the applied voltage at the time of operation. L
The propagation delay due to the wirings 4 and 5 between the SIs is a normal LS
In data transfer between I, it can be regarded as a constant value that does not depend on the temperature and voltage during operation. The delays of the data input buffers 240 and 140 of the data receiving side LSI are LSI2 and LS
It changes depending on the manufacturing process of I1, the temperature during operation, and the applied voltage during operation.

Therefore, as shown in FIG. 14, the input clocks 13010 to 1301 m of the FFs 13000 to 1300 n immediately after the data input to the LSI 1 are provided with the clock distribution system 1.
The output clocks 13030 to 1303m of the 6100 are output from the clock input of the FFs 11000 to 1100n immediately before data output to the data output, the delay of the data output buffer (150 in FIG. 13), and the delay of the data input buffer (140 in FIG. 13). A clock that passes through delay gates 13020 to 1302 m having a delay amount equal to the sum of the delays is used. F immediately after data input on the LSI 2 side
The same applies to the clock input of F. Generally, since different types of input buffers are used for the data input buffer and the clock input buffer, their delays are different from each other.

In FIG. 14, since the same number of FFs are driven for one branch of the output of the clock distribution system 16100, 0 to n are used for FF numbering, and the output of the clock distribution system is output. Each branch is numbered from 0 to m. For example, when driving four FFs from each branch,
n = 4m.

With the configuration of the clock unit 16 shown in FIG. 14, in the example of FIG.
The clock edge of the input clock 13010 of the F13000 lags behind the clock edge of the input clock 170 of the LSI 1 by the delay amount of the data input buffer 140, which is dependent on the change in the delay of the data receiving LSI (FIG. 15).

An FF for exchanging data within the LSI 1, which is neither immediately after data input to the LSI 1 nor immediately before data output.
Since 12000 to 1200n only exchange data within an LSI, there is generally more room for setup time and hold time for data transfer than when data is transferred across an LSI, and therefore clock timing for data transfer. Conditions are loose. Therefore, LSI1
FF12000-1200n that exchange data within
FF11000 to FF1 just before data output of LSI1
FFs 13000 to 13 immediately after data input from a clock edge of 100n clock input 11010 to 1101 m
A clock which has a clock edge between clock edges 1301 to 1301 m of 00n is input. For example, in the case of FIG. 14, the FFs 12000 to 1200n that exchange data in the LSI 1
A clock having the same timing as the clock input 11010 to 1101m of the FFs 11000 to 1100n immediately before the data output of No. 1 is input.

Next, as another embodiment, the input clock 1301 of the FFs 13000 to 1300n immediately after the data is input.
A configuration example of the clock unit 16 in which the way of giving a delay of 0 to 1301 m is changed will be described with reference to FIG.

In FIG. 16, F in FIG.
FF1 of the delay gates 13020 to 1302m inserted immediately before F13000 to 1300n.
The delay from the input of 1000 clocks to the output of data and the delay of the output buffer 150 are distributed to the clock distribution system 1
Bring before 6101.

In the case of the configuration shown in FIG. 16, the input clock 1301 of the FFs 13000 to 1300n immediately after data is input.
Of the delay amounts put in the range of 0 to 1301 m, the delay amount of the data input buffer 140 is FF13000 to 1301
The delay gates 13020 to 1302m can be omitted if there is a margin in setup time in data transfer between LSIs. When the delay gates 13020 to 1302m are omitted, only one delay inserted for each branch 13030 to 1303m of the clock distribution system needs to be inserted before the distribution system 16101, and the number of delay gates can be reduced. However, two systems of 16100 and 16101 are required. When the reduction in the gate amount due to the reduction of the delay gates 13020 to 1302m is larger than the increase in the gate amount due to the increase in the clock distribution system 16101, the configuration shown in FIG. 16 has a smaller gate amount than the configuration shown in FIG. It is advantageous from. FF13000 to 13 immediately after data input
The greater the number of 00n, the greater the gate reduction effect of the configuration shown in FIG.

In the example shown in FIG. 16, the FFs 12000 to 1200n for exchanging data in the LSI include:
The clock is supplied from the clock distribution system 16101 in which the delay gate 16102 is inserted before the clock distribution system.

Next, a description will be given of a method of configuring a clock system in a case where a plurality of types of clocks, ie, clocks which are synchronized with each other but have different phases and / or periods, are used in an LSI. . In the following, for simplification of the description, a case where the number of clock phases is two will be described.

FIG. 17 shows a multi-phase clock (two-phase clock).
1 shows a first embodiment in the case of using. In this embodiment,
Clock distribution systems 16100, 1 corresponding to the configuration of FIG.
6110 and delay gates 13020 to 1302 m,
13120-1312m, each clock phase 1600, 1
14A, the clock 161fb of one branch after the clock distribution of one clock phase 1601 is shown in FIG.
Through the delay gate 163 having the same delay amount (penetration delay amount) as the delay gate 163
The feedback clock 1631 is returned. PL
L162 controls the clock for clock phase 1601 returning to feedback clock 1631,
Clock division / multiphase clock generation circuit 160 generates each phase clock so that clock edges are aligned with all phase clocks (1600, 1601). Is controlled in the same manner as.

FIG. 18 shows a multi-phase clock (two-phase clock).
A second embodiment in which is used will be described. In this embodiment,
For one clock phase 1600, a clock distribution system 16100 and a delay gate 13020 shown in FIG.
１３０1302 m and another clock phase 160
1, the clock distribution system 1611 shown in FIG.
0, 16111 and delay gates 16112, 131
The clock 161fb of one branch after the clock distribution of the clock phase 1601 in the configuration shown in FIG. 16 has the same delay amount (delay amount for the clock input buffer) as the delay gate 163 in FIG. Through the delay gate 163 to the feedback clock 1631 of the PLL. Also in this example, the fact that the clock is controlled for all phases 1600 and 1601 is explained for the same reason as in the example of FIG.

As in the above two examples, (1) the clock distribution system and the delay gate shown in FIG. 16 are configured for each clock phase, and one phase is returned to the feedback of the PLL. (2) One clock The clock distribution system and delay gate configuration shown in FIG. 16 for one phase, and the clock distribution system and delay gate configuration shown in FIG. 14 for another clock phase, and the configuration shown in FIG. Is also possible to return the clock phase to the PLL feedback clock 1631.

Next, FIG. 19 shows the embodiment shown in FIG.
Clock distribution systems 16110, 16 of clock phase 1601
This is a configuration example in a case where the clock distribution system 16110 in which the delay gate 16112 is not inserted is omitted. If the cycle of the clock phase 1601 is sufficiently longer than the time required for data transfer between the LSIs and data transfer can be performed without performing fine clock control, one clock distribution system 1611 is provided for this clock phase 1601.
1 to all FFs to which the clock of this phase 1601 is supplied.
11100-1110n, 12100-1210n, 1
A clock system design that supplies a clock to 3100 to 1310n can also be adopted. FIG. 19 illustrates this idea.

When the clock division / multiphase clock generation circuit 160 of FIG. 19 generates a clock 1600 having the same cycle as the output 1621 of the PLL 162 and a clock 1601 having a cycle twice as long as the output 1621 of the PLL 162, FIG. 2 shows only the parts of the multi-phase clock generation circuit 160 and the delay gate 16112.
0 and outputs of two phases 1600, 16113
It can be understood that both the delay gates 16000 and 16112 are included.

Here, suppose that the delay gate 1 entering each phase
When the delay amounts of 6000 and 16112 are equal in all phases, the LS of each clock phase differs depending on whether the delay gates 16000 and 16112 of all phases are deleted or not.
The time relationship with respect to the clock input of I remains unchanged.
As shown in FIG.
12 can be deleted. This is because even if all phases are delayed by the same delay amount in the multi-phase clock, the PLL 16
2 by feedback control in the PLL 162
Is advanced by this delay amount, and the delay amounts of all phases are cancelled.

In the case of the embodiment shown in FIG.
The delay amount of 6000 is equal to the delay from the clock input 1621 to the data output 1601 of the FF 16001, and the delay amount of the delay gate 16112 is
Since the delay from the clock input to the data output (11000 in FIG. 13) and the delay of the output buffer (150 in FIG. 13) are equal to each other, the delay of the delay gate 16112 is generally larger and both delay gates are longer. Is removed, the clock phase 16
Although the advance of the clock phase 1600 with respect to 113 decreases, the amount of advance of the clock can be reduced from the clock input to the data output of the LSI without increasing the advance of the clock until the delay from the clock input to the data output of the LSI is completely eliminated. When observed from outside the LSI, it appears that the delay in the LSI has been reduced, that is, the performance of the LSI with respect to the delay has been improved, and the speed of the high-speed data transfer between the LSIs has been reduced. It is effective for the purpose.

Although the embodiments of the present invention have been described above, it goes without saying that the present invention can be modified in various ways.

[0047]

As described above, according to the present invention,
In the clock advance control method using the PLL, the PL
By inserting a delay gate (delay element) having an LSI penetration delay amount into the feedback path of L,
LL output is faster than the LSI input clock,
It seems that the delay from the clock input to the data output of the LSI, which was observed from outside, became smaller, that is, the performance of the LSI with respect to the delay became better. Further, both the amount of advance and the delay of the FF immediately before data output and the delay of the data output buffer are due to the gate delay in the same LSI, and the manufacturing process, operating temperature, and applied voltage during operation are the same. Therefore, the delay variation is the same, and the delay variation from the clock input to the data output of the LSI, which is observed from outside the LSI, can be suppressed. As a result of these,
When performing data transfer between a plurality of LSIs, the cycle time of data transfer between the LSIs can be reduced.

Further, the delay of the data input buffer varies when transferring data between LSIs.
By delaying the clock edge of the clock input of the FF receiving the data by the delay of the data input buffer with respect to the clock edge of the clock input of the LSI by the delay gate formed in the I, the delay of the data by the data input buffer The latch point can be delayed in the same way as the variation due to the manufacturing process, the operating temperature, and the applied voltage during operation.
It is possible to prevent the setup and hold margins from being lowered due to delay variations, and to reduce the cycle time of data transfer between LSIs.

[Brief description of the drawings]

FIG. 1 is a configuration example of an LSI clock control method according to the present invention.

FIG. 2 is an internal configuration example of a PLL circuit used in the present invention.

FIG. 3 is a time chart illustrating an operation of a phase comparison circuit in a PLL circuit.

FIG. 4 is a diagram illustrating an operation of a voltage controlled variable frequency oscillator in a PLL circuit.

FIG. 5 is a time chart for explaining the clock control operation of FIG. 1;

FIG. 6 is an example of the internal configuration of a synchronous logic LSI.

FIG. 7 is a diagram showing a clock signal distribution method of a conventional synchronous logic LSI.

FIG. 8 is a configuration example of a conventional LSI clock control method.

FIG. 9 is a configuration example of a conventional system for performing data transfer between LSIs.

FIG. 10 is a time chart for explaining the operation of data transfer between LSIs in FIG. 9;

FIG. 11 is a configuration example of a clock control method using a conventional PLL circuit.

FIG. 12 is a time chart illustrating the clock control operation of FIG. 11;

FIG. 13 is an overall configuration example of a system for transferring data between LSIs according to the present invention.

FIG. 14 is a configuration example of a clock control method of a system for performing data transfer between LSIs according to the present invention.

15 is a time chart for explaining the operation of data transfer between LSIs in FIG. 13;

FIG. 16 is another configuration example of a clock control method of a system for performing data transfer between LSIs according to the present invention.

FIG. 17 is a configuration example of a clock control method when a multi-phase clock of the present invention is used.

FIG. 18 is another configuration example of the clock control method when the multi-phase clock of the present invention is used.

FIG. 19 is still another configuration example of the clock control method when the multi-phase clock of the present invention is used.

20 is a diagram illustrating a clock frequency division / multi-phase clock generation circuit and a delay gate part of FIG. 19;

[Explanation of symbols]

1, 2 LSI created by synchronous logic 10 Combinational logic 16 Clock section 11000-1100n Flip-flop (FF) immediately before data output 12000-1200n FF 13000-1300n FF for exchanging data in LSI 150-15n data immediately after data input Output buffer 140 to 14n Data input buffer 17 Clock input buffer 160 Clock division / multiphase clock generation circuit 161, 1610 to 1611 Clock distribution system 162 PLL circuit 163 Delay gate 3 Clock generation unit 4, 5 LSI wiring

Claims (4)

[Claims] 1. A clock control method for an LSI comprising a plurality of logic elements operating in synchronization with a clock and a clock distribution circuit for inputting a clock from outside and distributing the clock to the plurality of logic elements. A phase-locked loop circuit (PLL circuit) that adjusts the phase of the output so that the phase of the reference input matches the phase of the feedback input. The externally input clock is used as the reference input of the PLL circuit, and the output of the PLL circuit is output. Input to the clock distribution circuit,
Distributing the output of the clock distribution circuit to each logic element, returning one of the outputs of the clock distribution circuit to the feedback input of the PLL circuit via a delay element, A clock control method for an LSI, wherein a delay amount from a clock input to a data output from the LSI (LSI penetration delay amount) or a delay amount close thereto is set. 2. The clock control method for an LSI according to claim 1, wherein a clock distributed to a logic element that latches data input from outside the LSI in synchronization with the clock is supplied to the clock input of the LSI. A clock control method for an LSI, characterized in that the clock is delayed by an amount of delay from an external data input to the logic element. 3. One or a plurality of first logic elements for outputting data to the outside via a data output buffer in synchronization with a clock, and latching data input from the outside in synchronization with the clock via a data input buffer. An LSI incorporating one or a plurality of second logic elements, and a clock unit for fetching an externally input clock via a clock input buffer and distributing the clock to each logic element, wherein the clock unit comprises: a reference input; A PLL circuit that adjusts the output phase so that the feedback input phase matches, a clock distribution circuit that generates a plurality of output clocks from the input clock, a delay amount of the clock input buffer and the first logic element The sum of the delay from the clock input to the data output of the device and the delay of the data output buffer, or A first delay element having a close delay amount, and a delay amount equal to or close to a sum of a delay amount from a clock input to a data output of the first logic element, a delay amount of the data output buffer, and a delay amount of the data input buffer; A second delay element that is a delay amount, wherein an output clock of the clock input buffer is used as a reference input of a PLL circuit, an output of the PLL circuit is used as an input clock of a clock distribution circuit, and a plurality of output clocks of the clock distribution circuit are provided. Is returned to the feedback input of the PLL circuit via the first delay element, and the other part of the plurality of output clocks of the clock distribution circuit is directly used as the clock input of the first logic element. Still another part of the plurality of output clocks of the circuit is configured to be the clock input of the second logic element via the second delay element. LSI characterized by. 4. A plurality of LSIs having the configuration according to claim 3,
A high-speed data transfer between the LSIs, comprising a wiring between LSIs for interconnecting a data output buffer and a data input buffer of each LSI and a clock generating unit for supplying a clock that changes at the same timing to a clock input buffer of each LSI; LSI system that enables