JPH11103262A - Frequency converter for superheterodyne receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency converter capable of sharply reducing power consumption in the stand-by state of a superheterodyne receiver and quickly starting operation at the time of turning on a power supply. SOLUTION: The frequency converter is provided with a single frequency oscillation circuit 7 as a local oscillator for converting the frequency of a transmitter-receiver having a superheterodyne receiving circuit in addition to a PLL frequency synthesizer 6. The converter is also provided with a switch 15 for selectively turning off a driving power supply for the synthesizer 6 and a switch 16 for selectively turning off a driving power supply for the circuit 7. In the stand-by state of reception, the switch 15 is held at OFF. During the reception of main information, the switch 16 is held at OFF.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency converter for a superheterodyne receiver used in a multi-channel access data transmission system having a relatively narrow service area.

[0002]

2. Description of the Related Art A relatively small area (1 in a factory, building, etc.)
The specific low-power radio equipment having a service area of about 00 to 200 m) is, for example, 429.1750 MHz to 42 MHz.
The frequency band of 9.7375 MHz is divided into 46 channels for use. More specifically, 4
Any one of the six channels is used as a control channel, and the remaining 45 channels are used as data (main information) transmission channels. The control signal of the control channel is
First transceiver prior to main data transmission (eg, master station)
And a second transceiver (for example, a slave station).

[0003]

The actual use time of actually transmitting data or information using a transceiver is generally much shorter than the time of waiting for transmission of data or information. It is. Since it is not known when a request to start data transmission using the control channel, that is, when a call is generated, the driving power supply of the transceiver must be turned on even in the standby state. Therefore, in order to reduce the power consumption of the transceiver, it is important to reduce the power consumption in the standby state. In order to reduce the power consumption in the standby state, it is conceivable to turn off the power supply of the unnecessary part in the standby state. However, since the control signal of the control channel must be received in the standby state, it has been difficult to significantly reduce the power consumption. This type of transceiver also includes a PLL frequency synthesizer to selectively use a control channel and a plurality of main information (data) channels. However, since the PLL frequency synthesizer includes a VCO, a PLL circuit, and the like in addition to the temperature compensated crystal oscillator, power consumption is relatively large. Also, the time (lock-up time) from when the frequency setting data is input to the PLL frequency synthesizer when the power is turned on until the desired frequency is obtained is relatively long, and the use cannot be started quickly. Further, it is necessary to input the frequency setting data to the PLL frequency synthesizer every time the power is turned on, so that the control software becomes complicated.

It is an object of the present invention to provide a frequency conversion device capable of greatly reducing the power consumption of a superheterodyne receiver in a standby state and starting operation immediately upon power-on. It is in.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems and achieve the above object, the present invention provides a method for selectively receiving a main information signal of a plurality of main information channels and a control signal of one control channel. A PLL frequency synthesizer for a superheterodyne receiver, comprising: a PLL frequency synthesizer that selectively generates signals of a plurality of frequencies for selectively receiving at least main information signals of the plurality of main information channels; A single-frequency oscillator configured to generate a single-frequency signal for receiving the control signal of the channel and to be driven with less power consumption than the PLL frequency synthesizer; At the time of reception and at the time of reception standby, select the output signal of the single frequency oscillation circuit, select from the main information signals of the plurality of main information channels The PL when receiving one that was
Selecting means for selecting an output signal of the L frequency synthesizer; and mixing the input signal of the receiver and the output signal selected by the selecting means to convert the frequency of the input signal to a lower frequency. A mixing circuit for stopping supply of driving power to at least a part of the PLL frequency synthesizer in at least a part of a reception standby period;
And a power supply unit configured to supply driving power to the PLL frequency synthesizer at least when the main information is received. As described in claims 2 and 4, a frequency conversion frequency for receiving the main information channel and a frequency conversion frequency for receiving the control channel are selected by an impedance circuit having first and second frequency characteristics. Can be obtained. Further, both the control channel frequency and the main information frequency can be formed based on the output of the single frequency oscillation circuit.

[0006]

According to the present invention, in addition to the PLL frequency synthesizer, a single frequency oscillating circuit for receiving a control channel or a frequency generating circuit for a control channel is provided to supply power to the PLL frequency synthesizer in a standby state. Is stopped, so that the PLL
The power consumption of the frequency synthesizer is reduced, and the power consumption of the receiver is also reduced. In addition, when the power is turned on, the single frequency oscillation circuit or the control channel frequency generation circuit rises more quickly than the PLL frequency synthesizer, so that the control channel can be received quickly. According to the second and fourth aspects of the present invention, when the impedance circuits having the first and second frequency characteristics are provided, the selection between the control channel frequency and the main information channel frequency can be easily achieved. According to the third and fourth aspects of the present invention, the reference oscillation circuit is shared by the control channel frequency generation circuit and the PLL frequency synthesizer, and the circuit configuration can be simplified.

[0007]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to the drawings.

[0008]

FIG. 1 shows a multi-channel access type transceiver according to a first embodiment. This transceiver is a specific low-power radio equipment having a small antenna power (about 10 mW) with a relatively narrow range (about 100 to 200 m) as a service area, and mainly performs binary FSK modulation (frequency shift keying) on data. ) Is used for a system for wireless transmission, and the receiving side is configured as a superheterodyne receiving circuit. FIG. 5 shows the FSK modulation method in principle. In this method, as shown in FIG. 5B, the amplitude change of a binary signal corresponding to the logic 0 and 1 in FIG. To change the frequency. Also, this transceiver
As shown in FIG. 6, the frequency band of 429.1570 MHz to 429.7375 MHz is divided into 46 channels and used, for example, f0 to f1.
Is used as a control channel for transmitting control signals, and f1 to f46 are used as main information channels for transmitting main information (data). Although only one transceiver is shown here, in reality, for example, one system is configured with a transceiver of one master station and transceivers of a plurality of slave stations. The transceiver of each slave station has an address (identification code) and is configured to be distinguishable from each other. When the master station transceiver and the slave station transceiver communicate with each other, first, the start of transmission / reception is confirmed using the control channel, and then the main information is transmitted using the main information channel.

The transceiver shown in FIG. 1 used as described above includes an antenna terminal 1a to which an antenna 1 is connected, a bandpass filter (BPF) 2, a transmission / reception switching circuit 3, a reception input amplifier 4, and a frequency conversion device. Mixing circuit 5, P
LL frequency synthesizer 6, single frequency oscillating circuit 7, switching circuit 8 as means for selecting a signal for frequency conversion, transmission / reception switching circuit 9, reception signal processing circuit 10, carrier sense circuit 11, transmission input circuit 12, transmission output amplifier 13 , Transmission / reception control circuit 14, and first and second power switches 1
5 and 16. In FIG. 1, the portion excluding the transmission input circuit 12 and the transmission output amplifier 13 is a superheterodyne receiving circuit. The PLL frequency synthesizer 6 functions not only as a local oscillator but also as an FM modulator, and is used for both transmission and reception.

Next, each part will be described in detail. The antenna terminal 1 transmits and receives signals in the transmission and reception frequency band.
The BPF 2 connected to the antenna terminal 1a allows signals in the transmission / reception frequency band to pass. The transmission / reception switching circuit 3 includes a switch for connecting the BPF 2 to the reception input amplifier 4 during reception and standby, and a switch for connecting the transmission output amplifier 13 to the BPF 2 during transmission, and is controlled by the transmission / reception control circuit 14.

The mixing circuit 5 is connected to an output line of the reception input amplifier 4 and a common output line 17 as a frequency conversion signal (local oscillation signal) output line of the switching circuit 8 and to determine the reception input frequency and the local oscillation frequency. The first intermediate frequency corresponding to the difference between the two input frequencies is obtained by mixing and beats. In the present embodiment, a single frequency oscillation circuit 7 is newly provided in addition to the mixing circuit 5 and the PLL frequency synthesizer 6 in order to configure the frequency conversion device. That is, in a conventional superheterodyne receiver, P
The LL frequency synthesizer 6 supplies the frequencies for receiving all the channels (control channel and main information channel). In this embodiment, however, a single frequency oscillation circuit 7 is newly provided, and the control channel frequency is supplied therefrom. Then P
The LL frequency synthesizer 6 supplies the frequency for the main information channel.

The single-frequency oscillating circuit 7 is a fixed local oscillating circuit comprising a crystal oscillator (oscillator) 18 having good temperature characteristics, an oscillating circuit 19 with temperature compensation, and an amplifier 20, as shown in principle in FIG. And generates a local oscillation frequency necessary for receiving the control channel (first channel). Since this single frequency oscillation circuit 7 does not include a PLL circuit,
Since the power consumption and the current are smaller than those of the L frequency synthesizer 6 and there is no lock-up time, the rise at the time of turning on the power is quick.

The PLL frequency synthesizer 6 includes a PLL
(Phase Locked Loop) circuit, which is a well-known device, and as shown in principle in FIG. 3, a variable frequency divider 23 composed of a crystal oscillator 21 having good temperature characteristics, an oscillation circuit 22 with temperature compensation, and a programmable divider. , A phase comparator 24, a low-pass filter (LPF) 25, a VCO (voltage controlled oscillator) 26, and a variable frequency divider 27 composed of a programmable divider for receiving a main information channel (second to 46th channels). Various local oscillation frequencies are transmitted to the line 28, and the VCO 26 transmits a frequency modulation signal (binary FSK modulation signal) corresponding to the transmission signal in response to the transmission signal on the line 29 during transmission. Variable frequency divider 2
Reference numerals 3 and 27 have a predetermined frequency division ratio in response to frequency control data supplied from the bus 30. The PLL frequency synthesizer 6 has a feature that various frequencies can be accurately generated, but has a drawback that power consumption is large because it includes the phase comparator 24, the VCO 26, and the like that constitute the PLL circuit. However, since the lock of the PLL circuit is not immediately established, there is a disadvantage that the rise is delayed, and that frequency control data must be supplied to the variable frequency dividers 23 and 27 every time the power is turned on, so that control software becomes complicated. .

In this embodiment, the PLL frequency synthesizer 6
As shown in FIG. 1, a drive power supply terminal + Vcc connected to a transmitter / receiver power supply composed of a battery, as shown in FIG.
A first power switch 15 is provided between the PLL frequency synthesizer 6 and the power supply to the PLL frequency synthesizer 6 by shutting off the switch 15 under the control of the transmission / reception control circuit 14 during standby. Further, a second power switch 16 is provided between the driving power supply terminal + Vcc and the single frequency oscillation circuit 7, and is controlled by the transmission / reception control circuit 14 to be turned on during control channel reception and standby, and turned off during reception of the main information channel. I have. Therefore, the power consumption of the local oscillation unit during standby is only the power consumption of the single frequency oscillation circuit 7, and the power consumption of the frequency conversion unit during standby is
It is a fraction of the conventional value.

The reception signal processing circuit 10 connected to the output line of the mixing circuit 5 is a well-known circuit, and includes an amplifier 31 and a band-pass filter (BDF) 32 as shown in FIG.
And a second mixing circuit 33 for obtaining a second intermediate frequency.
, A second local oscillation circuit 34, an amplifier 35, a band limiting filter 36, an amplifier 37, a detection circuit 38, a low-pass filter 39, and a waveform shaping circuit 40.
The amplifier 31 is connected to the first mixing circuit 5 of FIG. The second mixing circuit 33 is connected to the amplifier 31 via the BPF 32 and to the second local oscillation circuit 34 to form a second frequency conversion circuit. The output of the second mixing circuit 33 is an amplifier 35, a band limiting filter 36,
The signal is sent to the detection circuit 38 via the amplifier 37. The detection circuit 38 is a known quadrature detection circuit, and includes a circuit for phase-shifting the FM signal and a multiplier for multiplying the original FM signal by the phase-shifted FM signal. FIG. 4 shows the phase shift circuit and the multiplier as a detection circuit 38. By passing the output of the detection circuit 38 composed of the multiplier output to the LPF 39 of the next stage and further to the waveform shaping circuit 40 composed of the comparator, a demodulated waveform as shown in FIG. 5A can be obtained. The demodulated signal is sent to the transmission / reception control circuit 14 in FIG.

The carrier sense circuit 11 connected to the reception signal processing circuit 10 in FIG. 1 includes first and second carrier sense circuits 41 as first and second determination means, as shown in FIG. 42 and an AND gate 43.
The carrier sense circuit 11 detects the presence / absence of a received signal (carrier) and, based on this, knows the channel use state (vacant channel). The conventional carrier sense circuit is configured to determine the presence or absence of a received signal by noise detection.In this embodiment, however, the method of detecting the presence or absence of a received signal by noise and the reception based on the voltage level of the signal on the transmission line are used. The carrier sense circuit 11 is configured by combining a method of detecting the presence or absence of a signal (electric field).

The first carrier sense circuit 41 determines the presence or absence of a received signal using a linear correlation between the weak input signal level and the demodulation noise level, as in the conventional carrier sense circuit. And a band pass filter (BPF) 44 for passing a white noise component.
, A noise amplifier 45, a rectifier circuit 46 as a noise detector, a comparator 47, and a reference voltage source 48. The BPF 44 is connected to the output line of the detection circuit 38. The output of the BPF 44 is input to a voltage comparator 47 via a noise amplifier 45 and a rectifier circuit 46.
The comparator 47 determines whether the amplitude of the noise component is equal to the reference voltage source 48.
Generates an output indicating whether it is greater than. In this embodiment, a high-level output is obtained from the comparator 47 when the noise component is higher than the reference level. The noise component is low when the control signal or the main information signal is being received, and is high when it is not being received. Therefore, when the output of the comparator 47 indicates that the amplitude level of the noise component is equal to or higher than the reference value, it indicates that the channel is a vacant channel not used for signal transmission. Conversely, when the amplitude level of the noise component is lower than the reference value, it indicates that the signal is being transmitted to the channel.

The second carrier sense circuit 42 includes a signal transmission line signal amplitude detection circuit 49, a low-pass filter (LPF) 50, a voltage comparator 51, and a reference voltage source 52. The amplitude detection circuit 49 is connected to the output line of the amplifier 35 and detects the voltage of the signal line before detection. The signal amplitude of the signal line is proportional to the strength of the aerial electric field. Therefore, when the control signal or the main information signal (FM signal) is being transmitted to the currently received channel, an output corresponding to the signal amplitude is obtained from the amplitude detection circuit 49, and the control signal or the main information signal is output. No signal is obtained when not transmitting. The output of the amplitude detection circuit 49 is L for integration.
After being smoothed by the PF 50, it is input to the comparator 51,
Compared with the reference voltage of the reference voltage source 52, when the input signal is higher than the reference voltage, a low-level comparison output indicating that there is a received signal (the channel is in use) is obtained,
Conversely, when the input signal is equal to or lower than the reference voltage, a high-level comparison output indicating that there is no received signal (the channel is vacant) is obtained.

The two input terminals of the AND gate 43 as the final decision logic circuit are two comparators 47, 5
1 output line. Therefore, an output indicating an empty channel (no received signal) is obtained from the AND gate 43 only when both of the two comparators 47 and 51 are simultaneously generating an output indicating an empty channel (no received signal). To the transmission / reception control circuit 14. The first carrier sense circuit 41 based on noise is:
When a plurality of wireless data transmission systems are in use simultaneously and noise due to intermodulation interference occurs, the interference noise is erroneously detected as white noise. When such a detection is made, the first carrier sense circuit 41 generates an output indicating that there is no signal (a vacant channel) despite the presence of a signal in the specific channel. However, in the present embodiment, the second carrier sense circuit 42 based on the signal amplitude is provided, and the presence or absence of the received signal is determined based on the output of the AND gate 43.

The transmission input circuit 12 supplies a control signal and a main information signal to the VCO 26 of the PLL frequency synthesizer 6 in a binary format in the transmission mode. As a result, an FSK modulated signal is obtained from the VCO 26. The transmission / reception switching circuit 9 connects the synthesizer 6 to the switching circuit 8 in the reception mode, and connects the synthesizer 6 to the transmission amplifier 13 in the transmission mode.

Next, a procedure for transmitting a control signal and main information based on the control of the transmission / reception control circuit 14 will be described with reference to FIGS. FIGS. 7 to 9 show the flow of operation when main information is transmitted from the first transceiver of the master station (transmission side) to the second transceiver of the slave station (reception side). The left half shows the operation of the first transceiver on the transmitting side, and the right half shows the operation of the second transceiver on the receiving side. Here, the first and second transceivers are assumed to have the same configuration, and the description will be made assuming that there are two transceivers shown in FIG. In the standby (standby) state of the first and second transceivers shown in step S0 of FIG. 7, the power switch 15 of the PLL frequency synthesizer 6 is turned off, and the power switch 16 of the single frequency oscillation circuit 7 is turned off. Is turned on.
Next, when a transmission command signal is given to the first transceiver as shown in step S1 of FIG. 7, the first transceiver changes the idle state of the control channel (for example, the first channel) as shown in step S2. Check by the carrier sense circuit 11. Since the frequency of the single frequency oscillation circuit 7 is set to the control channel (first channel) reception frequency, the idle state of the control channel in the standby state can be immediately checked. Even if the control channel is used in another system or the like, it is rarely used continuously for a long time. Therefore, if the check is repeated, an output indicating an empty channel is obtained from the carrier sense circuit 11. Next, as shown in step S3, the second transceiver
The control signal of the connection request is transmitted using the control channel together with the address signal of the transceiver. When the control signal is transmitted, the second transceiver on the receiving side receives the control signal as shown in step S4. Since the second transceiver is in a standby state for receiving the control channel, when the control signal is transmitted, it receives the signal, demodulates it, and determines whether or not it is the control signal of its own address.
To judge. When it is determined that the control signal is a control signal for the second transceiver, before transmitting the control signal indicating connection permission in step S6, as shown in step S5, a carrier sense circuit determines whether or not the control channel is still free. Check at 11, and if it is free, proceed to the next step S6, turn on the power switch 15 to use the PLL frequency synthesizer 6 for transmission, and send a connection permission control signal to the first transceiver. Note that even if the power of the PLL frequency synthesizer 6 is turned on, the transmission / reception switching circuit 9
Since is set on the transmitting side, the PLL frequency synthesizer 6 is irrelevant to the receiving circuit. Next, the first
The transceiver receives a control signal indicating connection permission as shown in step S7. Next, as shown in step S8 in FIG. 8, the first transceiver transmits the main information channel (second to 46th).
Channel), and determines a channel to be used for transmitting main information. Next, as shown in step S9, the first transceiver transmits a main information channel selection signal (a control signal indicating a used channel), which is one type of control signal, together with the address of the second transceiver. Note that the control channel may be checked for vacancy prior to transmission of the selection signal in step S9. The second transceiver on the receiving side receives the main information channel selection signal (control signal indicating the used channel) and sends it to the transmission / reception control circuit 14, as shown in step S10. The transmission / reception control circuit 14 controls the variable frequency dividers 23 and 27 of the PLL frequency synthesizer 6 so as to obtain a frequency for receiving the signal of the main information channel specified by the selection signal as shown in step S11. Next, as shown in step S12, the power switch 16 of the first transceiver is controlled to be turned off in preparation for receiving the main information channel. Next, as shown in step S13, the switching circuit 8 is set to PLL.
The output of the frequency synthesizer 6 is controlled to be sent to the mixing circuit 5. Next, as shown in step S14 of FIG.
The transmission / reception switching circuits 3 and 9 of the transceiver are set to the reception mode. Next, the main information is transmitted from the first transceiver as shown in step S15, and the main information is received in the second transceiver as shown in step S16. When the second transmitter on the receiving side receives the main information of the main information channel, the PLL frequency synthesizer 6 is connected to the mixing circuit 5, and the reception of the main information channel becomes possible. When the communication of the main information is completed, switching control for obtaining a standby state is executed as shown in step S17. That is, the second transmission / reception side is set to the reception mode, the power switch 15 of the PLL frequency synthesizer 6 is turned off, the power switch 16 of the single frequency oscillation circuit 7 is turned on, and switching as frequency selection means is performed. The standby state is set by switching the circuit 8 to the single frequency oscillation circuit 7 side. As a result, as shown in step S18, a standby state similar to step S0 is established. In addition, FIG.
In the flow of FIG. 9, more carrier sense steps can be added, and a main information transmission permission control signal transmission / reception step can be added.

[0022]

Second Embodiment Next, a transceiver according to a second embodiment of the present invention will be described with reference to FIGS. However, FIG.
0 and FIG. 12 showing a third embodiment to be described later.
The same reference numerals are given to substantially the same portions as those described above, and the description thereof is omitted.

The transceiver of FIG. 10 has the same configuration as that of FIG. 1 except that the switching circuit 8 of FIG. 1 is replaced with a mutual interference prevention circuit 8a. 10 is connected to a line 9a where the PLL frequency synthesizer 6 reaches the mixing circuit 5 via the receiving side switch of the transmission / reception switching circuit 9 and to a line 7a where the single frequency oscillation circuit 7 reaches the mixing circuit 5. And
The common frequency conversion signal output line 17 derived therefrom is connected to the mixing circuit 5.

FIG. 11 shows the mutual interference prevention circuit 8a in detail. The mutual interference prevention circuit 8a includes impedance circuits 61 and 62 having first and second frequency characteristics.
And a coupling capacitor 63. The impedance circuit 61 having the first frequency characteristic includes four capacitors C1
, C2, C3, C4 and one inductance L1 and is constructed in the same manner as a matching circuit, and outputs the output frequency (second to second) of the PLL frequency synthesizer 6 inputted to the line 9a.
The signal at the local oscillation frequency for the forty-sixth channel) is transmitted on the common line 17 while the line 7a and the second circuit 6
PL of the signal of the output frequency (local oscillation frequency for the first channel) of the single frequency oscillation circuit 7 obtained through
The inflow to the L frequency synthesizer 6 is prevented. In other words, the first impedance circuit 61 is a PLL for the output signal of the single frequency oscillation circuit 7.
It is formed so as to prevent interference of the frequency synthesizer 6. The impedance circuit 62 having the second frequency characteristic includes four capacitors C5, C6, C7, C4
8 and one inductance L2, which are constructed in the same manner as the matching circuit. The signal of the output frequency (local oscillation frequency for the first channel) of the single oscillation circuit 7 input from the line 7a side is a common output line. 17, the output frequency of the PLL frequency synthesizer 6 (second to second).
The local oscillation frequency for the 46th channel is prevented from flowing into the single frequency oscillation circuit 7 side. In other words, the second impedance circuit 62 is
It is configured to prevent the single frequency oscillation circuit 7 from interfering with the output signal of the L frequency synthesizer 6.

Therefore, in this embodiment, the frequency of the PLL frequency synthesizer 6 and the frequency of the single frequency oscillator 7 can be selectively sent to the mixing circuit 5 without any special switching control. Is simplified. In this embodiment, in order to prevent both the output frequency of the PLL frequency synthesizer 6 and the output frequency of the single frequency oscillating circuit 7 from being input to the mixing circuit 5 at the same time, the first and second power supplies are switched to the reception mode. The switches 15 and 16 are controlled so as not to be turned on at the same time.

[0026]

Third Embodiment A transceiver according to a third embodiment shown in FIG. 12 includes a single frequency oscillation circuit 6a using the PLL frequency synthesizer 6 of the first embodiment shown in FIGS. 1 and 3 as a reference frequency source. It has the same configuration as that of FIG. 1 except that it is divided into a PLL frequency synthesizer 6b and a control channel frequency generator 7 'is provided instead of the single frequency oscillator 7 of FIG.

The single-frequency oscillating circuit 6a of the third embodiment comprises a crystal oscillator 21 and an oscillating circuit 22, as shown in FIG. This is similar to the crystal oscillator 21 and the oscillation circuit 22 of the PLL frequency synthesizer 6 in FIG. It should be noted that the single frequency oscillation circuit 6a of the third embodiment can be replaced with the crystal oscillator 18 and the oscillation circuit 19 of the first embodiment shown in FIG.

The PLL frequency synthesizer 6b according to the third embodiment is the same as the PLL frequency synthesizer 6 according to the first embodiment shown in FIG. 3 except that the crystal oscillator 21 and the oscillation circuit 22 are removed. Is the same as In addition,
The output of the single frequency oscillation circuit 6a is input to the variable frequency divider 23 of the PLL frequency synthesizer 6b.

The control channel frequency generating circuit 7 'of the third embodiment comprises an amplifier 18a, a multiplying circuit 19a and an amplifier 20a as shown in FIG. It is connected to a circuit 22. From the control channel frequency generating circuit 7 ', FIG.
The same frequency as that of the single frequency oscillation circuit 7 is output.

The first power switch 15 has a power terminal + Vcc.
And the PLL frequency synthesizer 6b. The second power supply terminal 16 is provided between the power supply terminal + Vcc and the control channel frequency generating circuit 7 '. The first power switch 15 is controlled to be turned on at least at the time of receiving the main information channel and at the time of the transmission mode. The second power switch 16 is turned on at least when receiving a control channel. The power supply terminal of the single frequency oscillation circuit 6a is always connected to the power supply terminal of the transceiver.

Also in the third embodiment, the power switch 15 of the PLL frequency synthesizer 6b is turned off when the control channel reception is on standby, and the power supply thereto is cut off. Fewer as in the example. Further, since the single frequency oscillation circuit 6a including the expensive crystal resonator 21 having good temperature characteristics and the oscillation circuit 22 having the temperature compensation circuit is shared by the PLL frequency synthesizer 6b and the control channel oscillation circuit 7 ', the cost is reduced. Can be reduced.

[0032]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The switching circuit 8 in the transceiver of the third embodiment shown in FIG. 11 can be replaced with an interference prevention circuit 8a composed of impedance circuits having first and second frequency characteristics in FIG. (2) The point in time when the power switch 15 of the PLL frequency synthesizers 6, 6b is turned on can be changed. For example, even if the power switch 15 is turned on immediately after receiving the control signal of the control channel for the first time, the on state can be maintained until the reception of the main information is completed. In short, when the power supply to the PLL frequency synthesizer 6 is stopped at least during a part of the standby period, the effect of reducing power consumption can be obtained. (3) Since the single frequency oscillation circuit 7 of FIG. 1 and the control channel frequency generation circuit 7 'of FIG. 12 do not include a PLL circuit, they consume less power. Therefore, the drive power can always be supplied without the power switch 16. FIG.
In the case of the second embodiment, which is 0, a switch for cutting off the output of the single frequency oscillation circuit 7 when a signal is sent from the PLL frequency synthesizer 6 to the interference prevention circuit 8a is added, and the power switch 16 is omitted. be able to. (4) The crystal oscillator and the oscillation circuit of the second local oscillation circuit 34 in FIG. 4 can be shared by the crystal oscillator 18 and the oscillation circuit 19 in FIG. 2 or the crystal oscillator 21 and the oscillation circuit 22 in FIG. . (5) It is possible to save power by turning off only a part of the PLL frequency synthesizer 6 without turning off the entire power supply of the PLL frequency synthesizer 6 with the switch 15. (5) From FIG. 1, FIG. 10 and FIG.
2. It is possible to omit the transmission output amplifier 13 and the transmission / reception switching circuits 3 and 9 and to use only the receiver. In short, the transmitter and the receiver can be configured independently. (6) The present invention can be applied not only to transmission and reception using FM signals but also to transmission and reception using AM signals.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a transceiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a single-frequency oscillation circuit of FIG. 1 in detail.

FIG. 3 is a block diagram illustrating a PLL frequency synthesizer of FIG. 1 in detail;

FIG. 4 is a block diagram showing a reception signal processing circuit and a carrier sense circuit of FIG. 1 in detail.

FIG. 5 is a waveform diagram showing FSK modulation in principle.

FIG. 6 is a diagram showing a channel configuration used in the transceiver of FIG. 1;

FIG. 7 is a diagram showing a flow of an operation of transmission and reception by the two transceivers of FIG. 1;

FIG. 8 is a diagram showing a flow of operation following FIG. 7;

FIG. 9 is a diagram showing a flow of operation following FIG. 8;

FIG. 10 is a block diagram illustrating a transceiver according to a second embodiment.

11 is a circuit diagram showing the mutual interference prevention circuit of FIG.

FIG. 12 is a block diagram illustrating a transceiver according to a third embodiment.

13 is a circuit diagram showing in detail a single frequency oscillation circuit, a PLL frequency synthesizer, and a control channel frequency generation circuit of FIG. 12;

[Explanation of symbols]

 5 Mixing circuit for frequency conversion 6 PLL frequency synthesizer 7 Single frequency oscillation circuit 8 Switching circuit 11 Carrier sense circuit 15, 16 Power switch

Claims (4)

[Claims] 1. A frequency converter for a superheterodyne receiver for selectively receiving a main information signal of a plurality of main information channels and a control signal of one control channel, comprising: A PLL frequency synthesizer for selectively generating a plurality of frequency signals for selectively receiving a main information signal; and a PLL for generating a single frequency signal for receiving the control signal of the control channel and the PLL. A single-frequency oscillation circuit configured to be able to be driven with less power consumption than a frequency synthesizer, selecting an output signal of the single-frequency oscillation circuit when receiving a control signal of the control channel and at a reception standby time, When receiving one selected from main information signals of a plurality of main information channels, the output signal of the PLL frequency synthesizer is Selecting means for selecting; a mixing circuit for mixing the input signal of the receiver and the output signal selected by the selecting means to convert the frequency of the input signal to a lower frequency; Power supply means configured to stop supplying drive power to at least a part of the PLL frequency synthesizer during at least a part of a standby period, and to supply drive power to the PLL frequency synthesizer at least when receiving the main information. A frequency conversion device comprising: 2. A frequency converter for a superheterodyne receiver for selectively receiving a main information signal of a plurality of main information channels and a control signal of one control channel, comprising: A PLL frequency synthesizer for selectively generating a plurality of frequency signals for selectively receiving a main information signal; and a PLL for generating a single frequency signal for receiving the control signal of the control channel and the PLL. A single frequency oscillation circuit configured to be driven with lower power consumption than a frequency synthesizer; and a signal output line for frequency conversion, connected between the PLL frequency synthesizer and the signal output line for frequency conversion. And an output signal of the PLL frequency synthesizer is formed, and An impedance circuit having a first frequency characteristic formed so as to prevent interference of the PLL frequency synthesizer with an output signal, the single frequency oscillation circuit, and the frequency conversion signal output line; An impedance circuit having a second frequency characteristic formed so as to pass an output signal of the one frequency oscillation circuit and configured to prevent interference of the single frequency oscillation circuit with an output signal of the PLL frequency synthesizer. Having a mutual interference preventing means, for mixing the input signal of the receiver and the signal of the frequency conversion signal output line of the mutual interference preventing means to convert the frequency of the input signal to a lower frequency. A mixing circuit, the single-frequency oscillation when receiving the control signal of the control channel and when waiting for reception; Drive power to the PLL frequency synthesizer, but does not supply drive power to the PLL frequency synthesizer. When receiving one selected from the main information signals of the plurality of main information channels, the drive power is supplied to the PLL frequency synthesizer. Power supply means for supplying the driving power to the single-frequency oscillating circuit. 3. A frequency converter for a superheterodyne receiver for selectively receiving a main information signal of a plurality of main information channels and a control signal of one control channel, wherein the frequency converter generates a single frequency output signal. A single frequency oscillating circuit, and selectively generating signals of a plurality of frequencies for selectively receiving at least the main information signals of the plurality of main information channels based on an output signal of the single frequency oscillating circuit. A PLL frequency synthesizer that generates a frequency for receiving the control signal of the control channel based on an output signal of the single frequency oscillation circuit, and is driven with lower power consumption than the PLL frequency synthesizer. A control channel frequency generating circuit configured so as to be able to receive the control signal of the control channel and at the time of reception standby Selecting means for selecting an output signal of the control channel frequency generating circuit and selecting an output signal of the PLL frequency synthesizer when receiving one selected from the main information signals of the plurality of main information channels; A mixing circuit for mixing the input signal of the receiver and the output signal selected by the selection means to convert the frequency of the input signal to a lower frequency; and Power supply means for stopping supply of driving power to at least a part of the PLL frequency synthesizer and supplying driving power to the PLL frequency synthesizer at least when the main information is received. Frequency conversion device. 4. A frequency converter for a super heterodyne receiver for selectively receiving a main information signal of a plurality of main information channels and a control signal of one control channel, wherein the frequency converter generates a single frequency output signal. A single frequency oscillating circuit, and selectively generating signals of a plurality of frequencies for selectively receiving at least the main information signals of the plurality of main information channels based on an output signal of the single frequency oscillating circuit. A PLL frequency synthesizer that generates a frequency for receiving the control signal of the control channel based on an output signal of the single frequency oscillation circuit, and is driven with lower power consumption than the PLL frequency synthesizer. A frequency generation circuit for a control channel configured so as to be able to control the signal, and a signal output line for frequency conversion. Connected between the synthesizer and the frequency conversion signal output line and configured to pass the output signal of the PLL frequency synthesizer, and to prevent interference of the PLL frequency synthesizer with the output signal of the control channel frequency generation circuit. Connected between the impedance circuit having the first frequency characteristic, the control channel frequency generation circuit, and the frequency conversion signal output line, and passing the output signal of the control channel frequency generation circuit. And the PL
An interference preventing means having an impedance circuit having a second frequency characteristic formed so as to prevent interference of the control channel frequency generating circuit with an output signal of the L frequency synthesizer; A mixing circuit for mixing the signal of the frequency conversion signal output line to convert the frequency of the input signal to a lower frequency, and for at least a part of the PLL frequency synthesizer in at least a part of a reception standby period. A frequency conversion device comprising: a power supply unit configured to stop supplying driving power and supply driving power to the PLL frequency synthesizer at least when receiving the main information.