JPH11103245A - Bipolar cmos output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bipolar CMOS output circuit capable of being driven at low voltage and reducing chip size. SOLUTION: This output circuit is provided with a bipolar transistor Q10 connected to the drain mutual node of a CMOS circuit, connecting its base to a signal output terminal Dout through PN junction diodes D10, D11, connecting its collector to one power supply potential VDD out of two power supply potential levels and connecting its emitter to the other power supply potential VSS through feedback resistors R11, R12 and bipolar TRs Q11, Q12 totem pole connected between the two power supply potential levels VDD, VSS and connecting their mutual node to the signal output terminal Dout. A signal input terminal Din is connected to the base of the TR Q11 and the mutual node of the resistors R11, R12 is connected to the base of te TR Q12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a combination of a bipolar transistor and a MOS transistor.
The present invention relates to a bi-CMOS output circuit formed in an S semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a CMOS / T using a C-MOS output circuit and a bi-CMOS circuit has been known as one of the embedded LSI technologies having both an analog function and a digital function.
TL output circuits are widely used. As shown in FIG. 4, a P-channel MOS transistor P1 and an N-channel MOS transistor N1 having drains and gates interconnected, a similarly connected P-channel MOS transistor P2 and N-channel MOS transistor N2,
The CMOS output circuit composed of the signal input terminal Din and the signal output terminal Dout requires a P-channel MOS transistor P2 and an N-channel MOS to increase the output.
Although the size of the transistor N2 must be increased, which leads to an increase in the chip size of the integrated circuit, it is widely used due to low power consumption.

Further, in a TTL output circuit composed of bipolar transistors Q1 to Q5 as shown in FIG. 3, an output amplitude is generated by a resistance load R3 of the bipolar transistor Q1, so that current consumption increases. When the voltage between the collector and the emitter enters the saturation region, a capacitance is formed in the bipolar transistor, and high-speed operation is hindered. Therefore, in order to perform a high-speed operation, the bipolar transistor Q1,
The Schottky barrier diodes S1, S2, and S3 for preventing saturation are connected between the collectors and bases of Q2 and Q5, respectively, for the purpose of improvement. However, a special manufacturing process is required, which leads to an increase in cost.

Therefore, a TTL output circuit has been proposed in which the Schottky barrier diode is not connected between the base and the collector of the bipolar transistor and the bipolar transistor operates without being saturated. As shown in FIG. 2, Darlington-connected bipolar transistors Q4, Q5 and Q3, Q6 are provided to quickly extract current from a capacitive load or the like connected to the output terminal Dout. Particularly, in the bipolar transistors Q3 and Q6, the voltage between the base of the bipolar transistor Q3 and the collector of the bipolar transistor Q6 is clamped by the PN junction diodes D1 and D2 connected in series. Thus, the saturation of the bipolar transistor Q3 and the bipolar transistor Q6 is prevented.

Further, in the same circuit, feedback resistors R3 and R4 are connected to the emitter of the bipolar transistor Q3,
The interconnection point of these feedback resistors is connected to the base of bipolar transistor Q6 to prevent the saturation of bipolar transistor Q6. In the same circuit, the input terminal D
The collectors of the differential pair bipolar transistors Q1 and Q2 having in, Ref and the constant current source Ig are directly connected to the bases of the bipolar transistors Q3 and Q4, respectively, so as to drive the output stage.

In the output circuit having the above configuration, the node C is connected to VDD-2 × Vf (bipolar transistors Q4, Q5
High-speed operation with the amplitude of the base-emitter voltage of the differential pair bipolar transistor Q
1. It is necessary to increase the current Ig flowing from the emitter of Q2, and there is a problem that power consumption increases.
In order to prevent the output pull-up bipolar transistor from being saturated, the pull-up bipolar transistors Q4 and Q5 are Darlington connected. In the output circuit having such a configuration, when a low-voltage power supply such as VDD = 3.3 V is used, the output voltage at the logic H level of the output terminal Dout is 3.3 V−2 Vf ≒ 1.7 V. There is no voltage margin for the connected circuit, and it cannot be used with a 3.3 V power supply.

[0007]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention has a smaller cell size than a CMOS output circuit and omits a Schottky barrier diode for preventing saturation of a transistor in a TTL output circuit. Can,
Moreover, a bi-CMOS output circuit that operates at a low voltage is proposed.

[0008]

SUMMARY OF THE INVENTION A bipolar CMOS output circuit according to the present invention comprises a bipolar transistor for pull-down driven by a bipolar transistor which is turned on and off by the output of a CMOS circuit, and a bipolar transistor totem-pole connected to the bipolar transistor for pull-down. A low power consumption, high performance, and a reduced cell size.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a bi-CMOS output circuit according to the present invention will be described below with reference to the circuit shown in FIG. As shown in FIG. 1, in the signal input stage, the drains and the gates of the P-channel MOS transistor P10 and the N-channel MOS transistor N10 are interconnected, and the source of the MOS transistor P10 is connected to the power supply potential VDD. The source is composed of a CMOS circuit connected to the power supply potential VSS, and the signal input terminal Din is commonly connected to the gate.

The drain node A of the CMOS circuit is connected to the base of the first bipolar transistor Q10 via a resistor R10, and the collector of the node A is connected to the power supply potential V.
The emitter is connected to the power supply potential VSS via a feedback resistor R11 and a feedback resistor R12 connected in series.

The collector of the second bipolar transistor Q11 for pull-up is connected to the power supply potential VDD, and the third bipolar transistor Q1 for pull-down is connected.
The two emitters are connected to the power supply potential VSS and are totem-pole connected between the two power supply potentials, and the signal output terminal Dout is taken out from the collector-emitter interconnection point C. Further, a PN junction diode D10 and a PN junction diode D11 are connected in series between the base of the first bipolar transistor Q10 and the signal output terminal Dout, with the anode being the base side and the cathode being the signal output terminal side, The signal input terminal Din is connected to the base of the second bipolar transistor Q11.

Hereinafter, the bi-CMOS of the present invention having the above configuration will be described.
The operation of the output circuit will be described. First, the signal input terminal Di
When the signal input to n changes from the L level to the H level, the base of the second bipolar transistor Q11 is connected to the signal input terminal Din. The output of the output terminal Dout becomes H level.

At this time, an N-channel MOS transistor N of a CMOS circuit composed of a P-channel MOS transistor P10 and an N-channel MOS transistor N10.
10 is turned on, the P-channel MOS transistor P10 is turned off, and the output of the node A goes to the L level, so that the first bipolar transistor Q10 is turned off, and the first bipolar transistor Q10 is turned off by the feedback resistor R10.
The third bipolar transistor Q12 driven via R11 is also turned off. Therefore, at this time, the first
No DC current flows through the bipolar transistor Q10 and the third bipolar transistor Q12.

On the other hand, when the signal input to the signal input terminal Din transitions from H level to L level, the second bipolar transistor Q11 turns off, the P-channel MOS transistor P10 turns on, and the N-channel MOS transistor P10 turns on.
The channel MOS transistor N10 turns off, the output from the node A changes from the L level to the H level, the base voltage of the first bipolar transistor Q10 is raised, and the first bipolar transistor Q10 turns on.
At the same time, the base voltage of the third bipolar transistor Q12 is also raised via the feedback resistors R10 and R11 and turned on, drawing current from the output terminal Dout and pulling down the output voltage.

At this time, the base voltage VB of the first bipolar transistor Q10 is VBE (Q12) ≒ VB
Since E (Q10) = Vf (base-emitter voltage), VB = VBE (Q12) × (1 + R11 / R1
2) + VBE (Q10) = (2 + R11 / R12) × V
f. As is apparent from this equation, the base-emitter voltage VBE (Q1) of the third bipolar transistor Q12 is connected to the VB via the feedback resistors R11 and R12.
2) has been returned.

At this time, when the output voltage Vout from the output terminal Dout becomes (R11 / R12) × Vf, V
B−Vout = (2 + R11 / R12) × Vf− (R1
1 / R12) × Vf = 2 × Vf, so that the PN junction diode D10 and the PN junction diode D11 are turned on, and the collector current of the third bipolar transistor Q12 passes through the PN junction diode D10 and the PN junction diode D11. As a result, the voltage at the node B is reduced, and as a result, the base voltage of the third bipolar transistor Q12 is reduced to reduce the collector current of the third bipolar transistor Q12.

As described above, the output voltage Vout becomes V
out = (R11 / R12) × Vf to be in a steady state. Therefore, since the L level of the output voltage can be controlled by (R11 / R12), the third bipolar transistor Q12 at the time of L level output can be used without connecting a Schottky barrier diode between the base and collector of the third bipolar transistor Q12. Can be avoided. Here, as for the feedback resistor, as shown in the figure, two resistors are connected in series and an interconnection point is drawn out as a voltage dividing terminal. However, the feedback resistor is configured by a potentiometer and the voltage dividing terminal is drawn out, so that the output voltage is reduced. Can be changed.

The current consumption at this time is the sum of Iq10 flowing through the first bipolar transistor Q10 and the current Iq12 flowing through the third bipolar transistor Q12. Here, ignoring the on-resistance of the P-channel MOS transistor P10, Iq10 = Vf / R12, Iq12 = {VDD- (2 + R11 / R12) × Vf}.
/ R10, as is apparent from the sum of these, as compared with the circuit shown in FIG. 2, the current flowing through the constant current source Ig of the differential pair transistor is unnecessary, which leads to lower power consumption.

Further, since it is not necessary to connect the pull-up transistor to the Darlington connection, the power supply voltage is 3.3V.
And the like, and a low-voltage operation can be performed. Further, the first bipolar transistor Q1 other than the second bipolar transistor Q11 and the third bipolar transistor Q12
0, MOS transistor P10, MOS transistor N
10, since a large current does not flow through the PN junction diode D10 and the PN junction diode D11, it can be realized by a small-sized element. Further, the bipolar transistor is an MO.
Since the current driving capability is higher than that of the S transistor, it can be realized with a smaller cell size than when a MOS transistor is used in the output stage.

[0020]

The present invention eliminates the need for a Darlington connection of a pull-up bipolar transistor.
Operation at low voltage becomes possible.

[Brief description of the drawings]

FIG. 1 is a bi-CMOS output circuit of the present invention.

FIG. 2 shows a conventional T with Schottky barrier diode.
This is a TL output circuit.

FIG. 3 is a conventional TTL output circuit without a Schottky barrier diode.

FIG. 4 is a conventional CMOS output circuit.

[Explanation of symbols]

P10, N10 ··· CMOS circuit Q10, Q11, Q
12. Bipolar transistors D10, D11 ...
PN junction diode R11, R12 feedback resistor

Claims (4)

[Claims] 1. A CMOS circuit having a signal input terminal, a signal output terminal, and a gate interconnection point connected to the signal input terminal, and a CMOS circuit having a drain interconnection point of the CMOS circuit connected to the signal output terminal. Its base is connected via a diode, its collector is connected to one of the two power supply potentials, and its emitter is connected via a feedback resistor having a voltage dividing terminal to the other of the two power supply potentials. A first connected bipolar transistor and 2
A second bipolar transistor and a third bipolar transistor connected to each other at a totem pole between two power supply potentials and having a connection point connected to the signal output terminal; and the signal input terminal is connected to the second bipolar transistor. A bi-CMOS output circuit, wherein the output terminal is connected to a base, and a voltage dividing terminal of the feedback resistor is connected to a base of the third bipolar transistor. 2. The bi-CMOS output circuit according to claim 1, wherein said diode is a PN junction diode. 3. The bi-CM according to claim 1, wherein a drain interconnection point of said CMOS circuit and a base of said first bipolar transistor are connected via a resistor.
OS output circuit. 4. The bi-CMOS output circuit according to claim 1, wherein said feedback resistor is a resistor having a variable voltage dividing ratio.