JPH11101860A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for suppressing the fluctuation of the output timing of a timing generator even when the operation rate of the timing generator is changed. SOLUTION: This semiconductor device is provided with the plural timing generators 1, an arithmetic control circuit 2, a register 3 and a pseudo operation circuit 4 and the respective timing generators 1 are provided with an edge control circuit 10, plural flip-flops 11, an OR circuit 12, a variable delay element 13 and a multiplexer 14. The arithmetic control circuit 2 calculates the operation rate of the timing generator 1 based on the output signals of the edge control circuit 10 and operates the pseudo operation circuit 4 so as to compensate the calculated operation rate. Thus, regardless of the operation rate of the timing generator 1, the operation rate of the entire device is set to be almost fixed at all times and the fluctuation of the output timing of the timing generator 1 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a timing generator for outputting a predetermined timing signal, and mainly relates to a tester for semiconductor testing, a waveform generating circuit, and the like.

[0002]

2. Description of the Related Art A part of a semiconductor device, for example, a semiconductor test device has a timing generator for outputting a predetermined timing signal. Generally, a variable delay element capable of adjusting a delay amount is provided inside the timing generator.

[0003] This type of variable delay circuit is often formed of CMOS in order to reduce power consumption. However, not only external factors such as fluctuations in ambient temperature and power supply voltage, but also self-heating and self-power consumption are required. A problem that the amount of delay changes due to factors inside the LSI such as electric motors has been pointed out.
As a method for solving this problem, the following first to third methods have been proposed.

[0004] The first technique is to maintain the ambient temperature at a constant temperature by a cooling / heating device. The second technique is to form a heater circuit having a CMOS configuration capable of controlling an output current on a semiconductor substrate, monitor a chip temperature, and offset a temperature change by an output current of the heater circuit.

In a third method, a CMOS heater circuit capable of controlling an output current is formed on a semiconductor substrate, the chip temperature is set higher than a normal use state, and the operating speed and the external environment are controlled. This is intended to prevent a change in the chip temperature due to the change from affecting the propagation delay time.

A fourth technique is to use a variable delay circuit with a PL
By making the L circuit configuration, the timing of the ring oscillator of the internal circuit and the reference clock whose temperature dependency of the propagation delay time input from the outside is extremely small are matched.
This is to suppress the fluctuation of the propagation delay time.

[0007]

However, the above-described first to fourth methods have the following problems. The cooling / heating device used in the first method is costly and requires maintenance, and when the cooling / heating device is provided separately from the variable delay circuit, a new mounting space is required, and the system needs to be installed. Miniaturization becomes difficult.

In the second method, the configuration of a control circuit for feeding back the result of monitoring the chip temperature to the heater circuit becomes complicated. That is, it is necessary to convert the result of monitoring the chip temperature into data for controlling the heater circuit. Also, if a sudden temperature change occurs,
A large feedback is applied from the control circuit to the heater circuit, and a certain period of time is required until the chip temperature is stabilized, during which time temperature compensation cannot be performed.

In the third method, since the heater circuit is formed on the semiconductor substrate, the power consumption increases, and the inherent characteristics of CMOS, which is low power consumption, cannot be utilized. In addition, it is necessary to use a chip package having a low resistance, and further, it is necessary to consider the structure of the cooling system, so that the cost increases.

In the fourth method, since the propagation delay time is controlled by the charge pump in the PLL circuit, jitter is easily generated, and cannot be used in a system requiring high accuracy. Also, since it is necessary to match the frequency of the reference clock with the operating frequency of the internal logic circuit that needs to suppress fluctuations in the propagation delay time, a plurality of PLL circuits must be built in, and the circuit scale is reduced. It is likely to be large and accuracy will be poor.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and an object of the present invention is to provide a semiconductor device in which the output timing of the timing generator does not change even when the operation rate of the timing generator changes. To provide.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor device having a timing generator for outputting a predetermined timing signal.
An operation rate calculation circuit that calculates the operation rate of the timing generator, the operation rate calculated by the operation rate calculation circuit, and an operation rate of the timing generator according to a difference between a predetermined value and a predetermined value. And an operation rate compensation circuit for compensating.

The operating rate compensation circuit compensates the operating rate of the timing generator so that, for example, the operating rate of the entire apparatus is substantially constant regardless of the operating rate of the timing generator.

Further, the timing generator includes, for example,
Outputs a test signal for performing a performance test of the device under test,
The operation rate compensation circuit compensates the operation rate of the timing generator so that the timing of the test signal is substantially constant regardless of the operation rate of the timing generator.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the timing generator outputs a test signal for performing a performance test of the device under test, and outputs a signal indicating occurrence of an edge, An edge control circuit that outputs a signal indicating the amount of delay of the edge, and a variable delay element that delays the signal indicating the occurrence of the edge by a delay amount corresponding to the signal indicating the amount of delay of the edge, A rate calculation circuit that calculates an operation rate of the timing generator based on the signal indicating the edge occurrence and the signal indicating the delay amount of the edge; and the operation rate compensation circuit calculates a delay amount due to the variable delay element. The operation rate of the timing generator is compensated such that is substantially constant regardless of the operation rate of the timing generator.

According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor device according to the first aspect further includes an edge detection circuit for detecting an edge included in an output signal of the device under test, and the operation rate calculation circuit includes the edge detection circuit. The operation rate of the timing generator is calculated based on the edge detected in step (1).

The operating rate compensating circuit includes, for example, a current source capable of adjusting a flowing current according to the difference.

According to a fourth aspect of the present invention, there is provided a semiconductor device including a plurality of timing generators for outputting a predetermined timing signal, wherein the semiconductor device includes an operation rate calculating circuit for calculating an operation rate of each of the plurality of timing generators. In accordance with a difference between the operation rate calculated by the operation rate calculation circuit and a predetermined value, the operation rate of the entire apparatus is always substantially constant regardless of the operation rate of each of the timing generators. Then, an unused timing generator among the plurality of timing generators is operated.

According to a fifth aspect of the present invention, there is provided a semiconductor device comprising: a timing generator for outputting a predetermined timing signal; and an operation rate calculating circuit for calculating an operation rate of the timing generator. The device includes an edge control circuit that outputs a signal indicating an edge occurrence and a signal indicating an edge delay amount, a variable delay element that can adjust the delay amount,
The operation rate calculation circuit calculates the operation rate of the timing generator based on the signal indicating the edge occurrence and the signal indicating the delay amount of the edge, and according to the calculated operation rate. Inputting pseudo data to the variable delay element,
Delay by the delay amount according to the operation rate.

The invention described in claim 1 will be described with reference to, for example, FIG. 1. "Operation rate operation circuit" corresponds to an operation control circuit, and "operation rate compensation circuit" corresponds to a pseudo operation circuit.

The invention described in claim 2 will be described with reference to, for example, FIG. 1. The “edge control circuit” corresponds to the edge control circuit 10, the “variable control element” corresponds to the variable control element 13,
Each corresponds.

The invention described in claim 5 will be described with reference to, for example, FIG. 3. “Edge detection circuit” corresponds to the edge detection circuit 21.

The invention according to claim 6 will be described with reference to, for example, FIG. 4. The “current source” corresponds to the current source 32.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device to which the present invention is applied will be specifically described with reference to the drawings. Hereinafter, a semiconductor device that performs a performance test on a device under test will be described as an example of the semiconductor device.

[First Embodiment] FIG. 1 is a block diagram of a first embodiment of a semiconductor device according to the present invention. The semiconductor device of the present embodiment includes a waveform generation circuit that outputs a test signal for testing a device under test, and a tester that detects an output signal of the device under test and determines whether the device under test is good or bad. FIG. 1 shows the configuration of the waveform generation circuit.

The waveform generating circuit shown in FIG. 1 includes a plurality of timing generators 1, an operation control circuit 2, a register 3, and a pseudo operation circuit 4. Each timing generator 1 includes an edge control circuit 10, The circuit includes a plurality of flip-flops 11, an OR circuit 12, a variable delay element 13, and a multiplexer 14.

The edge control circuit 10 receives timing edge information relating to a test pattern and a waveform mode, and address information indicating a storage location of the information. Based on the information, the edge control circuit 10 determines whether an edge has occurred. And a signal indicating the edge delay amount. These output signals are input to the OR circuit 12 or the multiplexer 14 after the timing is adjusted by the flip-flop 11.

The arithmetic and control circuit 2 includes an edge control circuit 10
The operation rate of each timing generator 1 is calculated based on the signal indicating the occurrence of the edge and the signal indicating the amount of delay of the edge, which are output from the controller 3. The value is compared with the value to detect the difference. The specified value preset in the register 3 is uniquely determined from a performance specification unique to the semiconductor device. As an example, data indicating the maximum operation rate of the timing generator is set as the specified value.

The simulated operation circuit 4 is composed of a plurality of circuit elements such as inverters and gates as shown in FIG. 2, for example, and the operation rate of each circuit element is determined according to the difference detected by the arithmetic and control circuit 2. Switch. For example, when the operation rate of the edge control circuit 10 is low, the operation rate of the pseudo operation circuit 4 is increased. Conversely, when the operation rate of the edge control circuit 10 is high, the operation rate of the pseudo operation circuit 4 is reduced. .

Here, the operation rate of the timing generator 1 is
Generally, it depends on the number of gate stages, and the total of the number of edges generated within a predetermined time and the delay time of the edges has a certain relationship with the current consumption. Therefore, by compensating this operation rate by the pseudo operation circuit 4, the temperature of the semiconductor device and the power supply voltage are always kept constant.

The pseudo operation circuit 4 shown in FIGS.
The configuration is not necessarily essential, and the variable delay circuit 13 may be used as a substitute for the pseudo operation circuit 4. That is, after the operation rate of the edge is calculated by the arithmetic and control circuit 2, the pseudo edge generation signal and the pseudo delay amount are calculated based on the calculated operation rate, and the pseudo edge generation signal is transmitted to the OR circuit 12 and the pseudo delay is generated. The quantity is input to multiplexer 14. Further, the output of the edge control circuit 10 is stopped, and at the same time, the selection direction of the multiplexer 14 is switched. Thus, the pseudo edge generation signal is input to the input terminal of the variable delay circuit 13 via the OR circuit 12, and the pseudo delay amount is input to the control terminal of the variable delay element 13 via the multiplexer 14, and the variable delay circuit 13 The operation is performed based on the pseudo edge generation signal and the pseudo delay amount, and the operation rate of the timing generator 1 can be compensated. In this case, the pseudo operation circuit 4 becomes unnecessary.

Further, among the plurality of timing generators 1,
When some of the timing generators 1 are in an unused state, the unused timing generators 1 may be operated in accordance with the operation rates calculated by the arithmetic and control circuit 2 to compensate the operation rates. Good. Also in this case, the pseudo operation circuit 4 can be omitted.

Conversely, when the operation rate is compensated only by the pseudo operation circuit 4 shown in FIG. 1, the OR circuit 12 and the multiplexer 14 shown in FIG. 1 can be omitted.

As described above, in the first embodiment, the operation rate of each timing generator 1 is calculated based on the signal output from the edge control circuit 10, and the pseudo operation circuit 4 is operated in accordance with the calculated operation rate. And the variable delay element 13 are operated, so that the operation rate of the entire waveform generation circuit can be made substantially constant at all times, and the output timing of the variable delay element 13 is made to substantially match even if the temperature or the power supply voltage changes. And a highly accurate waveform generation circuit can be obtained. Further, since the operation of the pseudo operation circuit 4 is immediately switched based on the calculation result of the operation rate, real-time control becomes possible.

Although FIG. 1 shows an example in which a plurality of timing generators 1 are provided, the number of timing generators 1 is one.
Only one.

[Second Embodiment] FIG. 3 is a block diagram showing a configuration of a tester for detecting a signal output from a device under test. The tester of FIG. 3 includes an edge detection circuit 21 that detects an edge included in a sense signal output from a device under test, a variable delay element 13, an operation control circuit 2,
A register 3 and a pseudo operation circuit 4 are provided. Except for the edge detection circuit 21, the configuration is the same as that of FIG.

Unlike the waveform generating circuit shown in FIG.
The reason why the edge detection circuit 21 is provided in the tester is that the sense signal output from the device under test depends on the quality of the device under test and the signal applied from the waveform generation circuit to the device under test, This is because the timing of the sense signal cannot be accurately detected unless the edge included in the sense signal is detected.

The operation control circuit 2 calculates the operation rate of the tester based on the number of edges of the sense signal included in the predetermined period, and sets the pseudo operation circuit 4 according to the calculated operation rate.
To work.

Thus, as in the first embodiment, the operation rate of the entire tester can be always kept constant, and the variation in the delay amount of the variable delay element 13 in the tester can be suppressed.

The tester shown in FIG. 3 may be formed on a semiconductor substrate integrally with the waveform generating circuit shown in FIG. 1, or may be provided separately from the waveform generating circuit.

[Third Embodiment] As shown in FIG. 2, the pseudo operation circuit 4 is preferably constituted by a circuit capable of predicting and controlling the operation rate.
The circuit scale may be too large. in this case,
As shown in FIG. 4, a D / A converter 31 that converts the operation rate data calculated by the arithmetic and control circuit 2 into an analog signal,
A current source 32 capable of adjusting the output current based on the output of the D / A converter 31 may be provided, and the operating rate may be compensated by the current source 32.

Thus, the configuration of the pseudo operation circuit 4 can be simplified. Further, since the current source 32 in FIG. 4 can control the flowing current in an analog (continuous) manner, the operation rate is compensated in smaller units than in the case of a random circuit as shown in FIG. Can be.

In each of the embodiments described above, the semiconductor test apparatus for performing the performance test of the device under test has been described. However, the present invention is widely applicable to various semiconductor devices having a timing generator.

Further, a plurality of specified values are stored in the register 3 shown in FIGS. 1 and 3 in advance, so that variations in the semiconductor manufacturing process and changes in the temperature and power supply voltage due to the usage environment of the semiconductor device are prevented. Accordingly, an optimal prescribed value may be selected.

[0045]

As described in detail above, according to the present invention, the operation rate of the timing generator is calculated and the operation rate is compensated. Variations in the output timing of the timing generator do not occur. In addition, when the operation rate is calculated, the operation rate is immediately compensated, so that real-time control becomes possible.
A highly accurate timing generator is obtained. Furthermore, since the configuration is such that the timing variation is predicted in advance and the variation is compensated for, the jitter which has been a problem when performing the conventional feedback control does not occur.
Unlike the feedback control, there is no need for a standby time until the correction control becomes effective, and the timing control can be performed easily and quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a circuit diagram illustrating an example of an internal configuration of a pseudo operation circuit.

FIG. 3 is a block diagram illustrating a configuration of a tester.

FIG. 4 is a diagram showing an example having a current source inside a pseudo operation circuit.

[Explanation of symbols]

 Reference Signs List 1 timing generator 2 operation control circuit 3 register 4 pseudo operation circuit 10 edge control circuit 11 flip-flop 12 OR circuit 13 variable delay element 14 multiplexer

Claims (5)

[Claims] 1. A semiconductor device provided with a timing generator for outputting a predetermined timing signal, wherein: an operation rate calculation circuit for calculating an operation rate of the timing generator; and the operation rate calculated by the operation rate calculation circuit. And a duty ratio compensating circuit for compensating the duty ratio of the timing generator according to a difference from a predetermined value. 2. The timing generator outputs a test signal for performing a performance test of a device under test. The timing generator outputs a signal indicating an edge occurrence and a signal indicating an edge delay amount. An edge control circuit, and a variable delay element that delays the signal indicating the occurrence of the edge by a delay amount according to the signal indicating the delay amount of the edge;
The operation rate calculation circuit calculates an operation rate of the timing generator based on the signal indicating the edge occurrence and a signal indicating the delay amount of the edge, and the operation rate compensation circuit includes: 2. The semiconductor device according to claim 1, wherein the operation rate of the timing generator is compensated so that a delay amount caused by the variable delay element is substantially constant regardless of the operation rate of the timing generator. An edge detection circuit for detecting an edge included in an output signal of the device under test, wherein the operation rate calculation circuit operates based on the edge detected by the edge detection circuit. The semiconductor device according to claim 1, wherein is calculated. 4. A semiconductor device comprising a plurality of timing generators for outputting a predetermined timing signal, comprising: an operation rate calculation circuit for calculating an operation rate of each of the plurality of timing generators; In accordance with the difference between the operation rate calculated by the operation rate calculation circuit and a predetermined value, the plurality of the plurality of timing generators are controlled so that the rate is substantially constant regardless of the operation rate of each of the timing generators. A semiconductor device characterized by operating an unused timing generator among the timing generators. 5. A semiconductor device comprising: a timing generator for outputting a predetermined timing signal; and an operation rate calculation circuit for calculating an operation rate of the timing generator, wherein the timing generator includes an edge generator. And an edge control circuit that outputs a signal indicating the amount of delay of the edge; and a variable delay element that can adjust the amount of delay. Based on the signal indicating the amount of delay of the edge, the operation rate of the timing generator is calculated, pseudo data corresponding to the calculated operation rate is input to the variable delay element, and the operation rate is determined according to the operation rate. A semiconductor device characterized by delaying by a delay amount.