JPH1098010A - Formation of compound semiconductor low-contact resistance electrode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable forming a low-resistance ohmic contact, which is suitable for processing of a ultrahigh-speed semiconductor device using a compound semiconductor by a method, wherein the concentration of impurities, which are doped to a semiconductor contact layer coming into contact with a metal layer, is set at a concentration of a specified value or higher and a prescribed temperature or lower in a pretreatment process, prior to a deposition of the metal film set at the deposition temperature of the metal film. SOLUTION: A TEG, an AsH3 and a DETe are used by an MLE, Te is doped to a GaAs contact layer at a substrate temperature of 325 deg.C in an ultrahigh vacuum, to grow the GaAs contact layer of an impurity concentration of 1×10<19> /cc or higher on a substrate and thereafter, an Si3 N4 film is deposited on the contact layer by a plasma CVD method in the atmosphere. After the pattern of the Si3 F4 film has been formed on the contact layer, the substrate is heated up to a prescribed temperature of 300 to 480 deg.C, such as 380 deg.C, while the AsH3 is introduced in the substrate to remove a natural oxide film. After that, the temperature of the substrate is set at a prescribed metal deposition temperature, such as 380 deg.C, and an W (CO)6 is introduced in the substrate to deposit a W metal film. Thereby, a low-resistance ohmic contact can be formed on an ultrahigh-speed III-V compound semiconductor device, having a super thin multilayer structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor contact with a low-resistance metal in a manufacturing process of a compound semiconductor device, and particularly to an ultra-high-speed ultra-high-speed multilayer structure having a high concentration and a steep concentration profile. The present invention relates to a method for forming a compound semiconductor low contact resistance electrode for forming an ohmic contact with extremely low resistance in a III-V compound semiconductor device.

[0002]

2. Description of the Related Art Compared with Si which has been widely used for high-speed semiconductor devices, III-V compound semiconductors such as GaAs and InGaAs have high electron mobility and are suitable for ultra-high-speed semiconductor devices. . recent years,
Ultra miniaturization of semiconductor devices has been promoted in order to achieve ultra-high speed, but various problems to be solved have also been derived along with this. One of those issues is a technique for forming a metal / semiconductor contact resistance electrode, a so-called ohmic electrode.

Generally, if a metal / semiconductor contact with a fixed contact resistivity, the dimensions of the semiconductor device is 1 / k times, the contact resistance is increased to ^twice k. Therefore, ultra-high speed semiconductor devices require metal / semiconductor contacts with very low contact resistivity. In addition, with the miniaturization of semiconductor devices, the semiconductor layer has an extremely thin multilayer structure having a steep concentration profile of high-concentration impurities,
The allowable range of diffusion of the electrode material metal into the semiconductor layer is limited to be short in both the vertical and horizontal directions. Au /
The alloyed ohmic contact centered on Ge has a problem that the contact resistivity is as high as 1 × 10 ⁻⁶ Ωcm ² or more, and the diffusion of metal reaches 100 nm or more due to the alloying heat treatment. For this reason, non-alloyed ohmic contacts have been developed.

When the electric conduction at the metal / semiconductor interface is based on a tunnel mechanism, the contact resistance Rc is represented by a metal / semiconductor barrier fb and a doping concentration Nd.
xp {fb / (Nd) ² }. Therefore, in order to form a low-resistance ohmic contact, high-concentration doping may be performed on the semiconductor layer near the interface or a metal having a low metal / semiconductor barrier may be used.

However, it is very difficult to obtain a metal / semiconductor interface having a low barrier height with good reproducibility. For example, in the case of n-type GaAs, the barrier height of the metal / semiconductor interface formed by a usual method is small. As is well known, due to a phenomenon called pinning, it shows a substantially constant value of about 0.8 eV. Therefore, a high concentration doping technique for the GaAs semiconductor layer is extremely important for realizing a low-resistance ohmic contact. Recent molecular layer epitaxy (hereafter,
It is described as "MLE". ) Or molecular beam epitaxy (hereinafter,
Indicated as "MBE". ) By remarkable technology development,
Doping at x10 ¹⁹ / cc or more has also become possible.
By MBE, an Si impurity was added to a surface of about 1 × 1
In the n-type GaAs layer doped with 0 ²⁰ / cc, the metal is vapor-deposited in situ immediately after the MBE is performed.
A contact resistance of 10 ^-6 Ωcm ² has been obtained (Applied Physics Letters, 1985, vol. 47, p.
26).

However, even if such a semiconductor layer containing high-concentration impurities is used, once it is exposed to air after MBE, a natural oxide film is formed on the GaAs surface, whereby the high-impurity concentration layer is oxidized and spontaneously oxidized. Because it becomes an oxide film,
The resulting contact resistivity was more than an order of magnitude higher. The method of forming a metal film in situ after growing a contact layer is excellent in minimizing contact resistance, but reduces the degree of freedom in the device fabrication process.

[0007] To obtain the thermal stability of the metal / semiconductor interface, W (tungsten), or high-melting metal such as Ti (titanium), used WN _x, WSi _x, preferred by alloys such as TiSi _x However, these metal films are generally difficult to process and require a process of forming a metal film by forming a pattern in advance, and the problem of forming a natural oxide film is inevitable.

On the other hand, as a protective film for a natural oxide film,
Low temperature growth (hereinafter referred to as “LTG”) GaAs has been proposed (Applied Physics Letters, 1).
995, 66, p1412). This is because high concentrations of S
Immediately after the MBE of the GaAs layer containing
A TG-GaAs layer is grown at a low temperature (up to 250 ° C.) at a temperature of 2 to 5 nm, and is then exposed to the atmosphere. A low-resistance metal / semiconductor contact is formed by removing a native oxide film remaining in the GaAs layer and thereafter depositing a metal film. Note that this LT
It is considered that the G-GaAs layer is amorphous, and evaporates together with the natural oxide film by heating in an ultra-high vacuum. In this LTG-GaAs, the natural oxide film layer to be removed remains in the LTG-GaAs layer and does not reach the GaAs layer containing high-concentration Si impurities. Therefore, the contact resistivity is 3 × 10 ⁻⁷ Ωcm ² at the minimum. Have been.

However, as is well known, the formation of a natural oxide film occurs in an extremely short time in the air, so that the natural chemical film cannot be completely removed by ordinary chemical treatment. Therefore, conventionally, crystal growth has been performed by heating to 500 to 600 ° C. while supplying As in an atmosphere containing no oxidizing species, for example, in an ultra-high vacuum or a hydrogen atmosphere.

[0010]

However, the temperature in removing the natural oxide film is not only too high for the ultra-high-speed device semiconductor layer having an ultra-thin multilayer structure having a steep concentration profile of high-concentration impurities as described above, This causes redistribution of impurities in the contact layer having a high impurity concentration, and cannot be applied to lowering the ohmic contact resistance. L above
The temperature of TG is extremely low at 250 ° C., and there is no problem in film formation. However, there is a problem to be solved in that natural oxide film cannot be completely removed by ordinary chemical treatment. Furthermore, there is a problem to be solved that the thickness of the natural oxide film formed by the process after MBE growth cannot be controlled, and the optimum thickness of the LTG protective film differs for each process and is not uniquely determined. . Thus, the conventional 500 to 600
In the high-temperature oxide film removal step of heating to ° C., the vicinity of the surface of the contact layer containing high-concentration impurities deteriorated, and it was difficult to obtain a good low-resistance ohmic contact with good reproducibility.

In view of the above problems, an object of the present invention is to provide a method for forming a compound semiconductor low contact resistance electrode capable of realizing a low resistance ohmic contact suitable for an ultra-high speed semiconductor device process using a compound semiconductor. Things.

[0012]

In order to achieve the above object, a method for forming a compound semiconductor low contact resistance electrode according to the present invention comprises a step of forming a predetermined semiconductor contact layer on a semiconductor substrate, and a step of forming a contact layer. A step of forming a predetermined pattern on the semiconductor substrate, and a step of forming a low contact resistance electrode by introducing a source gas onto the semiconductor substrate and depositing a predetermined metal film on the semiconductor contact layer. The impurities to be added should be 1 × 10 ¹⁹ / cc or more,
The temperature of the pre-processing step before depositing the metal film is set to a predetermined temperature in the range of 300 ° C. to 480 ° C., and the predetermined temperature of the pre-processing step or lower than the predetermined temperature is set as the metal film deposition temperature. Further, in addition to the above configuration, a configuration may be adopted in which a hydride gas as a crystal raw material of a compound semiconductor is introduced at a low pressure during a pretreatment step before depositing a metal film. Further, a configuration may be adopted in which the deposition temperature of the metal film is set to a temperature range that activates impurities in the contact layer.

With such a configuration, each process is performed at a sufficiently low temperature. Therefore, an ultra-high-speed III-V compound semiconductor device having an ultra-thin multilayer structure having a high concentration and a steep profile can be connected to an ohmic contact having an extremely low resistance. Can be formed.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, in the present embodiment, III-V
GaAs is used as a group III compound semiconductor, Te (tellurium) is used as an n-type impurity to be added, and high melting point metal W (tungsten) is used as an ohmic metal. It should be noted that the present invention
The invention can be applied to other group III-V compound semiconductors of As, and the ohmic metal may be any metal or alloy regardless of whether the impurity is n-type or p-type.

As other III-V compound semiconductors of GaAs, InGaAs, AlGaAs, GaP, InP,
There are InGaP, InGaAlP, InAsP and the like. Further, as a metal or alloy, an ultra-thin In / W two-layer structure, M
o, ultra-thin In / Mo bilayer structure, ultrathin Ti / W bilayer structure,
Ultra-thin Ti / Mo bilayer structure, ultrathin Cs / W bilayer structure, ultrathin Cs / Mo bilayer structure, ultrathin Hf / W bilayer structure, ultrathin Hf
/ Mo two-layer structure. Here, “/” indicates that it has a laminated two-layer structure.

Since the ultra-high-speed semiconductor device manufactured according to the present invention has an ultra-thin multilayer structure having a high concentration and a steep profile, the growth of the contact layer usually formed on the uppermost layer of the device structure necessarily involves a low temperature. There must be. Therefore, a molecular layer epitaxy (MLE) method most suitable for such a structure is used. Note that the present invention can be applied to other growth methods that are low-temperature growth and that allow crystal growth in units of molecular layers.

In the method of forming a compound semiconductor low contact resistance electrode of the present invention, triethyl gallium (hereinafter, referred to as “TEG”), arsine (AsH ₃ ), and diethyl tellurium (hereinafter, referred to as “DETe”) are first set by MLE. ), Doping Te at a substrate temperature of 325 ° C. in an ultra-high vacuum to grow a GaAs contact layer of 1 to 2 × 10 ¹⁹ / cc on the substrate. Plasma CV on GaAs contact layer
D is used to deposit a silicon nitride film (Si ₃ N ₄ ) at 250 ° C. In the case where the impurity density is 1 × 10 ¹⁹ / cc or more, since the tunnel conduction mechanism through tunnel injection and defects caused by the added impurities is mainly used, the impurity density of Te is determined to be 1 to 2 × 10 ¹⁹ / cc. I have.

Next, after a predetermined pattern is formed by a usual photolithography method, the device is mounted on a metal deposition apparatus. This metal deposition apparatus may be an apparatus having the same configuration as the MLE. While introducing AsH ₃ at a pressure of 1 × 10 ⁻³ Torr, the substrate is heated to a predetermined temperature of 300 ° C. to 480 ° C., for example, 380 ° C., and held for 30 minutes to remove a natural oxide film. Thereafter, a predetermined metal deposition temperature, for example, 38
Set to 0 ° C and use tungsten hexacarbonyl (W (C
O) ₆ ) is introduced at a pressure of 20 mTorr,
Angstrom thick W metal is deposited. Here, in order to form a semiconductor low contact resistance electrode, the deposition temperature of the metal film is preferably equal to or lower than the natural oxide film removal temperature, and the deposition time is 10 to 3 times.
It takes about 0 minutes.

The deposition temperature of the metal film is set so that the impurity profile of the added impurity in the contact layer is not substantially rearranged in order to obtain a low-resistance metal-semiconductor contact. Needs to be a low temperature that does not substantially change
It is necessary to keep the temperature below 0 ° C.

In the present invention, the optimum doping temperature at which a desired high-density addition and a steep impurity distribution profile can be obtained is 325 ° C. Optimally, the surface treatment is performed at a temperature at which no defects are introduced due to a change or a stoichiometric composition of the surface being shifted.

Further, the activation of the added impurity atoms makes the thickness of the depletion layer at the metal-semiconductor contact interface extremely thin and improves the tunnel conduction mechanism. A temperature at which the dopant is activated below the temperature, for example, 380 ° C. is preferred.

In this embodiment, the heat treatment is performed in AsH _{3 to} remove the natural oxide film. However, the introduction of AsH ₃ prevents the scattering of As from the contact layer surface and suppresses the formation of a high resistance layer. When the introduction pressure of AsH ₃ is low, the effect of preventing the scattering of As is small, and in order to sufficiently prevent the scattering of As, the introduction pressure is desirably set to 1 × 10 ⁻⁴ Torr. As scattered is prevented, in addition to introducing the AsH ₃ is hydrogen gases crystalline material, it may be introduced As ₂ or As _4.

This is because Ga is used as a III-V compound semiconductor.
This is the case where As is used. In the case of InP, heat treatment is performed while introducing PH ₃ . That is, such a III-V
It is desirable to remove the natural oxide film in a temperature range of 300 ° C. to 480 ° C. while introducing a hydrogenation gas or a crystal raw material gas of a crystal raw material of the group III compound semiconductor at a low pressure. In such a temperature range, the dissociation of the high vapor pressure component element is not remarkable, the impurity profile of the contact layer or the device structure does not substantially change, and the surface reaction of AsH ₃ or PH ₃ substantially proceeds. I do.

The method of forming the compound semiconductor low contact resistance electrode configured as described above removes the natural oxide film at a sufficiently low temperature, and has an ultra-high speed III− having an ultrathin multilayer structure having a high concentration and a steep concentration profile. Group V compound semiconductor devices
Form ohmic contacts with very low resistance.

Since the contact resistance between metal and semiconductor depends on the pressure at which AsH _{3 is} introduced, at the same surface treatment temperature and metal deposition temperature, the introduction of AsH ₃ in the natural oxide film removing step is stoichiometric on the surface. It is extremely important for controlling the composition. Good control of the stoichiometric composition of the surface acts to improve the tunnel conduction mechanism at the metal-semiconductor contact interface, and can form a good low-resistance metal-semiconductor contact. Regarding the improvement of the tunnel conduction mechanism at the metal-semiconductor contact interface, controlling the stoichiometric composition of the surface involves controlling the formation of a specific level near the metal-semiconductor contact interface or the position control of impurity substitution in the high-purity impurity-added layer near the interface. Make it optimal. Therefore, the formation of a specific level enhances the tunnel conduction mechanism via the level, and the control of the impurity substitution position leads to the improvement of the tunnel conduction mechanism by reducing the thickness of the ultra-thin tunnel barrier layer at the interface. , A very good low contact resistance electrode is formed.

[0026]

EXAMPLE Next, in order to measure the contact resistance in the method of forming a compound semiconductor low contact resistance electrode of the present invention, a second metal layer was deposited after removing the native oxide film in the configuration of the above embodiment. Aluminum (Al) was vapor-deposited, and the metal was etched by a photolithography method to form a metal electrode. The contact resistance of the sample thus manufactured was measured.

FIG. 1 shows the dependence of the contact resistivity on the temperature of the AsH ₃ treatment for removing the native oxide film. As clearly shown in FIG. 1, at AsH ₃ treatment temperature of 480 ° C. or less, the contact resistivity sharply decreases, and at 400 ° C. or less, the contact resistivity reproducibly becomes about 5
x10 ⁻⁷ Ω · cm ² . At temperatures above 480 ° C,
Although the natural oxide film can be efficiently removed, the diffusion of impurities in GaAs becomes active and the device structure is destroyed. In a heat treatment experiment of a contact layer doped with Te at a high concentration, it was also found that the carrier concentration sharply decreased at 480 ° C. or higher, and the AsH ₃ treatment for removing a natural oxide film at 480 ° C. or higher was inappropriate.

It should be noted that, without performing the AsH ₃ treatment for removing the native oxide film, Au /
When the same measurement was performed with Ti metal deposited, the contact resistivity was about 3 × 10 ⁻⁶ Ω · cm ² . Also,
In order to remove the natural oxide film, the AsH ₃ treatment temperature is set to 30.
When grown at 0 ° C. or lower, the natural oxide film on the GaAs surface does not desorb, and the contact resistivity increases.
Therefore, if the pretreatment temperature before depositing the metal film is in the range of 300 ° C. to 480 ° C. while introducing AsH ₃ , which is a hydrogenation gas containing the crystal raw material of the III-V compound semiconductor, the contact resistance is extremely low. Can be formed.

[0029]

As will be understood from the above description, in the method of forming a compound semiconductor low contact resistance electrode according to the present invention, since each process is performed at a sufficiently low temperature, an extremely thin multilayer having a high concentration and a steep profile is obtained. It has an effect that an ohmic contact with extremely low resistance can be formed for an ultrahigh-speed compound semiconductor device having a structure.

[Brief description of the drawings]

FIG. 1 shows A for removing a natural oxide film having a contact resistivity.
is a graph showing the sH ₃ treatment temperature dependence.

Claims (3)

[Claims] A step of forming a predetermined semiconductor contact layer on the semiconductor substrate; a step of forming a predetermined pattern on the semiconductor substrate on which the contact layer is formed; and introducing a source gas onto the semiconductor substrate. Depositing a predetermined metal film, comprising: depositing the metal film with an impurity added to the semiconductor contact layer in contact with the metal film at 1 × 10 ¹⁹ / cc or more. The temperature of the previous pretreatment process is 300 ° C
A predetermined temperature in the range of from about 480 ° C. to 480 ° C., and a predetermined temperature in the pretreatment step or a temperature lower than the predetermined temperature is a deposition temperature of the metal film. 2. The compound semiconductor low contact resistance electrode according to claim 1, wherein a hydrogenation gas as a crystal raw material of the compound semiconductor is introduced at a low pressure during a pretreatment step before depositing the metal film. Forming method. 3. The method according to claim 1, wherein the deposition temperature of the metal film is within a temperature range for activating impurities in the contact layer.