JPH1097226A - Liquid crystal driver and liquid crystal display device provided with this device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of a liquid crystal display device. SOLUTION: A liquid crystal driver is provided with a common driver, a segment driver incorporating a frame memory, a display control circuit, a VRAM(video RAM) for storing display data, a low frequency oscillation circuit 270 being a generation source of a low frequency timing signal for liquid crystal display, and a high frequency oscillation circuit 250 being a generation source of a high frequency timing signal for transmitting display data. In this case, the high frequency oscillation circuit 250 supplies a clock source required for writing display data in the VRAM, reading out display data from the VRAM, and transmission-processing display data to the segment driver. To reduce power consumption, intermittent operation of the high frequency oscillation circuit 250 is controlled by a timing control circuit 240, when display data is rewritten or a display rewriting command is written from a MPU (microprocessor unit) 100, oscillation is started, when transferring display data to the segment drive is finished, the circuit 250 is automatically stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a liquid crystal driving device used for a liquid crystal display device.

[0002]

2. Description of the Related Art In a simple matrix type liquid crystal display device, which is an example of a flat panel display, a micro-display is used.
From the processor unit (hereinafter also referred to as “MPU”) side, an LCD module (liquid crystal display (hereinafter also referred to as “liquid crystal display module”)), a scan electrode driving circuit (hereinafter referred to as “MPU”)
As a method of transferring display data to a module including a signal driver circuit (hereinafter, also referred to as a “segment driver”) and the like, a matrix-type liquid crystal display element module controller (hereinafter, referred to as a “liquid crystal controller”) Is also typical. In this method, like a display device using a CRT, a liquid crystal controller connected to a system bus reads display data from a video RAM (VRAM) storing display data and transfers the read data to a liquid crystal display module with a high frequency clock. To perform a display refresh operation. In recent years, the same system has been proposed which incorporates a frame memory as a segment driver, reads display data inside the segment driver with a low-frequency clock, and refreshes the display without constantly transferring display data from a liquid crystal controller. I have. In this case, the MPU
As long as a display rewrite request does not occur, a series of operations relating to the transfer of display data to the segment driver can be stopped, so that the power consumption of the entire liquid crystal display module can be reduced.

[0003]

However, in the above-mentioned conventional example, although the power consumption at the time of display refresh is reduced, the high-frequency oscillation circuit itself needs to continuously oscillate. It is not possible to suppress power consumption in the part. As a workaround for this, it is conceivable to use a basic clock of the MPU as an external clock without using a high-frequency oscillation circuit inside the liquid crystal controller. Time tends to decrease. Specifically, for example, an MPU employed in a small portable device or the like has a plurality of clock sources (high speed,
(Low speed), and a high-speed clock is used for communication, and a low-speed clock is used for standby.
In such a case, it cannot be used as a clock for the display data transfer processing of the liquid crystal controller.

In view of the above-mentioned problems, the present invention improves the oscillation circuit of the liquid crystal controller and the transfer method of display data. It is to provide a liquid crystal display device.

[0005]

According to a first aspect of the present invention, there is provided a liquid crystal driving apparatus comprising: a scanning electrode driving circuit; a signal electrode driving circuit including a frame memory; a display control circuit; and storage means for storing display data. The display control circuit includes a low-frequency oscillation circuit that is a source of a low-frequency timing signal for liquid crystal display and a high-frequency oscillation circuit that is a source of a high-frequency timing signal for display data transfer, and the high-frequency oscillation circuit is a display. An intermittent operation is performed according to a data processing command, and a display rewriting operation is performed according to an output state of the high-frequency oscillation circuit.

According to a second aspect of the present invention, in the liquid crystal driving device according to the first aspect, there is provided means for monitoring an output state of the high-frequency oscillation circuit performing the intermittent operation, and display is performed according to an output of the monitoring means. Perform a rewrite operation.

According to a third aspect of the present invention, in the liquid crystal driving device according to the first or second aspect, the operation of writing display data to the storage means and the operation of reading display data from the storage means are performed by the following. When the high-frequency oscillation circuit is stopped is controlled based on the command signal,
When the high-frequency oscillation circuit is operating stably, it is controlled based on the output signal of the high-frequency oscillation circuit.

According to a fourth aspect of the present invention, in the liquid crystal driving device according to the third aspect, there is provided a means for identifying whether the high-frequency oscillation circuit is in the oscillation state or the oscillation stop state, and the identification means is provided. The control signal source for writing the display data to the storage means is selected in accordance with the output state of the display data.

According to a fifth aspect of the present invention, there is provided a liquid crystal display device including the liquid crystal driving device according to the third aspect and a liquid crystal display driven by the liquid crystal driving device.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

<Overview of Liquid Crystal Display Module and Liquid Crystal Controller> FIG. 2 is a block diagram of a liquid crystal display module according to the present invention. In addition, FIG. 2 also shows an MPU for explanation of the embodiment.

In FIG. 1, an MPU 100 controls the entire system including a liquid crystal display module. The control of the liquid crystal display module is performed by controlling an LCD controller (hereinafter, also referred to as “liquid crystal controller”) 200 connected to the MPU data bus of the MPU. Specifically, a command code or data for the liquid crystal controller is output on the MPU data bus, and control signals (DT / _CM and A [0:15] in the figure) are output.
The signal is transferred to the liquid crystal controller using the chip select signal _CS signal generated by the address decoder 101.

The LCD controller 200 is also called a liquid crystal controller, has a built-in low frequency oscillation circuit, and supplies a low frequency clock required for liquid crystal display (LP, Y).
D and FR). The display data transferred from the MPU is output to the VRAM data bus VD [0: 7], and the control signals (_VCS, VR / _W and _VOE) are output.
And VR using address bus signals VA [0:15].
Write to AM300. Segment driver 500
When transferring display data to -1,500-2, first, VR
Control signal for AM (_VCS, VR / _W
And _VOE) and VRAM address bus signal VA
The display data is read from the VRAM to the data bus VD [0: 7] by [0:15]. Subsequently, the display data read from the VRAM is output to the display data bus XD [0: 7], and is transferred to the segment driver using the shift clock XSCL.

Reference numeral 300 denotes a VRAM, which is storage means for storing display data transferred from the MPU via the liquid crystal controller 200. This is necessary for adjusting the handling of display data on the MPU side and the display side because the control operation of the MPU for the liquid crystal display module and the liquid crystal display operation are completely asynchronous in timing.

Numeral 400 denotes a liquid crystal display panel as a liquid crystal display. In this embodiment, the number of pixels is not limited, but for convenience of explanation, a liquid crystal display having a horizontal 320 pixel and a vertical 240 pixel called a quarter VGA. Explanation is given using a panel.

Reference numerals 500-1 and 500-2 denote segment drivers arranged in the horizontal direction of the liquid crystal display panel, and two 160-signal output drivers are used in relation to the panel size. These segment drivers output a voltage necessary for displaying on their output terminals in synchronization with YD and a horizontal synchronization signal LP (latch pulse) which are vertical synchronization signals (frame pulses) supplied from a liquid crystal controller. I do. The output voltage at that time is determined by the signal FR and the display data for inverting the polarity of the output voltage in order to prevent DC application to the liquid crystal element. The display data is output by a liquid crystal controller onto an 8-bit display data bus XD [0: 7], and is serially transferred into a segment driver by a shift clock XSCL. The horizontal pixel size is 320
Therefore, XSCL is forty shots, and display data for one line is transferred. The segment driver used here is
This is a type of driver having a frame memory for storing display data. Regarding the configuration and operation of such a segment driver with a built-in memory, the applicant has disclosed in Japanese Patent Application Laid-Open
The detailed description of the segment driver according to the present embodiment is omitted because the detailed description is given in Japanese Patent Application Laid-Open No. 130910/1991. The display data of the frame memory in the memory is read using the LP which is a low frequency clock, and the output voltage is determined. The power consumption of the display module can be reduced.

Reference numerals 600-1 and 600-2 denote common drivers arranged in the vertical direction of the liquid crystal display panel. Two common drivers which output 120 signals are used in relation to the panel size. These common drivers use the vertical synchronization signal (frame pulse) YD supplied from the liquid crystal controller as a trigger to synchronize with the horizontal synchronization signal LP (latch pulse) from the first line to generate a voltage necessary for displaying. Apply while scanning. The output voltage at that time is
It is determined by a signal FR for inverting the polarity of the output voltage in order to prevent DC application to the liquid crystal element.

Next, the internal configuration of the liquid crystal controller which is a main part of the present invention will be described. FIG. 1 is a block diagram of a liquid crystal controller 200 according to the present invention.

In the figure, thick lines represent buses for display data and the like. The signal group on the right side of the drawing is control signals to the VRAM, the segment driver, and the common driver. The dashed lines represent the control inside the liquid crystal controller, and the solid lines from the high frequency oscillation circuit 250 and the low frequency oscillation circuit 270 to the timing control circuit 240 are the clock outputs from the high frequency clock source and the low frequency clock source, respectively.

Reference numeral 210 denotes an MPU interface.
The liquid crystal controller 200 is selected by the CS signal, and M
A command code or data on the PU data bus D [0: 7] is received. At this time, the command code and the data are distinguished based on the state of the control signal DT / _CM. Specifically, when DT / _CM = "L", a command code, DT / _CM
CM = “H” and data. If the written data is a command code, the MPU interface
It analyzes the command and controls each unit to perform an operation according to the command and data to be subsequently written as a parameter of the command. If the written command is a command for transferring display data, the subsequent data is recognized as display data, and the VRA
An operation for writing to M is performed.

Reference numeral 220 denotes a bus holder, which latches display data into the bus holder at the rise of the _CS signal and transfers the display data to the VRAM according to timing control inside the liquid crystal controller.

Reference numeral 230 denotes a VRAM control circuit.
The display data is written to M and the display data is read from the VRAM. When accessing the VRAM, the chip select signal _VC for the VRAM
S, read / write control signal VR / _W, output enable signal_VOE, and address bus signal VA
[0:15]. The display data read from the VRAM is output to the LCD timing control circuit 240. At this time, the address for the VRAM is switched and output between writing (MPU processing) and reading (LCD processing). The MPU access address is given by the MPU, and the LCD access address is given by the timing control circuit 240.

Reference numeral 240 denotes a timing control circuit which generates low frequency clocks LP, YD and FR necessary for liquid crystal display based on the low frequency clock supplied from the low frequency oscillation circuit 270. Further, based on a high-frequency clock supplied from the high-frequency oscillation circuit 250, a control signal group for VRAM control and XSCL as a transfer clock for display data to the segment driver are generated. At that time, XSCL
And outputs the display data to VD [0: 7] in synchronization with the data.

Reference numeral 250 denotes a high-frequency oscillation circuit, which is a VRAM
And a clock source necessary for writing display data to the VRAM, reading display data from the VRAM, and transferring display data to the segment driver. The intermittent operation of the high-frequency oscillation circuit is controlled by a timing control circuit. When the display data is rewritten or a display rewrite command is written from the MPU, the oscillation starts, and when the display data transfer to the segment driver is completed, the oscillation starts automatically. To stop.

Reference numeral 270 denotes a low-frequency oscillation circuit which outputs a clock signal as a clock source which is a source of low-frequency clocks LP, YD and FR necessary for a liquid crystal display.

<Detailed Description of Operation> First, the liquid crystal display timing will be described. FIG. 3 is a timing diagram showing the liquid crystal display timing. In the present embodiment, as described with reference to FIG. 1, a liquid crystal panel having a pixel size of 320 pixels horizontally and 240 pixels vertically is used, so one vertical period (also referred to as one frame, corresponding to one period of the YD signal) ) Has 240 horizontal periods (240 LPs). An example is shown in which the polarity inversion signal FR is inverted every frame. The enlarged view within the dotted line shows the details within the horizontal period. Since the display data is transferred from the liquid crystal controller through an 8-bit data bus, 40 XSCLs corresponding to 320 pixels in the horizontal direction are shown. When the display is not rewritten and the display data need not be transferred to the segment driver, the data buses XD [0: 7] and XSCL are fixed to “L”.

FIG. 4 is a block diagram of the low-frequency oscillation circuit, showing the oscillation circuit portion and the LP generation portion. In the figure,
Inverters 271, 272, and 273 connect an external capacitor (not shown) between OSC1 and OSC2, and a resistor between OSC1 and OSC3. When an external low frequency clock is input without performing the oscillation operation, the external low frequency clock is input to OSC1 and OSC2 and OSC2 are input.
C3 is released. 274 is a D flip-flop (hereinafter, referred to as D flip-flop)
275 is a delay circuit, 276 is an inverter, and these generate an LP pulse. DFF274
Since the VDD input of “H” level is input to the D input of the DFF 274, the output of the DFF 274 becomes “H” at the rising edge of the low-frequency clock supplied from the oscillation circuit, but passes through the delay circuit and the inverter. After DFF27
4 is reset, an LP pulse having a pulse width determined by the delay time of the delay circuit is obtained (the cycle is
It is determined by the oscillation circuit part). The other timing signals YD and FR can be generated by a simple frequency divider in the timing control circuit 240 using this LP.

FIG. 5 shows the internal configuration of the high-frequency oscillation circuit. In the figure, a NAND gate 251 and a resistor 25 are shown.
2. Crystal oscillator 253 and capacitors 254, 255
Is a high frequency clock generation circuit, and the crystal oscillator and the capacitor are usually external components. This circuit can control the start and stop of the oscillation by the CTL signal which is one input of the NAND gate 251. That is, oscillation is performed when CTL = “H”, and stopped when “L”. Inverter 256 shapes the oscillation clock and sends HCLK to timing control circuit 240.
Output as 257, 258 and 264 inverters, 259 and 260 P-channel transistors,
The capacitors 261 and 262 and the resistor 263 monitor the output of the oscillation circuit. That is, when the oscillation operation is performed, the P-channel transistor 259 is turned on when the output of the inverter 257 is “L”, and charges the capacitor 261 with the “H” potential. Next, the inverter 25
7 becomes "H", the output of the inverter 258 becomes "H".
At this time, the P-channel transistor 260 is turned on, and the charge previously charged in the capacitor 261 moves to the capacitor 262. When the oscillation is stably maintained, this operation is always repeated. Since the input terminal of the inverter 264 always maintains the “H” level, MONI = “L.” Therefore, when the oscillation is stopped, that is, MONI = “H”.
4 and 5, VDD represents a fixed potential at the “H” level. The common terminal of the capacitor in FIG.
Connected to system ground potential.

FIG. 6 is a block diagram of a display data processing system in the VRAM control circuit and the timing control circuit. FIG. 7 is a timing diagram of the operation. In the figure, blocks in the 230's are included in the VRAM control circuit 230, and blocks in the 240's are
include. MP when the high-frequency oscillation circuit is stopped
If there is a write operation of display data from U, _CS
, A write pulse generation circuit 232 generates a control signal IWR for writing to the VRAM. By the generation of this signal, a control signal and an address signal for VRAM writing are output from the VA control circuit 238, the _VCS control circuit 234, and the VR / _W control circuit 235. At this time, the display data (DATA) is already held in the bus holder 220, and when the high-frequency oscillation circuit is stopped, the display data (DATA) is
33, the data is directly transferred to the VD bus control circuit 237, and is written to the VRAM by the control signal for VRAM writing described above.

In this case, the CTL signal becomes "H" by the first write operation (first _CS) from the MPU,
The high-frequency oscillation circuit is started (see FIG. 5). When the output of the oscillation circuit is stabilized (HCLK starts), the MO shown in FIG.
The NI signal becomes "L". When the display is rewritten from the MPU, the display data is stored in the VRAM in the next frame.
And transfer it to the segment driver. The transfer of display data to the segment driver is shown in FIG.
, The transfer is started from the beginning of the current frame (after the 240th LP in FIG. 3). FIG. 7 clearly shows the determination point in the form of a signal YD '. In this manner, whether or not to transfer the display data in the next frame is determined at this timing point because the YD output to the segment driver has already sent the display data of the first line in terms of timing. (See FIG. 3). Therefore, the determination is made at a point earlier by one horizontal period than YD. FIG.
In the example of (1), since MONI is at "L" (oscillation stable state) before YD ', display data is read from the VRAM at the transition to YD', and processing of transferring the display data to the segment driver is performed. Specifically, “L” of HCLK
In the period, the VA control circuit outputs a read address for display refresh, the _VCS control circuit, and the VR / _W
Control circuit, _VOE control circuit 236,
A read process from the RAM is performed. At this time, the display data may be rewritten from the MPU. In this case, if the display data is written to the VRAM at the same timing as the state where the high-frequency oscillation circuit is stopped, the display data from the VRAM for refreshing is displayed. Since the data read operation and the write operation are asynchronous, data may collide on the VD bus and display may be disturbed. For this reason, when refreshing from the VRAM is being performed, DATA is latched at the rising edge of HCLK, put on the VD bus, and display data is written to the VRAM during the "H" period of HCLK. As a result, the write operation and the read operation to the VRAM become HC
Since the display is performed alternately using the LK, the display is not disturbed. However, the frequency of HCLK needs to be higher than the cycle time of _CS. The XD bus control circuit 241 and the XSCL control circuit 242 latch the display data on the VD bus read from the VRAM at the rise of HCLK and output it as XD. XSCL has the same phase as HCLK and is output when the display data on the XD bus is determined.

FIG. 7 shows the transition of the high-frequency oscillation circuit from the stop state to the oscillation state. The transition from the oscillation state to the stop state will be described below. That is, if the display data is not refreshed from the MPU while the display data is being refreshed in one frame, the CTL is changed to "YD '" before entering the next frame.
L "to stop the high frequency oscillation circuit.

In this embodiment, the start of the refresh operation is determined based on the monitor signal MONI output from the high-frequency oscillation circuit. However, instead of providing such a detection circuit, the CTL signal is set to "H" and then fixed. The refresh operation may be started from YD ′ after a lapse of time (time considering the oscillation rise time). The certain time in that case can be easily realized by, for example, counting LPs.

As described above, the liquid crystal controller is provided with the low frequency oscillation circuit which is the source of the low frequency timing signal for liquid crystal display and the high frequency oscillation circuit which is the source of the high frequency timing signal for display data transfer. The circuit intermittently operates in accordance with a display data processing operation from a microprocessor (MPU), and performs a display rewriting operation in accordance with an output state of the high-frequency oscillation circuit, whereby power consumption of the entire liquid crystal module is reduced.

[0033]

As described above, according to the present invention, a liquid crystal display panel, a scan electrode driving circuit (common driver),
In a liquid crystal display module including a signal electrode drive circuit with a built-in frame memory (segment driver with a built-in frame memory), a display control circuit (a liquid crystal controller), and a VRAM for storing display data, the liquid crystal controller uses A low-frequency oscillation circuit and a high-frequency oscillation circuit that is a source of a high-frequency timing signal for display data transfer, the high-frequency oscillation circuit intermittently operates according to a display data processing operation from a microprocessor (MPU); By performing the display rewriting operation in accordance with the output state of the oscillation circuit, low power consumption of the entire liquid crystal module can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a liquid crystal controller according to an embodiment of the present invention.

FIG. 2 is a block diagram of a liquid crystal module.

FIG. 3 is a timing diagram of a liquid crystal display.

FIG. 4 is a block diagram of a low-frequency oscillation circuit.

FIG. 5 is an internal circuit diagram of a high-frequency oscillation circuit.

FIG. 6 is a block diagram showing a display data processing flow.

FIG. 7 is a timing diagram of display data processing.

[Explanation of symbols]

Reference Signs List 100 microprocessor unit (MPU) 101 address decoder 200 liquid crystal controller 210 MPU interface 220 bus holder 230 VRAM control circuit 231 D flip-flop 232 write pulse generation circuit 233 selector 234 _VCS control circuit 235 VR / _W control circuit 236 _VOE control circuit 237 VD bus Control circuit 238 VA control circuit 240 Timing control circuit 241 XD bus control circuit 242 XSCL control circuit 250 High-frequency oscillation circuit 251 NAND gate 252 Resistance 253 Crystal oscillator 254 Capacitor 255 Capacitor 256 Inverter 257 Inverter 258 Inverter 259 P-channel transistor 260 P-channel transistor 261 Capacitor 262 Capacitor 2 3 Resistor 264 Inverter 270 Low frequency oscillation circuit 271 Inverter 272 Inverter 273 Inverter 274 D flip-flop 275 Delay circuit 276 Inverter 300 Video RAM (VRAM) 400 LCD panel 500-1 Segment driver with built-in frame memory 500-2 Segment driver with built-in frame memory 600 -1 common driver 600-2 common driver D [0: 7] MPU data bus A [0:15] MPU address bus DT / _CM data / command identification signal _CS LCD controller chip select signal VD [0: 7] VRAM data bus _VCS VRAM chip select signal _VOE VRAM output enable signal VR / _W VRAM read / write control signal VA [0: 1 ] VRAM address bus signal XD [0: 7] display data bus XSCL display data transfer shift clock LP horizontal synchronization signal (latch pulse) YD vertical synchronization signal (frame signal) FR polarity inversion signal OSC1 low frequency oscillation circuit terminal OSC2 low frequency oscillation Circuit terminal OSC3 Low frequency oscillation circuit terminal LPOUT Low frequency oscillation circuit output CTL High frequency oscillation circuit control input HCLK High frequency oscillation circuit output MONI High frequency oscillation circuit output monitor DATA Display data in bus holder SEL Selector control input IWR Write clock pulse

Claims (5)

[Claims] A scanning electrode driving circuit; a signal electrode driving circuit including a frame memory; a display control circuit; and storage means for storing display data. A high-frequency oscillation circuit that is a source of a signal and a high-frequency oscillation circuit that is a source of a high-frequency timing signal for display data transfer, wherein the high-frequency oscillation circuit operates intermittently according to a display data processing command, A liquid crystal driving device which performs a display rewriting operation according to an output state. 2. A liquid crystal driving device according to claim 1, further comprising means for monitoring an output state of said high-frequency oscillation circuit performing said intermittent operation, and performing a display rewriting operation in accordance with an output of said monitoring means. Liquid crystal drive. 3. The liquid crystal driving device according to claim 1, wherein the operation of writing display data to the storage means and the operation of reading display data from the storage means are performed when the high-frequency oscillation circuit is stopped. When the high frequency oscillation circuit is operating stably, it is controlled based on the output signal of the high frequency oscillation circuit. apparatus. 4. A liquid crystal driving device according to claim 3, further comprising means for identifying whether said high-frequency oscillation circuit is in an oscillation state or an oscillation stop state, and said storage means is provided in accordance with an output state of said identification means. A liquid crystal driving device for selecting a control signal source for writing display data to the means. 5. A liquid crystal display device comprising: the liquid crystal driving device according to claim 3; and a liquid crystal display driven by the liquid crystal driving device.