JPH1096892A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an image reversible, in an LCD integrated with a driver using p-SiTFT, by making a shift register left and right bidirectional. SOLUTION: An adjusting display pixel DP, in the number of lines not less than those superimposed of the output of each level in a horizontal shift register 1, is provided at both ends continuously from a display pixel PX, correspondingly to which the number of the output level S/R of the horizontal shift register 1 is made an odd number. The shift direction is changed right/left by merely switching left and right the supply end of a start pulse to the horizontal shift register 1, and the distortion affecting the pixel signal voltage is equalized between the center and the end part of the display by the two drain lines conducted through a sampling gate SP and a video data line VD, so that the display quality is homogenized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (TFT) using a polycrystalline semiconductor layer.
r) are arranged in a matrix on the display unit and are also arranged to form a gate array on the periphery, so that a drive circuit-integrated liquid crystal display device (LC
In particular, the present invention relates to an LCD in which the operation direction of a drive circuit unit is freely changed to enhance versatility.

[0002]

2. Description of the Related Art LCDs have advantages such as small size, thin shape, and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a TFT as a switching element can perform static driving with a duty ratio of 100% in principle in a multiplex manner, and is used for a large-screen, high-definition moving image display.

In recent years, by using polycrystalline (poly) silicon (p-Si) as a channel layer of a TFT,
An LCD integrated with a driving circuit in which a matrix display section and a peripheral driving circuit section are formed on the same substrate has been developed. Generally, p-Si has a higher mobility than amorphous silicon (a-Si). Therefore, the size of the TFT is reduced, and high definition is realized. Further, since miniaturization by the gate self-aligned structure and speeding-up by reduction of the parasitic capacitance are achieved, the CMOS comprising the n-ch TFT and the p-ch TFT is realized.
By forming the transistor, a high-speed driver circuit can be formed. As described above, by integrally forming the drive circuit portion and the matrix display portion on the same substrate, reduction in manufacturing cost and downsizing of the LCD module can be realized.

FIG. 6 is a block diagram showing the structure of the LCD. The central matrix circuit is a display unit. A gate line (GL) as a scanning line and a drain line (DL) as a signal line are arranged horizontally and vertically, and a TFT is provided at the intersection thereof.
(SE) is formed. One electrode of a pixel capacitance (LC) for driving a liquid crystal and one electrode of an auxiliary capacitance (SC) for holding a charge are connected to the TFT (SE). Pixel capacitance (L
The other electrode of C) is formed entirely on another substrate facing the liquid crystal layer. That is, in the pixel capacitance (LC), a liquid crystal and a common electrode are partitioned by a display electrode, and a TFT (SE) is connected to the liquid crystal and the common electrode to form a display pixel.

A drain driver (D) mainly comprising a shift register and a sampling circuit is provided around the display section.
D) and a gate driver (GD) mainly composed of a shift register. These gate driver (GD) and drain driver (DD) are TF
T CMOS
Like (SE), they are formed integrally on the same substrate using p-Si.

A drain driver (DD) is driven by a horizontal shift register and each stage output of the horizontal shift register.
It consists of a transfer gate for sampling whose N / OFF is controlled. One terminal of the sampling gate
A video data line is connected, and an original picture signal created in an external integrated circuit is supplied. The other terminal is connected to a drain line (DL). The horizontal shift register has a horizontal clock signal HCLK.
And its inverted clock signal * HCLK and horizontal start pulse HST are supplied to the vertical shift register, and the vertical clock signal VCLK and its inverted clock signal * VCLK are supplied to the vertical shift register.
And a vertical start pulse VST. The horizontal shift register and the vertical shift register are started at the same timing. Then, a pixel signal voltage matching one point specified in a matrix is sampled and supplied to each drain line (DL), and the gate line (G
The pixel capacitance (LC) is charged through the TFT (SE) that is turned on during the selection of L).

[0007]

The three Ls of R, G and B
In a projector in which a CD is installed together with a lens and a reflector to constitute a predetermined optical system, and an image projected on a screen is enlarged, images projected by each LCD must match. Had to be restricted. In other words, an arrangement is required to match the vertical and horizontal directions of the image, which reduces the degree of freedom of the installation mode of the LCD. Further, in order to secure the degree of freedom of the installation mode of the LCD, different LCDs must be manufactured in accordance with the LCD arrangement method. In order to reduce the manufacturing cost by small-scale, high-volume production, the display data writing position must be vertically and symmetrically reversible.

The shift register has an output stage composed of a clocked inverter for data shift and an inverter connected in series and a clocked inverter connected in antiparallel to the inverter, and is supplied to the clock inverter for data shift. The polarity of the shift clock is reversed for each stage. That is, the clock signal and the inverted clock signal are 1
It is supplied alternately for each stage.

Therefore, when the horizontal shift register has a left-right bidirectional shift direction, if the shift clocks of the left end stage and the right end stage of the shift register are different between the clock signal CK and the inverted clock signal * CK, the start is performed. There is a problem that the shift clock that matches the pulse is different and the shift operation does not start because the start pulse is not taken in either the left or the right.

As a configuration for compensating for a speed shortage due to signal distortion due to a high resistance of a p-SiTFT logic gate, a configuration in which the output of a horizontal shift register is made longer than two clocks or a plurality of horizontal shift registers are provided. A configuration in which a margin is provided for the clock frequency is employed. In this case, a plurality of sampling gates connected to the same video data line are turned on between adjacent or neighboring several columns.
Because of the time period, a state occurs in which a plurality of drain lines (DL) are connected via these sampling gates and video data lines. The original image signal is sampled at the moment when the sampling gate is turned off, and supplied to each drain line (DL) as a pixel signal voltage. At this time, immediately before the sampling gate is turned off, a plurality of signals including the sampling gate are turned off. Are turned on, and a plurality of drain lines (D) connected to these via a video data line.
L) is the parasitic capacitance. Then, at the edge of the shift clock at which the sampling gate is turned off, if the sampling gates corresponding to the columns several columns ahead are turned on at the same time, the charge of the parasitic capacitance including the drain line (DL) is accordingly caused. For moving,
Instantaneous signal distortion occurs. That is, at the moment when the sampling gate is turned off, a signal charge is supplied to the drain line (DL) located several columns ahead, so that the signal voltage applied to the drain line (DL) is momentarily distorted. Such distortion at the time of sampling the original image signal is as follows.
In the center of the display, video data lines and O
Since the number of drain lines (DL) connected via the N sampling gates is always the same, it is written to each pixel as a pixel signal voltage including a certain distortion, which causes display unevenness. There is no. However, at the end of the display unit, the sampling gate connected to the same video data line as the sampling gate in the next several columns does not turn ON, and the same signal distortion as in the center may be applied to the pixel signal voltage. Absent. Therefore, a difference occurs in the pixel signal voltage between the central portion and the end portion, resulting in a problem that the contrast ratio and the luminance are different, and the display becomes uneven.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and a plurality of gate lines and a plurality of gate lines are provided on a display portion on one of opposing surfaces of a pair of electrode substrates which are arranged opposite to each other with a liquid crystal interposed therebetween. Drain lines are arranged crossing each other,
At each of these intersections, a display pixel including a first group of thin film transistors using a polycrystalline semiconductor and display electrodes for driving a liquid crystal connected to the first group of thin film transistors is formed and arranged in a matrix. And a second group of thin-film transistors using the same polycrystalline semiconductor as the first group of thin-film transistors are arranged on the periphery of the facing surface, and a vertical shift for sequentially applying a scanning signal voltage to each of the gate lines. A gate driver comprising a register and a sampling gate for sampling a pixel signal voltage corresponding to each of the drain lines from an original image signal supplied from the outside, and a horizontal shift for sequentially turning on the sampling gate to sample the pixel signal voltage In a liquid crystal display device comprising a drain driver comprising a register, The horizontal shift register is a bidirectional shift register that can be switched leftward / rightward, and has at least an output stage to which a start pulse is supplied in a rightward shift and an output to which a start pulse is supplied in a leftward shift. The number of output stages between the stages is odd, and adjustment display pixels corresponding to the number of output stages of the horizontal shift register are additionally arranged on both left and right sides of the display unit.

As a result, since the clock signals of the same phase are supplied to the left and right shift clocks of the horizontal shift register, only the start pulse supply stage is switched between left and right, so that the right / left bidirectional shift is performed. A register is obtained. In particular, the number of columns of the display pixels for adjustment additionally arranged at one end of the display pixels is determined by the number of output stages at which the outputs of the horizontal shift registers are simultaneously at the high level and the outputs of the same stages of the shift registers. The configuration is equal to or more than the product of the number of sampling gates to be controlled.

Thus, at the end of the effective display section,
Similar to the central portion, the display is uniformly affected by the peripheral display pixels, so that uniform display quality can be obtained over the entire effective display area. In particular, the rightward start pulse of the horizontal shift register includes an output stage associated with the adjustment display pixel such that the total number of stages with the output stage associated with the display pixel is odd. Also, the start pulse supplied to the left end stage not included in the horizontal shift register in the left direction is adjusted so that the total number of stages with the number of output stages associated with the display pixel becomes an odd number. Are supplied to the right end stage that includes or does not include the output stage associated with.

Thus, even when the number of columns of the adjustment display pixels to be added increases, the time occupied by the adjustment display pixels in the horizontal scanning period is shortened, and the scanning period of the effective display section is saved. You.

[0015]

FIG. 1 shows a configuration of a drain driver according to a first embodiment of the present invention. In the center of the figure, each output stage (S / R) is a horizontal shift register (1) composed of a clocked inverter and an inverter connected in series, and a clocked inverter connected in anti-parallel to the inverter. The output of the stage (S / R) controls the on / off of each transfer gate (2). Also, each sampling transfer gate (2) has:
Video data lines (VD) are commonly supplied,
The output of each sampling gate (2) is supplied to the drain line and sent to each column of the matrix display section (3) at the bottom of the figure. The pixel signal voltage to be supplied to each display pixel (PX) for the row selected by applying the scanning signal to the display unit (3) is converted into a video data line (VD) as an original image signal created by an external integrated circuit. Supplied to The original image signal is controlled by the shift operation of the horizontal shift register (1), and the sampling gate (2) turned on in sequence.
As a result, the data is sampled and held at the timing assigned to each column in each horizontal scanning period, and is supplied to each display pixel (PX) as a pixel signal voltage corresponding to each display pixel specified in a matrix. In each output stage (S / R) of the horizontal shift register (1), the shift operation is controlled by the clock signal CK and the inverted clock signal * CK every other stage, and the charge stabilizing operation is performed by the inverted clock signal * Controlled by CK and clock signal CK.

In the present embodiment, the horizontal shift register (1) is a bidirectional shift register capable of switching the shift direction to both left and right directions. Further, several rows of display pixels for adjustment (DP) are provided at both ends of the matrix display section. During a rightward shift, a start pulse (STR) is supplied to the left end of the horizontal shift register (1). Then, at the left end stage, the clock signal CK matches this start pulse (STR), and the right shift operation is started. On the other hand, when shifting leftward, the start pulse (STL) is supplied to the right end of the horizontal shift register (1), and the left shift operation is started when the clock signal CK matches this. In this embodiment mode, the display pixel (P
The number of output stages of the horizontal shift register (1) associated with X) is an even number, but two output stages (S / R) are added to the left end and three output stages are added to the right end. Adjustment display pixels (DP) are additionally arranged in two columns at the left end and three columns at the right end of the display unit, and the total number of stages is odd. These adjustment display pixels (DP) are pixels for which no display is performed, and are covered by, for example, a light shielding layer formed on the counter substrate side.

FIG. 2 is a timing chart of the operation of the horizontal shift register (1). The clock signal CK, which is the shift clock, and the inverted clock signal * CK have opposite polarities. The start pulse ST is supplied so as to match the clock signal, and the shift operation is started. In the first stage, the half clock period during which the clock signal CK matching the start pulse ST becomes high and the next 1
/ 2 clock period, a high level is output (OUT
1). In the second stage, a high level is output during a ク ロ ッ ク clock period during which the inverted clock signal * CK goes high following the clock signal CK and a ク ロ ッ ク clock period following this (OUT2). In other words, the adjacent stages output a high level overlapping by 1/2 clock period.

Each stage output (OUT1,... OUTn,.
) Turns on each sampling gate, and supplies the original image signal voltage at the moment when these sampling gates (2) are turned off to each drain line as a pixel signal voltage. Therefore, in the present embodiment, the two sampling gates (2) are always ON, and these sampling gates (2) and the two drain lines are conductively connected via the video data line (VD). It is in a state of being left. Therefore, for the n-th stage, the clock signal CK
At the instant T when the sampling gate (2) is turned off at the rising edge of (inverted clock signal * CK), the sampling gate (2) of the (n + 2) th stage, which is two stages ahead
Turns ON. At this time, in a state where the parasitic capacitance is generated by the drain line which is conductively connected via the sampling gate (2) of the nth and (n + 1) th stages and the video data line (VD), the sampling gate of the nth stage ( 2) is turned off, and the (n + 2) -th sampling gate (2)
Is turned on, the original image signal is momentarily distorted and sampled. Such distortion of the pixel signal voltage is as follows.
At the center of the display unit, the sampling gate (2) is substantially constant at the end of the display unit at the moment when the sampling gate (2) is turned off, and at the same time, several steps later at the end of the display unit. Therefore, there was no distortion of the pixel signal voltage. For this reason, the contrast ratio of the two rows at the end of the display unit is different from that of the center part, which causes a problem of display unevenness.

In the present embodiment, in order to solve such a problem, as shown in FIG. 1, two or more output stages (S / R) are provided at both ends of a horizontal shift register, and the output stages are associated with the output stages. Two or more columns of adjustment display pixels (DP) are provided at both ends of the display pixel (PX). Thereby, the display pixel (PX)
At the moment when the sampling gate (2) is turned off, the sampling gate (2) two steps ahead of the sampling gate (2) is turned on, so that a constant distortion is applied to the pixel signal voltage as in the center portion, A screen with a uniform display quality can be obtained over the entire display area.

In this embodiment, the horizontal shift register (1) is a bidirectional shift register. In the case of rightward shift, the start pulse (STR) is supplied to the leftmost output stage of the shift register (1). , The shift operation is started in accordance with the clock signal CK. However, the first two stages,
That is, for one clock, the pixel signal voltage is adjusted to the adjustment pixel (D
P) and no display is performed. Then, from the subsequent third stage, a pixel signal voltage is supplied to the display pixel (PX), and normal display is performed. The last three stages are also display pixels for adjustment (DP), and no display is performed. That is, the left two columns and the right three columns are non-display areas.

In the left direction, the start pulse (ST
L) is supplied to the rightmost output stage of the shift register (1), and the shift operation is started in accordance with the clock signal.
At this time, the pixel signal voltage is supplied to the adjustment display pixel (DP) for the first three stages, that is, one clock half, and the display is not performed, and the normal display is performed from the subsequent fourth stage. In the last two stages, the pixel signal voltage is similarly adjusted for the display pixel (DP).
And no display is provided. That is, in each case, the two columns on the left and the three columns on the right are the adjustment display pixels (DP).
This is an area where no display is performed.

Here, the number of output stages (S / R) associated with the display pixels (PX) is an even number, and two stages are provided at the left end.
By providing three output stages (S / R) corresponding to the adjustment display pixels (DP) at the right end, the number of all output stages (S / R) is odd. Thus, both the left end stage and the right end stage of the horizontal shift register (1) operate by the same clock signal CK. Therefore, the shift direction of the horizontal shift register (1) can be freely switched between the left direction and the right direction only by switching the supply end of the start pulse to either the left end stage or the right end stage. At this time, the left two columns and the right three
A column is not displayed as an adjustment display pixel (DP) and is not displayed, and a middle even column between them is an effective display pixel. Therefore, at the time of the rightward shift and the leftward shift, the pixel image voltage is supplied to the display pixel (PX), and the inverted image displayed effectively is shifted by one column.

If the number of output stages of the horizontal shift register corresponding to the effective pixels is odd depending on the type of the LCD panel, two stages are added to both ends of the horizontal shift register in accordance with the gist of the present invention. In addition, by providing the adjustment pixels, it is apparent that the problems of switching of the shift direction of the horizontal shift register and display unevenness at the end of the display unit can be solved.

FIG. 3 shows a configuration of a drain driver according to a second embodiment of the present invention. In the present embodiment,
Four or more output stages (S / R) are added to both ends of the output stage (S / R) of the horizontal shift register (11) corresponding to the display pixel (PX) of the display unit (13). Corresponding display pixels (DP) of four or more columns are provided at both left and right ends of the display unit in association with each other. Further, the start pulse (STR) for the rightward shift is supplied to the fifth stage from the left end of the shift register (11), and the start pulse (STL) for the leftward shift is four pulses from the right end of the shift register (11).
It is supplied at the stage.

FIG. 4 shows a timing chart of the operation of the shift register (11). The start pulse ST is supplied corresponding to two clocks of the clock signal CK. That is, it coincides with two consecutive high periods of the clock signal CK. Therefore, each stage output (OUT1,.
OUTn,...) Output a high level every two clock periods, and four neighboring sampling gates
/ 2 clock periods.

The sampling gate (12) of the n-th stage is O
At the moment of the FF, the (n + 4) -th sampling gate (12), which is four steps ahead, is simultaneously turned on. Immediately before the (n + 4) th sampling gate is turned on, the (n + 4) -th sampling gate is turned on.
Parasitic capacitance is caused by four drain lines conductively connected to the three-stage sampling gate (12) and the video data line (VD). At time T, the n-th sampling gate (12) is turned off.
At the same time, the sampling gate (1
When 2) is turned on, the distortion of the original image signal generated at the moment when the drain line of the (n + 4) th stage becomes conductive is transmitted to the nth stage, and a certain change is added to the pixel signal voltage to be supplied to the display pixel (PX). Will be.

In this embodiment, by providing four or more columns of adjustment pixels (DP) at the end of the display unit, the same distortion as in the center is given to the four columns at the end of the effective display pixels. ,
The display quality is uniform throughout the effective display area. The horizontal shift register (11) is a bidirectional shift register. The supply end of the start pulse (STR) at the time of shifting rightward is supplied to the fifth stage from the left end. The shift operation is started. Also, a start pulse (ST
The supply end of L) is supplied to the fourth stage from the right end, and the left shift operation is started in accordance with the clock signal CK. In the present embodiment, the number of columns of display pixels (PX) is an even number, and four columns of adjustment display pixels (D
P) is provided in correspondence with the number of all output stages (S / R) of the horizontal shift register (11). Between the supply stage of the right start pulse (STR) and the supply stage of the left start pulse (STL), the number of stages including these is an odd minimum value. In other words, an output stage (S / R) to which a rightward start pulse (STR) is supplied and a leftward start pulse (SRL) are provided by adding one stage to an output stage (S / R) associated with an effective pixel. ) Are operated by shift clocks of the same polarity. Therefore, switching to the right / left shift direction can be changed only by switching the supply stage of the start pulse.

With this configuration, the horizontal period required for the invalid pixel column is reduced, the pixel signal information to be displayed is increased,
Efficient driving is performed. That is, at the time of right shift, the output is started from the fifth output stage (S / R) from the left end.
On the left end, there is no column in which the pixel signal voltage is supplied to the adjustment display pixel (DP) and becomes invalid, and on the right side,
Since the four rows of adjustment pixels (DP) are provided, even in the rightmost four rows of the effective pixels, a fixed amount of the original picture signal generated at the moment when the sampling gate (12) four rows ahead is turned on, as in the center part, is turned on. Suffer distortion. In this case, only the four columns of the right adjustment display pixels (DP) become invalid. In addition, at the time of left shift, starting from the fourth stage from the right end, the pixel signal voltage is supplied to the adjustment display pixel (DP) and becomes invalid at the beginning, that is, one column at the right, and at the end, that is, at 4 at the left. In the columns, the invalid video and horizontal periods are reduced. Further, since four columns of display pixels for adjustment (DP) are provided on the left side, the distortion of the pixel signal voltage in the four columns on the left end is also constant, and display unevenness is prevented. That is, in the present embodiment, the four columns on both the left and right sides are non-display pixels, and the pixel signal voltage is supplied to the adjustment display pixel (DP) and becomes invalid only in the four columns at the end of the rightward shift. When the image is shifted leftward, the first column at the right end and the last four columns are displayed. As a result, the inverted image displayed when the pixel signal voltage is supplied to the effective display pixel (PX) is 1 at the time of horizontal shift. Deviate by columns.

When the number of effective pixel columns is odd depending on the model, according to the gist of the present invention, the number of adjustment pixel columns to be added to the left and right sides is four, and the right start pulse and the left The output stage (S /
R) is the fifth row from the left end and the right end, respectively. In this case, there is no column that is initially invalid in any of the left and right shift directions, and the inverted image does not shift due to the switching in the left and right direction.

FIG. 5 shows a configuration of a drain driver according to a third embodiment of the present invention. In this embodiment,
This is an example in which the present invention is applied to an R, G, B color active matrix type LCD. Each output stage (S / R) has a horizontal shift register (21) having the same configuration as that of the first and second embodiments, and a sampling gate (22) whose ON / OFF is controlled by each stage output. And a display section (23) connected to an output terminal of the sampling gate (22), respectively, of a drain line (not shown) of each column. Video data lines (VDR, VDG, VDB) are R, G,
B, and the display section (23) also has a triangle arrangement in which R, G, and B are repeated every three columns, and are shifted by half a pitch for each row. Each of the sampling gates (22) corresponding to each column is connected to every three video data lines (VDR, VDG, VDB). On / off of the sampling gates corresponding to one set of R, G, B is simultaneously controlled by the output of the same output stage (S / R) of the shift register (21). The start pulse matches one clock, as in the first embodiment. Each stage output outputs a high level of one clock, and the high level output of an adjacent stage is ク ロ ッ ク clock. Period overlaps.

In this embodiment, six or more columns of display pixels for adjustment (DR, DG, DB) are provided at both ends of the display section (23), and the horizontal shift register (2) is associated with them.
The output stage (S / R) of 1) is added. The start pulse (STR) for the rightward shift and the start pulse (STL) for the leftward shift have the same meaning as in the second embodiment, and are output at the third stage from the left end and the second stage from the right end, respectively. To the stage (S / R).

The output timing of each stage of the horizontal shift register (21) is the same as in FIG. In this embodiment, three columns of R, G, and B are simultaneously sampled, and the same video data line (VDR, VDG, VD
With respect to B), the two adjacent columns are sampled simultaneously for a half clock period. Therefore, at the moment when each sampling gate (22) is turned off, the sampling gate (22) two stages ahead connected to the same video data line (VDR, VDG, VDB) is turned on. At this time, the same video data lines (VDR, VDG, VD
The adjacent drain line connected to B) is in a conductive state via each corresponding sampling gate (22) and its video data lines (VDR, VDG, VDB). Therefore, in this case, at time T, at the moment when the sampling gate (22) is turned off, the sampling gate (22) two steps ahead is turned on.
Then, the original image signal is distortedly sampled and supplied to each of the display pixels (R, G, B) as a pixel signal voltage. For this reason, in the present embodiment, six or more adjustment display pixels (DR), which are the product of three of the number of columns controlled by the same output stage and two of the number of columns sampled simultaneously in a で clock period, are used. , DG, DB), and an output stage (S / R) is added to both ends of the horizontal shift register (21) in association with this. As a result, a constant distortion is applied to the pixel signal voltage at the end of the effective display unit in any of R, G, and B, as in the center, so that the contrast ratio between the center and the end of the display unit is increased. The problem of different display unevenness can be prevented.

In the example given here, the horizontal shift register (21) has an even number of stages corresponding to the effective display pixels (PX) and is a bidirectional shift register in the right / left direction. The number of stages between the output stage (S / R) to which the rightward start pulse (STR) is supplied and the output stage (S / R) to which the leftward start pulse (STR) is supplied is determined by the number of these output stages (S / R). R) Odd number including itself. Accordingly, the output stage (S / R) to which the rightward start pulse (STR) is supplied and the leftward start pulse (ST)
Since the output stage (S / R) to which L) is supplied operates with a shift clock having the same polarity, only the output stage (S / R) for supplying the start pulse is switched between left / right,
The shift to the left is switched. Further, similarly to the second embodiment, unlike the case where the left and right start pulses are supplied to the end stage of the horizontal shift register, the non-displayed image and the horizontal period are reduced, so that a larger display can be obtained.

The structure shown in FIG. 5 shows an example in which the number of columns of the effective display section does not become an integral multiple of the three columns of R, G, and B.
Six columns on the left side and seven columns on the right side have the adjustment display pixels (D
P) is provided, and the number of output stages (S / R) of the horizontal shift register (11) is increased in a form corresponding to this.
In this case, in the rightward shift, the display pixels (PX) in the seventh column corresponding to the third stage of the horizontal shift register (21)
, Display is performed, and the pixel signal voltage is supplied to the end, that is, seven columns of the adjustment display pixels (DP) on the right side, and become invalid. When shifting leftward, the horizontal shift register (21)
The pixel signal voltage is supplied to a part of the first stage and the second stage of the first stage, that is, the adjustment display pixels (DP) of four columns on the right side and the end, that is, the adjustment display pixels (DP) of six columns on the left side. Has become. In this case, the inverted image displayed by supplying the signal voltage to the effective display pixel (PX) is one stage, that is, one set of R, G, and B by shifting the shift in the horizontal direction.
Deviate by columns.

It is not always necessary to form a switching element, a pixel capacitance, and an auxiliary capacitance in addition to the drain line for the adjustment display pixel (DP).

[0036]

As is apparent from the above description, according to the present invention, in a liquid crystal display device in which a driving circuit around a display section is integrally built, a shift register constituting a driving circuit can be bidirectionally formed with a simple configuration. In addition, by providing display pixels for adjusting the optimal number of columns at both ends of the display unit, the image is reversible on the left and right, and a uniform image with no difference in display quality between the center and the end of the display unit was gotten.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a drain driver according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the shift register according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a drain driver according to a second embodiment of the present invention.

FIG. 4 is a timing chart of a shift register according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a drain driver according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a liquid crystal display device.

[Explanation of symbols]

 1,11,21 horizontal shift register 2,12,22 sampling gate 3,13,23 display unit

Claims (3)

[Claims] A plurality of gate lines and a plurality of drain lines are arranged in a display section on one of opposing surfaces of a pair of electrode substrates opposed to each other with a liquid crystal interposed therebetween, and a polycrystalline semiconductor is provided at each of these intersections. Are formed and arranged in a matrix with display pixels for driving liquid crystal connected to the first group of thin film transistors, respectively, and are arranged in a matrix. A second group of thin film transistors using the same polycrystalline semiconductor as the first group of thin film transistors, and a gate driver including a vertical shift register for sequentially applying a scanning signal voltage to each of the gate lines; A sampling gate for sampling a pixel signal voltage corresponding to each of the drain lines from the supplied original image signal; In a liquid crystal display device having a drain driver composed of a horizontal shift register that sequentially turns on each sampling gate for ringing, the horizontal shift register can switch a shift direction between a left direction and a right direction. The number of output stages between the output stage to which a start pulse is supplied at the time of rightward shift and the output stage to which a start pulse is supplied at the time of leftward shift is an odd number; A liquid crystal display device characterized in that adjustment display pixels corresponding to the number of output stages of the horizontal shift register are additionally arranged on the left and right sides of the liquid crystal display. 2. The number of columns of adjustment display pixels additionally arranged on the left and right sides of the display unit is the same as the number of output stages at which the output of each stage of the horizontal shift register is simultaneously at a high level and the number of output stages of the shift register. 2. The liquid crystal display device according to claim 1, wherein the value is equal to or more than the product of the number of sampling gates controlled by the one-stage output. 3. The start pulse in the rightward direction of the horizontal shift register is output from the output stage associated with the adjustment display pixel such that the total number of stages including the output stage associated with the display pixel is odd. Is supplied to the left end stage that does or does not include, and the start pulse in the leftward direction of the horizontal shift register is adjusted so that the total number of stages with the number of output stages associated with the display pixels is odd. The output stage corresponding to the display pixel is supplied to the right end stage that is included or not included.
The liquid crystal display device as described in the above.