JPH1096888A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an image reversible, in an LCD integrated with a driver using p-SiTFT (Si-thin film transistor), by providing bidirectional left and right shift registers. SOLUTION: The device is such that an output stage S/R is increased which is not less than the number of the simultaneous high level stage in each stage output of the first and the second horizontal shift registers 1, 2, that the number of the first horizontal shift register 1 stage is made an odd number while that of the second horizontal shift register 2 stage is made an even number with one stage less than the odd number, and that an adjusting display pixel DP is provided corresponding to the increased stages. A clock signal HCKB supplied to the second shift register 2 and its inverted clock signal *HCKB are such that the inversion/noninversion of the polarity is controlled integrally with the switching of the shift direction of the shift registers 1, 2. Thus, a simple image inversion is made possible, and also the mutual effect of the pixel is equalized between the center and the end so that the display quality is uniformized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (TFT) using a polycrystalline semiconductor layer.
r) are arranged in a matrix on the display unit and are also arranged to form a gate array on the periphery, so that a drive circuit-integrated liquid crystal display device (LC
In particular, the present invention relates to an LCD in which the operation direction of a drive circuit unit is freely changed to enhance versatility.

[0002]

2. Description of the Related Art LCDs have advantages such as small size, thin shape, and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a TFT as a switching element can perform static driving with a duty ratio of 100% in principle in a multiplex manner, and is used for a large-screen, high-definition moving image display.

In recent years, by using polycrystalline (poly) silicon (p-Si) as a channel layer of a TFT,
An LCD integrated with a driving circuit in which a matrix display section and a peripheral driving circuit section are formed on the same substrate has been developed. Generally, p-Si has a higher mobility than amorphous silicon (a-Si). Therefore, the size of the TFT is reduced, and high definition is realized. Further, since miniaturization by the gate self-aligned structure and speeding-up by reduction of the parasitic capacitance are achieved, the CMOS comprising the n-ch TFT and the p-ch TFT is realized.
By forming the transistor, a high-speed driver circuit can be formed. As described above, by integrally forming the drive circuit portion and the matrix display portion on the same substrate, reduction in manufacturing cost and downsizing of the LCD module can be realized.

FIG. 5 is a configuration diagram of an LCD. The central matrix circuit is a display unit. A gate line (GL) serving as a scanning line and a drain line (DL) serving as a signal line are arranged and formed horizontally and vertically, and a TFT (SE) is formed at an intersection thereof. One electrode of a pixel capacitance (LC) for driving a liquid crystal and one electrode of an auxiliary capacitance (SC) for holding a charge are connected to the TFT (SE). The other electrode of the pixel capacitor (LC) is entirely formed on another substrate opposed to the liquid crystal layer. That is, the liquid crystal and the common electrode are divided by the display electrode in the pixel capacitance (LC), and T
FT (SE) is connected to form a display pixel.

A drain driver (D) mainly comprising a shift register and a sampling circuit is provided around the display section.
D) and a gate driver (GD) mainly composed of a shift register. These gate driver (GD) and drain driver (DD) are TF
T CMOS
Like (SE), they are formed integrally on the same substrate using p-Si.

A drain driver (DD) is driven by a horizontal shift register and each stage output of the horizontal shift register.
It consists of a transfer gate for sampling whose N / OFF is controlled. One terminal of the sampling gate
A video data line is connected, and an original image signal VDSG created in an external integrated circuit is supplied. Also,
The drain terminals (DL) are connected to the other terminals, respectively. The horizontal shift register receives horizontal clock signals HCKA and HCKB and their inverted clock signals * HCKA and * HCKB and a horizontal start pulse H from an external integrated circuit.
ST is supplied, and the vertical shift register is supplied with the vertical clock signal VCK, its inverted signal * VCK, and the vertical start pulse VST. The horizontal shift register and the vertical shift register are started at the same timing, and pixel signal voltages corresponding to one point designated in a matrix are sampled and each drain line (DL) is sampled.
And the pixel capacitance (LC) is charged through the TFT (SE) which is turned on during the selection of the gate line (GL).

In particular, the drain driver (DD) is composed of two series of horizontal shift registers whose shift operation is controlled by clock signals CKA and CKB whose phases are shifted from each other by 90 °, and each sampling gate has a different series every other column. Is connected to each stage. Thereby, the frequency of the horizontal shift clock can be reduced to １ ／,
Insufficient speed of the logic gate composed of the p-Si TFT is compensated.

[0008]

The three Ls of R, G and B
In a projector in which a CD is installed together with a lens and a reflector to constitute a predetermined optical system, and an image projected on a screen is enlarged, images projected by each LCD must match. Had to be restricted. In other words, an arrangement is required to match the vertical and horizontal directions of the image, which reduces the degree of freedom of the installation mode of the LCD. Further, in order to secure the degree of freedom of the installation mode of the LCD, different LCDs must be manufactured in accordance with the LCD arrangement method. In order to reduce the manufacturing cost by small-scale, high-volume production, the display data writing position must be vertically and symmetrically reversible.

The shift register is composed of a clocked inverter for data shift and an inverter connected in series at each output stage, and a clocked inverter connected in antiparallel to the inverter, and supplies the clocked inverter for data shift. The polarity of the shift clock is inverted for each stage. That is, the clock signal and the inverted clock signal are alternately supplied every other stage.

At this time, if the shift direction of the horizontal shift register is bidirectional, if the shift clocks of the left end stage and the right end stage of the shift register are different between the clock signal CK and the inverted clock signal * CK, There is a problem that the shift clock that matches the start pulse is different, and either the left or right shift operation does not start without the start pulse being captured.

As a configuration for compensating for a lack of speed due to signal distortion due to a high resistance of a logic gate composed of a p-Si TFT, a configuration in which the output of a horizontal shift register is made longer than two clocks or a plurality of horizontal shift registers are provided. A configuration in which a margin is provided for the clock frequency is employed. In this case, a plurality of sampling gates connected to the same video data line are turned on between adjacent or neighboring several columns.
Because of the time period, a state occurs in which a plurality of drain lines (DL) are connected via these sampling gates and video data lines. The original image signal is sampled at the moment when the sampling gate is turned off, and supplied to each drain line (DL) as a pixel signal voltage. At this time, immediately before the sampling gate is turned off, a plurality of signals including the sampling gate are turned off. Are turned on, and a plurality of drain lines (D) connected to these via a video data line.
L) is the parasitic capacitance. Then, at the edge of the shift clock at which the sampling gate is turned off, if the sampling gates corresponding to the columns several columns ahead are turned on at the same time, the charge of the parasitic capacitance including the drain line (DL) is accordingly caused. For moving,
Instantaneous signal distortion occurs. That is, at the moment when the sampling gate is turned off, a signal charge is supplied to the drain line (DL) located several columns ahead, so that the signal voltage applied to the drain line (DL) is momentarily distorted. Such distortion at the time of sampling the original image signal is as follows.
In the center of the display, video data lines and O
Since the number of drain lines (DL) connected via the N sampling gates is always the same, it is written to each pixel as a pixel signal voltage including a certain distortion, which causes display unevenness. There is no. However, at the end of the display unit, the sampling gate connected to the same video data line as the sampling gate is not turned on in several columns, and the same signal distortion as in the center may be applied to the pixel signal voltage. Disappears. Therefore, a difference occurs in the pixel signal voltage between the central portion and the end portion, resulting in a problem that the contrast ratio and the luminance are different, and the display becomes uneven.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and a plurality of gate lines and a plurality of gate lines are provided on a display portion on one of opposing surfaces of a pair of electrode substrates which are arranged opposite to each other with a liquid crystal interposed therebetween. Drain lines are arranged crossing each other,
At each of these intersections, a display pixel including a first group of thin film transistors using a polycrystalline semiconductor and display electrodes for driving liquid crystal connected to the first group of thin film transistors is formed and arranged in a matrix. And a second group of thin-film transistors using the same polycrystalline semiconductor as the first group of thin-film transistors are arranged on the periphery of the facing surface, and a vertical shift for sequentially applying a scanning signal voltage to each of the gate lines. A sampling gate for sampling a pixel signal voltage corresponding to each of the drain lines from a gate driver including a register and an original image signal supplied from the outside, and controlling the sampling gates for each of a plurality of sampling gates in the same sequence to sample the pixel signal voltage. A two-system horizontal shift register that sequentially turns on the sampling gate. The two series of horizontal shift registers are bidirectional shift registers capable of switching the shift direction between left and right, and the number of output stages thereof is one. In this configuration, adjustment display pixels associated with each other so as to make the output stages of the two series of horizontal shift registers differ by one stage are additionally arranged on the left and right sides of the display unit.

[0013] Thus, the clock signals of the same phase can be supplied as the shift clocks of both the left output stage and the right output stage to which the start pulses of the two series of horizontal shift registers are supplied. By simply switching the pulse supply stage between left and right, a bidirectional shift register having a simple structure that can be switched rightward / leftward can be obtained.

In particular, the number of columns of adjustment display pixels additionally arranged on both the left and right sides of the display unit is determined by the number of output stages at which the output of each stage of the horizontal shift register is simultaneously at the high level.
It is a configuration that is at least twice the product of the number of sampling gates controlled by the same stage output of the shift register. As a result, at the end of the effective display area, similarly to the central area, the same influence of the peripheral display pixels is received, so that uniform display quality can be obtained over the entire effective display area.

Particularly, in the horizontal shift register having an even number of output stages, the polarity of the horizontal clock signal for controlling the shift operation is switched integrally with the left / right switching of the shift direction of the horizontal shift register. It is. As a result, the phases of the shift clocks supplied to all the left output stages and all the right output stages to which the start pulses of the two-system horizontal shift registers are to be supplied are all the same, so that the start pulse supply stages are switched. Thus, either the rightward or leftward shift operation is started equally.

[0016]

FIG. 1 shows a configuration of a drain driver according to an embodiment of the present invention. In the upper half of the figure, each output stage (S / R) is composed of a first clocked inverter and an inverter connected in series, and a second clocked inverter connected anti-parallel to the inverter for charge stabilization. First and second two series of horizontal shift registers (1, 2). The output stage (S / R) of each series is connected to the O of the transfer gate for sampling (3) arranged.
N / OFF is controlled every other one. That is, the sampling gates (3) are alternately connected to the first horizontal shift register (1) and the second horizontal shift register (2) every two. A video data line (VD) is commonly supplied to each sampling transfer gate (3), and an output of each sampling gate (3) is supplied to a drain line. It is sent to each column of 4). A pixel signal voltage to be supplied to each display pixel (PX) for a row selected by applying a scan signal to the display unit (4) is
It is supplied to a video data line (VD) as an original image signal created by an external integrated circuit. The original image signal is sampled and held by the sampling gate (3) sequentially turned on by the shift operation of the first and second horizontal shift registers (1, 2) at the timing assigned to each column during each horizontal scanning period. Then, it is given to each display pixel (PX) as a pixel signal voltage corresponding to each display point designated in a matrix.

Each output stage (S / R) of the first and second horizontal shift registers (1, 2) has a first clocked inverter whose shift operation is controlled by a clock signal and which is connected to the inverter. A second clocked inverter connected in anti-parallel is controlled by the inverted clock signal,
Further, a clock signal and an inverted clock signal are alternately supplied for each stage. First horizontal shift register (1)
The shift operation is controlled by the first horizontal clock signal HCKA and its inverted clock signal * HCKA, and the second horizontal shift register (2) outputs the second horizontal clock signal HCKA.
The shift operation is controlled by KB and its inverted clock signal * HCKB. This first horizontal clock signal HCKA
And the second horizontal clock signal HCKB are out of phase by 90 °, and the sampling operation is alternately controlled every other stage. Therefore, the shift clock frequency determined from the required sampling frequency is The shift clock frequency to be supplied is further reduced by half.

In the present invention, each of the first and second horizontal shift registers (1, 2) is a bidirectional shift register capable of switching the shift direction to both the left direction and the right direction. The first horizontal shift register (1) has an odd number of output stages (S / R), and the second horizontal shift register (2) has one fewer output stages (S / R). The display pixels for adjustment (DP) are arranged at both ends of the display pixels (PX) in an even number and in correspondence with the display pixels (DP). Further, the polarity of the second horizontal clock HCKB and its inverted clock signal * HCKB is inverted at the time of rightward shift and at the time of leftward shift, as described later.

In particular, in this embodiment, the display pixel (PX)
In addition to the output stage of the horizontal shift register (1, 2) associated with, four or more stages are added to both ends thereof, and in correspondence with this, four or more columns of adjustment display pixels ( D
P) is an additional sequence. When shifting rightward, the horizontal start pulse is supplied to the horizontal shift register (1,
The first horizontal clock signal HCKA and the second horizontal clock signal HCKB coincide with the start pulse, and the right shift operation is started. On the other hand, at the time of the left shift, the start pulse is supplied to the right output stage (S / R) of the horizontal shift register (1, 2), and the second horizontal clock signal HCKB is supplied.
And the polarity of the inverted clock signal * HCKB is inverted,
The left shift operation is started when the first clock signal HCKA and the inverted clock signal − * HCKB of the inverted second horizontal clock signal match the start pulse.

FIG. 2 is an operation timing chart of the first and second horizontal shift registers (1, 2). The first horizontal clock signal HCKA (and its inverted clock signal * HCK
A), there is a second horizontal clock signal HCKB (and its inverted clock signal * HCKB), and a start pulse ST that commonly matches the two high-level periods of these horizontal clock signals HCKA and HCKB. Start pulse S
The first output stage (S / S1) of the first horizontal shift register (1) is provided during the half clock period in which the first horizontal clock signal HCKA matching T has become high level and the next half clock period. R) outputs a high level (OUTA).
1). Subsequently, the output stage of the first stage of the second horizontal shift register (1/2 stage) during the 1/2 clock period in which the second horizontal clock signal HCKB matching the start pulse ST has become high level and the next 1/2 clock period ( S / R) outputs a high level (OUTB1). This output OUTB1 is O
It is issued from UTA1 with a delay of 1/4 clock period. Subsequently, a high level is output from the second output stage (S / R) of the first shift register (1) with a delay of 1/2 clock period from OUTA1 (OUTA2). Hereinafter, OUTB
2, OUTA3, OUTB3,... That is, the control signals extracted in parallel from the first and second horizontal shift registers (1, 2) are output with a delay of 1/4 clock period, and the length of the high level period is 1 clock period. Therefore, together with the first shift register (1) and the second shift register (2), the four output stages (S / R) always output the high level at the same time for 1/4 clock period.

Each stage output (OUTA1, OUTB1,... O
UTAn, OUTBn,...) Turn on each sampling gate (3) and supply the original image signal voltage at the moment when these sampling gates (3) turn off to each drain line as a pixel signal voltage. In the present embodiment,
As described above, four sampling gates (3) are always on, and these sampling gates (3) are connected to the four drain lines via the video data line (VD). It has become. Therefore, for example, with respect to the n-th stage of the first shift register (1), at the instant T when the sampling gate (3) is turned off at the rising edge of the first horizontal clock signal HCKA (or its inverted clock signal * HCKA). Is the sampling gate of the (n + 2) th stage four stages ahead (3)
Turns ON. At this time, the n-th and (n + 1) -th sampling gates (3) of the first shift register (1) and the second shift register (2) and the video data line (V
D), the parasitic capacitance is generated by the drain line which is conductively connected. Therefore, at the moment when the (n + 2) -th sampling gate (3) of the first shift register (2) is opened and charge flows from the video data line (VD) to its drain line, the original picture signal is momentarily distorted, and this voltage is Sampling gate (3) is OF
F and will be sampled. Such a distortion of the pixel signal voltage is substantially constant at the center of the display unit, but conventionally, at the end of the display unit, at the moment when the sampling gate (3) is turned off, at the same time. There is no sampling gate (3) that is turned on a few steps ahead, so there is no distortion of the pixel signal voltage. In such a case, there is a problem that the display unit (4) corresponding to the four steps at the end has a different contrast ratio from the central part, resulting in display unevenness.

In the present invention, in order to solve such a problem, as shown in FIG. 1, four or more output stages (S / R) are provided at both ends of a horizontal shift register, and display pixels are associated with the output stages. (PX) at both ends of four or more columns of adjustment display pixels (D
P). Thus, at the moment when the sampling gate (3) is turned off at the end row of the display pixels (PX), the sampling gate (3) associated with the adjustment display pixel (DP) four steps ahead of this is turned on. To do
As in the case of the central portion, a certain distortion is applied to the pixel signal voltage, and a screen having a uniform display quality can be obtained over the entire display portion.
The adjustment display pixel (DP) is covered with a light shielding layer provided on the counter substrate side, and is not displayed.

FIG. 3 is a diagram showing a configuration of the LCD according to the embodiment of the present invention. A gate line (GL) and a drain line (DL) are arranged vertically and horizontally in a central display unit.
At the intersection, the switching element p-SiTF
T (SE), a pixel capacitance (LC) for driving the liquid crystal, and an auxiliary capacitance (SC) for holding electric charges are formed to constitute a display pixel. A switching element (S
E) A gate driver (GD) for driving a gate line (GL) and a drain driver (D) for driving a drain line (DL), which are composed of the same p-Si TFT as in E).
D) is arranged.

Each of the gate driver (GD) and the drain driver (DD) includes a vertical shift register and a horizontal shift register. Gate driver (G
D) is supplied with a vertical start pulse VST, a vertical clock signal VCK and its inverted clock signal * VCK,
The horizontal start pulse H is applied to the drain driver (DD).
ST and 2 according to the number of series of horizontal shift registers.
Two horizontal clock signals HCKA, HCKB and their inverted clock signals * HCKA, HCKB, and an original picture signal VDSG are supplied. In the present invention, the horizontal clock signal HCKB to be supplied to the shift register (2) having an even number of output stages and its inverted clock signal * HCK
B is supplied via a polarity switching circuit (SW) shown in FIG.

As shown in FIG. 4, the polarity switching circuit is composed of two EXOR gates (5), and a horizontal clock signal HCKB and its inverted clock signal * HCKB are supplied to one input terminal of these EXOR gates (5). And a polarity switching control signal CH to the other input terminal.
N is commonly supplied. As a result, when the polarity switching control signal CHN is set to the high level, the EXOR gate (5) to which the horizontal clock signal HCKB and its inverted clock signal * HCKB are supplied respectively outputs the horizontal clock signal HCKB 'whose polarity has been switched to the opposite polarity and its inverse. Clock signal * HCKB 'is output. Conversely, when the polarity switching control signal CHN is set to low, the horizontal clock signal HCKB
And its inverted clock signal * HCKB is output with the same polarity.

This polarity switching circuit, like the switching TFT (SE), the drain driver (DD) and the gate driver (GD), has a p-SiT
By forming the FT, it is integrally formed. The polarity switching control signal CHN is externally controlled integrally with the switching of the shift direction of the horizontal shift register (1, 2) and the switching of the start pulse supply stage at that time.

In the present invention, the horizontal shift register (1,
2) is a bidirectional shift register, the number of output stages (S / R) of one horizontal shift register (1) is odd,
The number of output stages (S / R) of the other horizontal shift register (2) is an even number smaller by one stage. And FIG.
As shown in the figure, four columns of adjustment display pixels (DP) are provided on the left side of the group of display pixels (PX) and five columns are provided on the right side of the display pixel (PX) group. S /
R) By increasing the number, the number of output stages of the first shift register (1) is odd, and the number of output stages of the second shift register (2) is even.

In the case of a rightward shift, the start pulse ST
Is the leftmost output stage (S / S) of the horizontal shift register (1, 2).
R), and as shown in FIG. 2, the shift operation is started in accordance with the first horizontal clock signal HCKA and the second HCKB. However, in the first four stages, that is, in the first two stages of the first and second shift registers (1, 2), the pixel signal voltage is supplied to the adjustment display pixel (DP), and the actual display is performed. Absent. Then, the pixel signal voltage is sampled from the subsequent fifth stage, that is, the third stage of the first shift register (1), and supplied to the display pixel (PX).
Further, the last five stages, that is, the last three stages of the first shift register (1) and the last two stages of the second shift register (2) are not displayed by the adjustment display pixels (DP). . After all, the left four columns and the right five columns of the display unit (4) corresponding to these are the non-display areas.

In the case of a left shift, the start pulse S
T is a right end output stage (S) of the horizontal shift register (1, 2).
/ R), and the inverted signal of the first horizontal clock signal HCKA and the inverted second horizontal clock signal.
* The shift operation is started in accordance with HCKB. Since the number of output stages of the second shift register (2) is even, the right end stage has the shift clock whose phase is 1 with respect to the left end stage.
It is shifted by 80 °. Therefore, since the inverted clock signal of the second horizontal clock signal HCKB is supplied to the right end of the second shift register (2), the second horizontal clock signal HCKB supplied to the second shift register (2) is provided.
The polarity of the inverted clock signal * HCKB and its polarity is switched by a polarity switching circuit (SW), so that the shift clock supplied to the right end becomes the same signal as the second horizontal clock signal HCKB. As a result, even when shifting to the left, the first horizontal clock signal HCKA supplied to the first shift register (1) is the same as the content shown in FIG.
Then, the start pulse ST matches the high level of the second horizontal clock signal HCKB supplied to the second shift register (2), and the leftward shift is started.

At this time, as in the case of the rightward shift, five stages on the right side, that is, three stages on the right side of the first shift register (1) and two stages on the right side of the second shift register (2). ,
In the columns corresponding to the four stages on the left side, that is, the two stages on the left side of the first and second shift registers (1, 2), the pixel signal voltages are supplied to the adjustment display pixels (DP) and are not displayed. Therefore, the displayed image is shifted by one column between the right shift and the left shift.

In this embodiment, the effective display pixels (P
The number of output stages of the first and second horizontal shift registers (1, 2) associated with X) is an even number. Therefore, as shown in FIG. 2, the number of output stages (S / R) of which the high level is output simultaneously is four or more, and the number of output stages (S / R) of the first shift register (1) is an odd number. In order to
Four stages are added on the left and five stages are added on the right.

When the number of output stages of the horizontal shift registers (1, 2) corresponding to the effective pixels differs from that of the present embodiment depending on the type of the LCD panel, the horizontal shift registers (1, 2) are provided in accordance with the gist of the present invention. 2) The number of additional stages can be set optimally. For example, when the number of output stages of the first and second horizontal shift registers (1, 2) is the same and odd, the number of stages to be added to make the number of output stages of the second shift register (2) even is two on each side. The number of stages for increasing the number of output stages of the first shift register (1) in an odd number is three on each side. As a result, the number of additional stages for the first and second horizontal shift registers (1, 2) is 5 and 6 on the left and right, and the number of output stages (S / R) at which a high level is output at the same time is 4 or more. Meet at least. Further, when the number of output stages of the first shift register (1) associated with the effective pixel is an odd number, and the number of output stages of the second shift register (2) is an even number smaller by one,
If two stages are added at both ends of the first and second horizontal shift registers (1, 2), exactly four stages are added on both sides. The first shift register (1) is an even number, and the second shift register (1) is an even number.
If the shift register (2) is an odd number that is one stage less than this, by adding two and three stages at both ends of the first shift register (1) and the second shift register (2), , The first shift register (1) is an odd-numbered
Shift register (2) is an even-numbered stage that is one stage smaller than that, and four and six stages are added to both sides of the first and second horizontal shift registers (1, 2), respectively. .

Further, it is not always necessary for the adjustment display pixel (DP) to form a switching element, a pixel capacitance, and an auxiliary capacitance in addition to the drain line.

[0034]

As is apparent from the above description, according to the present invention, in a liquid crystal display device in which a driving circuit around a display section is integrally built, a shift register constituting a driving circuit can be bidirectionally formed with a simple configuration. In addition, by providing display pixels for adjusting the optimal number of columns at both ends of the display unit, the image is reversible on the left and right, and a uniform image with no difference in display quality between the center and the end of the display unit was gotten.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a drain driver according to an embodiment of the present invention.

FIG. 2 is a timing chart of the shift register according to the embodiment of the present invention;

FIG. 3 is a configuration diagram of an LCD according to an embodiment of the present invention.

FIG. 4 is a block diagram of a polarity switching circuit.

FIG. 5 is a configuration diagram of a liquid crystal display device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first horizontal shift register 2 second horizontal shift register 3 sampling gate 4 display unit 5 EXOR gate

Claims (3)

[Claims] A plurality of gate lines and a plurality of drain lines are arranged in a display section on one of opposing surfaces of a pair of electrode substrates opposed to each other with a liquid crystal interposed therebetween, and a polycrystalline semiconductor is provided at each of these intersections. Are formed and arranged in a matrix with display pixels for driving liquid crystal connected to the first group of thin film transistors, respectively, and are arranged in a matrix. A second group of thin film transistors using the same polycrystalline semiconductor as the first group of thin film transistors, and a gate driver including a vertical shift register for sequentially applying a scanning signal voltage to each of the gate lines; A sampling gate for sampling a pixel signal voltage corresponding to each of the drain lines from the supplied original image signal and the sampling gate; 2. A liquid crystal display device comprising a drain driver comprising two series of horizontal shift registers for controlling each of the sampling gates sequentially in order to sample the pixel signal voltage by controlling the same for every two pixels. The series horizontal shift register is a bidirectional shift register whose shift direction can be switched leftward / rightward, and the number of output stages thereof is different by one. A liquid crystal display device further comprising adjustment display pixels associated with each other so that the number of output stages of the series horizontal shift registers is different by one. 2. The number of columns of adjustment display pixels additionally arranged on the left and right sides of the display unit is the same as the number of output stages at which the output of each stage of the horizontal shift register is simultaneously at a high level and the number of output stages of the shift register. 2. The liquid crystal display device according to claim 1, wherein the product is at least twice the product of the number of sampling gates controlled by one-stage output. 3. The horizontal shift register having an even number of output stages, wherein the polarity of a horizontal clock signal for controlling the shift operation is such that the horizontal shift register has a left / right shift direction in the shift direction of the horizontal shift register.
2. The liquid crystal display device according to claim 1, wherein the switching is performed integrally with the switching in the right direction.