JPH1093109A - Coulomb blockade element and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To integrate conductor islands at a high density and realize various coupling structural elements. SOLUTION: On a step structure, composed of insulation films 2, 3, an Si layer 4 is formed and processed into a shape, having fine wire parts 20. The forming of this layer 4 on the step structure makes the layer 4 thinner at or near the step side walls than at the fine wire parts 20, thus forming tunnel barriers having energy higher than that of the fine wire parts 20 at both sides of the fine wire parts 20, resulting in Si islands for confining charges at the fine line parts 20 held between the tunnel barriers (tunnel capacitance).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device using the Coulomb blockade phenomenon and a method for manufacturing the same.

[0002]

2. Description of the Related Art The Coulomb blockade phenomenon of electron tunneling in a small tunnel junction is a phenomenon in which a tunnel of one electron is suppressed by an increase in free energy due to charging energy accompanying the tunneling. A Coulomb blockade device utilizing such a Coulomb blockade phenomenon can control the current or charge flowing out of the device or accumulated in the device in single electron units, so that the power consumption per device is extremely low. It is characterized by its small size and extremely small device area, and is expected to achieve integration far exceeding the integration limit of existing silicon-based integrated circuits. The basic structure of this device is a single electron transistor (Single Electron Transistor).
r) and Single Electron Memory.

A conventional Coulomb blockade element mainly comprises an electrode formed on a two-dimensional electron gas formed on a heterojunction interface of a III-V group compound semiconductor or a thin single crystal silicon layer. And the semiconductor layer is confined in an island shape by the processed shape of the semiconductor layer and the like, and electrons are tunneled between the island and electrodes formed at both ends of the island. Figure 17 shows the document “Physical Review
Letter, Vol. 65, pp. 771-774, 1990 ", a bird's-eye view of the conventional Coulomb blockade element viewed from obliquely above, and FIG. 18 is an equivalent circuit diagram of the Coulomb blockade element. 71 is a substrate made of n-type GaAs, 72 is an AlGaAs layer, 73 is a GaAs layer, 7
Reference numeral 4 denotes an electrode formed on the GaAs layer 73.

In such a Coulomb blockade device, a two-dimensional electron gas is formed at the hetero interface between the AlGaAs layer 72 and the GaAs layer 73. By providing a narrowed narrow portion 75 in the horizontal direction in the electrode 74, a potential barrier is formed in this portion by a quantum size effect, and the region 76 sandwiched between these forms a conductive island for confining electric charges. Thus, the conductor island 76 and the source electrode 7
7 acts as a tunnel capacitance Cs, and a potential barrier between the conductor island 76 and the drain electrode 78 acts as a tunnel capacitance Cd.
An element having an equivalent circuit as shown in FIG.

With such a structure, it is easy to form a single Coulomb blockade element, but there is a problem that the degree of freedom is small when these elements are connected and operated. That is, the element is formed by confining the two-dimensional planar electron gas in a processed shape (the case where the upper electrode is confined to an island is considered to be equivalent to the processing of the electrode pattern), thereby forming the element. Even when a large number of devices are integrated, the arrangement is limited to a two-dimensional arrangement.

When the Coulomb blockade elements are used in an integrated manner, it is needless to say that it is important to control the capacitance between the islands based on the principle. At this time, for example, when it is desired to increase the capacitance between the islands of adjacent elements, the only way is to make the islands closer or to increase the area of the islands. When the area of the island is increased, the charging energy of the island is reduced, and the operable temperature is limited to an extremely low region close to absolute zero. Therefore, it is necessary to reduce the distance between islands, but two-dimensional distance control must rely on lithography. This naturally has a limit, and it is extremely difficult to reduce the thickness to 10 nm or less. As described above, in the two-dimensional arrangement, there is a problem that there is a limit to the type of the connection structure element to be manufactured. Further, in the case of the Coulomb blockade element shown in FIG. 17, since it is necessary to surround the conductor island 76 with the electrode 74, the arrangement of the electrodes is limited, and a plurality of conductor islands can be integrated at a high density. It is extremely disadvantageous to connect various conductive islands to produce various devices.

Further, a Coulomb blockade device for processing a two-dimensional single-crystal silicon layer and confining it in an island shape (Japanese Patent Application No. Hei.
No.-275544), an SOI wafer (SIMOX, bonded wafer, or the like) including a substrate silicon 81, a buried oxide film 82, and an upper silicon layer 83 is used. It is processed into a shape having wide electrode portions 91 and 92. Next, when this wafer is thermally oxidized, oxidation depending on the pattern shape occurs, and a phenomenon occurs in which the silicon layer 83 near the thin line portions of the electrode portions 91 and 92 becomes thinner than the silicon layer 83 of the thin line portion 90. By utilizing this phenomenon, the thinned portion is used as a tunnel capacitance, and the thin line portion 90 is changed into a small silicon island.

This method is excellent in that an extremely small silicon island connected to the electrode portions 91 and 92 via a tunnel capacitor can be automatically formed. As is clear from the structure shown in FIG. Since the structure of the electrode portions 91 and 92 must be wider than that of the thin line portion 90, there is a problem that it is difficult to integrate the islands with high density and it is also difficult to make the islands close to each other.

[0009]

As described above, in the conventional Coulomb blockade device, there is a problem that the type of the connection structure device having a plurality of conductor islands is limited, and that various devices cannot be produced. Was. Further, there is a problem that it is difficult to integrate the conductive islands at a high density, and it is also difficult to make the islands close to each other. The present invention has been made to solve the above problems, and has as its object to integrate conductive islands at a high density and to realize various connection structure elements.

[0010]

According to a first aspect of the present invention, a semiconductor is formed on a step structure formed of an insulating film having at least two steps and a flat portion sandwiched between the steps. A thin film is formed, and the thin film has a thin line portion serving as a conductor island for confining charges on a flat portion, and the film thickness on the step side wall or near the side wall is smaller than that of the thin line portion. By making the film thickness of the step side wall or the vicinity of the side wall smaller than that of the thin wire portion, a tunnel barrier having higher energy than the thin wire portion is formed at both ends of the thin wire portion, and a conductor island is formed in the thin wire portion. A thin film made of a semiconductor is formed on a step structure in which a metal film or a semiconductor film having at least two steps and a flat portion sandwiched between the steps is covered with an insulating film. The thin film has a thin line portion serving as a conductive island for confining charges on the flat portion, and the film thickness on the step side wall or near the side wall is smaller than that of the thin line portion. By making the film thickness of the step side wall or the vicinity of the side wall smaller than that of the thin wire portion, a tunnel barrier having higher energy than the thin wire portion is formed at both ends of the thin wire portion, and a conductor island is formed in the thin wire portion. Then, a three-dimensional arrangement in which the conductor island is connected to, for example, a metal film serving as an electrode or a semiconductor film serving as an electrode or a conductor island via an insulating film serving as a non-tunneling capacitor or a tunneling capacitor. Can be realized. Further, as described in claim 3, the insulating film is a tunnel insulating film.

According to another aspect of the present invention, a step of forming a step structure made of an insulating film having at least two steps and a flat portion sandwiched between the steps is formed, and the step structure is formed at or near the step side wall. Forming a thin film made of a semiconductor on a step structure so that the film thickness is thinner than a film thickness formed on a flat portion, and a shape having a thin line portion serving as a conductor island for confining charges in the thin film. And a step of processing into a. A step of forming a step structure in which a metal film or a semiconductor film having at least two steps and a flat portion sandwiched between the steps is covered with an insulating film; Forming a thin film made of a semiconductor on a step structure so that the film thickness formed on the flat portion becomes smaller than the film thickness formed on the flat portion, and a thin wire serving as a conductor island for confining electric charge in the thin film. Processing into a shape having a portion.

According to a sixth aspect of the present invention, the step side wall has an inclination. By giving the side wall an inclination in this manner, a thin film is formed on the flat portion and the side wall at a film thickness ratio substantially corresponding to the inclination. Further, as described in claim 7, a thin film is formed with anisotropic film deposition shape. Further, as described in claim 8, a thin film is formed by reacting chemical species diffused from a gas phase.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

1. Embodiment 1. FIG. 1A is a plan view of a Coulomb blockade device according to a first embodiment of the present invention, and FIG.
FIG. 2 is a sectional view taken along line AA of FIG. FIG.
(A) shows up to the point where a silicon layer described later is processed into a shape having a fine line portion. First, a manufacturing process of the Coulomb blockade device will be described. First, an insulating film 2 made of, for example, a silicon nitride film or a silicon oxide film, and an insulating film 3 are sequentially formed on a substrate 1 made of silicon or the like.

Then, the other insulating films 3 are removed by a technique such as lithography and etching while leaving the insulating film 3 having a constant width (the horizontal direction in FIG. 1). Thereby, the position P
Steps are formed at 1 and P2, respectively. The height of this step (the thickness of the insulating film 3 in the present embodiment) may be set to about 100 nm or less. If the material of the insulating film 2 and the insulating film 3 is changed and a material that is not etched in the lower insulating film 2 is used, the height of the step can be accurately controlled by the thickness of the insulating film 3. Further, a method of controlling the height of the step by the etching amount may be used. In this case, it goes without saying that the insulating film 2 and the insulating film 3 may be made of the same material.

Subsequently, a silicon layer 4 made of polycrystalline silicon or amorphous silicon is deposited on such a step structure by a chemical vapor deposition (CVD) method. At this time, silane is used as the reactive gas, and the silane gas partial pressure is set lower (or the substrate temperature is set higher to increase the reaction rate), and the film formation rate is not the surface reaction rate but the reactive gas. The silicon layer is formed on the step side wall (the side wall of the insulating film 3) and the lower part of the step near the side wall (the surface of the insulating film 2) by a method such as making the region a diffusion controlled region by diffusion or using disilane gas as a reactive gas. 4 is deposited so as to be thin.

The thickness of the silicon layer 4 below the step is:
It is necessary to make the height equal to or less than the height of the step (up to about twice). When the CVD method is used, the thickness of the silicon layer 4 becomes thinner at the lower part of the step near the side wall as well as at the side wall, and becomes the same as the thickness of the silicon layer 4 at the upper part of the step (upper surface of the insulating film 3) as the distance from the side wall increases. Therefore, it is necessary to set the deposition film thickness in consideration of this.

Next, when the silicon layer 4 is viewed from above by a technique such as lithography and etching, FIG.
Is processed so as to obtain the pattern shown in FIG. In this manner, the silicon layer 4 includes the thin line portion 20 orthogonal to the step and the thin line portion 20.
That is, it is processed into a shape having a source-side electrode portion 21 and a drain-side electrode portion 22 having a wider width (the vertical direction in FIG. 1A). The reason that the width of the electrode portions 21 and 22 is made wider than that of the thin wire portion 20 is to lower the resistance value so as to function as an electrode. It is not always necessary to increase the width of 21 and 22.

A gate insulating film 5 made of a silicon oxide film or the like is formed on such a structure, and a gate electrode 6 is formed of polysilicon or the like so as to cover the silicon layer 4 formed above the step. Lastly, like a conventional MOS transistor, a window for an electrode is opened in a part of the gate insulating film 5 on the source-side electrode part 21 and the drain-side electrode part 22, and this part is made of aluminum, tungsten, titanium or the like. A source electrode and a drain electrode are formed using metal as a lead electrode. Thus, the manufacturing process of the Coulomb blockade device is completed.

As described above, when the silicon layer 4 formed on the step side wall and the lower part of the step near the side wall becomes thinner than the silicon layer 4 formed on the upper part of the step, the conduction band of silicon in the thinned region becomes quantum. As a result, the ground energy becomes larger than that of the silicon layer above the step. Therefore, when viewed from the electrons in the silicon layer above the step, this silicon layer is sandwiched between both ends by an energy barrier, and looks like an isolated island.

FIG. 2 is an energy band diagram schematically showing this state, and FIG. 3 is an equivalent circuit diagram of the Coulomb blockade device of FIG. This Coulomb blockade element is called a single electron transistor. FIG. 2 shows only the conduction band.

The thin silicon region formed on the step side wall and under the step near the side wall has a potential barrier (tunnel barrier) as shown in FIG.
It will be 30. These two potential barriers 30 function to confine charges in the silicon layer above the step, and
It acts as a tunnel capacitance Cs (source-side capacitance) and Cd (drain-side capacitance). Thus, the silicon layer 4 formed above the step becomes a small silicon island (conductor island).
A gate electrode 6 is connected to this silicon island via a gate capacitance Cg formed by a gate insulating film 5, and a substrate (back gate electrode) 1 is connected to the silicon island via a back gate capacitance Cb formed by the insulating films 2 and 3. I have.

In such a Coulomb blockade element, when a small voltage is applied between the source-side electrode portion 21 and the drain-side electrode portion 22 to increase the gate voltage, the conductance between the source and the drain periodically increases and decreases. I do.
This operation will be described with reference to FIG. 2. Since the silicon island is surrounded by a small capacitance, the energy increase due to one electron entering the island increases, and an energy level is generated in the silicon island (see FIG. 2). 2, only two levels above and below the Coulomb gap are shown).

When the gate voltage Vg applied to the gate electrode 6 is changed, the energy level rises and falls while maintaining a constant gap due to the capacitive connection between the gate electrode 6 and the island. Then, when the source-drain voltage Vd is smaller than this Coulomb gap, if a source or drain level enters the gap, a blockade state is formed in which no current flows between the source and drain. Further, when any one of the levels of the silicon island enters between the energy levels of the source and the drain, a current flows from the source to the drain via this level.

Therefore, at a certain gate voltage, the number of electrons in the silicon island becomes stable at n (integer) due to the effect of the blockade, and no current flows (the conductance is small).
However, when the gate voltage increases, the blockade is broken and another electron can be increased. When a gate voltage is applied to this region, the number of electrons in the silicon island can take both values of n and n + 1, so one electron enters the silicon island and then exits one (the number of electrons in the island is By reciprocating between n and n + 1), a current flows and the conductance increases. In other words, when the gate voltage Vg is changed, these two states appear alternately, so that the conductance between the source and the drain pulsates.

This pulsation of conductance is blurred by thermal energy at a temperature other than absolute zero. To be able to observe conductance oscillations up to high temperatures,
That is, in order to secure a high operating temperature, the total capacity surrounding the silicon island is Ctotal (= Cg + Cs + Cd + C
b), the thermal fluctuation kT (k is Boltzmann constant) due to the temperature T is the charging energy e of one electron on the island.
It is required to be sufficiently smaller than ² / 2Ctotal. Therefore, in order to ensure a high operating temperature, it is necessary to reduce Ctotal, which is equivalent to reducing the size of the silicon island.

In order to reduce the size of the silicon island, the distance between the steps is reduced and the width of the thin line portion 20 (FIG. 1) is reduced.
It is required to reduce (a) the vertical direction) and to reduce the thickness of the thin line portion 20 (the thickness of the silicon layer 4 above the step). It is desirable that each of them is about 100 nm or less. Although the minimum value of these sizes is limited by the initial processing size, after forming the fine wire portion 20, the fine wire portion 20 is thermally oxidized to convert silicon into a silicon oxide film, thereby reducing the size of the silicon island. Can be smaller.

Embodiment 2 In the first embodiment, an example in which a CVD method is used as a method for forming the deposited silicon layer 4 has been described. The same effect can be obtained by reducing the film thickness on the step side wall or in the vicinity of the side wall. Therefore, for example, a sputtering method, a vacuum evaporation method, an ECR (Electron Cyclotron Resonance Plasma) -CVD method or the like can be used in addition to the CVD method.

FIG. 4A is a plan view of a Coulomb blockade device according to another embodiment of the present invention, and FIG. 4B is a sectional view taken along line AA of FIG. 4A. FIG. 4 (a)
Shows the portion up to the point where the silicon layer is processed into a shape having a fine line portion. First, a manufacturing process of the Coulomb blockade device will be described. First, the insulating film 2 and the insulating film 3a are sequentially formed on the substrate 1 in the same manner as in the first embodiment, and the insulating film 3a between the positions P3 and P4 and the position P5 are formed by a technique such as lithography and etching. The right insulating film 3a is removed. Thereby, the positions P3, P4, P5
Are formed respectively.

Then, on such a step structure, EC
A silicon layer 4a made of polycrystalline silicon or amorphous silicon is formed by the R-CVD method. In this method, the silane in the gas phase is activated by irradiating an ECR plasma flow of an inert gas such as argon from above the substrate with the silane gas flowing at a low pressure in the gas phase to activate the insulating film 2, A silicon layer 4a is deposited on the surface of 3a.

Therefore, unlike the ordinary CVD method,
The silicon layer 4a is deposited with anisotropic film deposition shape. That is, silicon is deposited from above the substrate 1. Since silicon is deposited in a directional manner, only a small amount of silicon is formed on the step side wall. Further, in the ECR-CVD method, if it is a flat portion, the upper portion of the step (the upper surface of the insulating film 3a) or the lower portion of the step (the upper surface of the insulating film 2).
However, since silicon is deposited to the same thickness, there is a feature that a silicon island sandwiched between tunnel barriers is formed below the step.

However, since the film is formed on the side wall under the step just below the side wall, the film is formed on the side wall. The setting of the step height and the thickness of the deposited film for obtaining an appropriate structure is determined in consideration of the thickness of the side wall and the film thickness under the step immediately below the side wall, but the deposited film thickness is generally twice or less the height of the step. Need to be

Next, when the silicon layer 4a is viewed from above by a technique such as lithography and etching, FIG.
Is processed so as to obtain the pattern shown in FIG. In this manner, the silicon layer 4a has a thin line portion 20a perpendicular to the step and a source-side electrode portion 21a and a drain-side electrode portion having a width (vertical direction in FIG. 4A) wider than the thin line portion 20a to reduce the resistance value. 22a. Finally, a gate insulating film and a gate electrode (not shown) are formed on this structure in the same manner as in the first embodiment.

FIG. 5 shows an equivalent circuit of such a Coulomb blockade element. The thin silicon regions formed by the steps at the positions P3, P4, and P5 serve as tunnel barriers as in the first embodiment, and act as tunnel capacitors Cs, Cc, and Cd, respectively. Thus, the silicon layer 4 below the step sandwiched between the steps P3 and P4
a, the silicon layer 4a above the step between the steps P4 and P5 becomes a silicon island.

A gate electrode is connected to the silicon island between P3 and P4 via a gate capacitance Cg1 made of a gate insulating film, and a back gate capacitance Cg formed by the insulating films 2, 3a.
The substrate 1 is connected via b1. Similarly, P4,
A gate electrode is connected to the silicon island between P5 via a gate capacitance Cg2 formed by a gate insulating film.
The substrate 1 is connected via the back gate capacitance Cb2 by a.

Although the present embodiment has a structure in which two silicon islands are connected in series via a tunnel capacitor, it is possible to connect any number of silicon islands by continuously forming steps. It goes without saying that you can do it. Further, in the present embodiment, the Coulomb blockade element in which the silicon layer is formed by using the ECR-CVD method has been described.
A similar structure can be obtained by other methods as long as the thin film deposition method has a similar directionality. For example, a vacuum deposition method (including a technique such as molecular beam deposition under high vacuum) or a sputtering method may be used.

By the way, in the ECR-CVD method, the sputtering method, and the vacuum evaporation method, the silicon film becomes thin only on the side wall and immediately below the side wall due to the three-dimensional effect of the step. It is equivalent to the upper part of the step. However, in the CVD method described in the first embodiment, as described above, the silicon film becomes thinner at the side wall and immediately below the side wall due to a surface reaction, a gas phase reaction, and a diffusion phenomenon. The film thickness slowly recovers as the distance from the lens increases. Therefore, the recovery of the film thickness is slow as compared with the ECR-CVD method, the sputtering method, and the vacuum evaporation method.

Thus, although a silicon island can be formed below the step by using the CVD method, it is necessary to control the film thickness more strictly. On the other hand, in the ECR-CVD method, since the direction of film deposition is extremely good, when the side wall is vertical, the silicon formed on the side wall becomes extremely thin. Therefore, although it is effective in reducing the thickness of silicon, if the controllability of the deposition shape is not kept high, the possibility of disconnection increases when the height of the step is high. In addition, disconnection occurs when a method of reducing the size of the island by thermal oxidation or the like is used. The simplest way to avoid this is to make the height of the step and the deposited film thickness the same.

Embodiment 3 FIG. 6 is a sectional view of a Coulomb blockade device showing another embodiment of the present invention. In the second embodiment, the step side wall is formed in a vertical shape. However, when the side wall is inclined as in the insulating film 3b of FIG. 6, the flat portion (the insulating film 2, 3
The silicon layer 4b is deposited on the upper surface of the silicon layer 4b) and the side walls. Therefore, there is an effect that the film thickness ratio between the silicon island or the flat portion serving as the electrode portion and the sidewall serving as the tunnel barrier can be controlled by the inclination angle of the sidewall.

Fourth Embodiment In the second embodiment, 2
Although the gate electrodes are formed so as to cover the entire silicon islands, the gate electrodes may be formed separately for each silicon island. FIG. 7A is a plan view of a Coulomb blockade device according to another embodiment of the present invention.
FIG. 8B is a sectional view taken along line AA of FIG. Note that in FIG. 7A, the gate insulating film is transparent to show the structure below the gate electrode.

In the present embodiment, a silicon layer 4b formed in the same manner as in the third embodiment is provided with a thin line portion orthogonal to the step, a source-side electrode portion 21b and a drain-side electrode portion wider than the thin line portion. 22b. On such a structure, a gate insulating film 5b is formed, a gate electrode 6a is formed so as to cover the silicon layer 4b formed below the step, and similarly, a silicon layer 4b formed above the step is covered. Then, a gate electrode 6b is formed.

In this manner, by dividing the gate electrode, the gate potential can be adjusted independently for each silicon island. FIG. 8 shows an equivalent circuit of the Coulomb blockade element. This is an element called a pump. By applying a sine wave or a triangular wave with a phase shift to the gate electrode 6a and the gate electrode 6b, a direction from the source to the drain or from the drain to the source (depending on the degree of phase shift). Has the effect of allowing electrons to flow one by one in one cycle. Therefore, a current proportional to the frequency (a current obtained by multiplying the elementary electric charge by the frequency) flows.

Embodiment 5 Furthermore, various single-electron elements can be manufactured by applying the above-described embodiment and arranging the above-described step structure two-dimensionally. FIG. 9 is a plan view of a Coulomb blockade device according to another embodiment of the present invention, and FIG. 10 is an equivalent circuit diagram of the Coulomb blockade device. FIG. 9 shows only the insulating film below the silicon layer.

In this embodiment, the insulating film 3 is formed on the insulating film 2.
c is arranged as shown in FIG. A region between the insulating film 2 and the insulating film 3c is a step sidewall formed by the insulating film 3c. Thus, the upper portion of the step formed by the upper surface of the insulating film 3c and the lower portion of the step formed by the upper surface of the insulating film 2 are arranged in a checkered pattern.

When a silicon layer (not shown) is formed on such a structure, the silicon islands formed on the upper and lower steps are arranged in an array.
In addition, since the silicon layer on the step side wall between the adjacent islands becomes thinner and functions as a tunnel barrier, an element of an equivalent circuit as shown in FIG. 10 in which the adjacent islands are connected by the tunnel capacitance Ct can be manufactured. . In FIG. 10, black circles indicate silicon islands formed above the steps, and white circles indicate silicon islands formed below the steps.

Here, the gate electrode is not formed on this element, but by forming the gate electrode at a desired position via an insulating film, the degree of freedom of the circuit configuration that can be manufactured is increased.

6. Embodiment 6 By applying the fifth embodiment, a more complicatedly connected circuit can be realized. FIG. 11 is a plan view of a Coulomb blockade device showing another embodiment of the present invention, and FIG. 12 is an equivalent circuit diagram of the Coulomb blockade device. FIG. 11 shows only the insulating film below the silicon layer.

In this embodiment, the insulating film 3 is formed on the insulating film 2.
d is formed, a part thereof (where the insulating film 2 is visible) is removed, and an insulating film 7 is formed on the insulating film 3d as shown in FIG. A region between the insulating films is a step side wall formed by the insulating films 3d and 7. As a result, the uppermost portion of the step formed by the upper surface of the insulating film 7, the middle portion of the step formed by the upper surface of the insulating film 3d, and the lowermost portion of the step formed by the upper surface of the insulating film 2 are arranged as shown in FIG.

When a silicon layer (not shown) is formed on such a structure, silicon islands formed at the top of the step, the middle of the step, and the bottom of the step are lined up, and the adjacent islands are formed. Since the silicon layer on the side wall of the step between them becomes thinner and functions as a tunnel barrier, an element of an equivalent circuit as shown in FIG. 12 in which adjacent islands are connected by tunnel capacitances Ct1 to Ct3 can be manufactured.
In FIG. 12, black circles indicate silicon islands formed at the top of the step, double circles indicate silicon islands formed at the middle of the step, and white circles indicate silicon islands formed at the bottom of the step.

As described above, each silicon island has a structure in which it is connected to six adjacent islands by a tunnel capacitance. However, since there are three types of step heights or side wall shapes, there are three types of tunnel capacitances. Will exist.
That is, there are three types: a tunnel capacitance Ct1 due to a step between the uppermost part and the middle part, a tunnel capacitance Ct2 due to a step between the middle part and the lower part, and a tunnel capacitance Ct3 due to a step between the uppermost part and the lowermost part.

The magnitude of the tunnel resistance and the capacitance can be changed depending on the height of the step and the shape of the side wall. For example, only the uppermost part and the middle part act as a tunnel capacitance, and the other parts do not tunnel (the tunnel resistance). Is equivalent to a very high tunnel capacity). Needless to say, various connection island structures can be manufactured by devising a combination of the number of steps, the arrangement of silicon islands (flat portions), and the height of the steps.

7. Embodiment 7 In the above embodiment,
Although an example of a two-dimensional arrangement of silicon islands, that is, an example in which each silicon island does not overlap in the height direction, has been described,
Next, a method for arranging silicon islands three-dimensionally will be described. FIG. 13A is a plan view of a Coulomb blockade device according to another embodiment of the present invention, and FIG.
FIG. 3A is a sectional view taken along line AA, and FIG.
It is a BB sectional view taken on the line of (a). In FIG. 13A, an insulating film below a second silicon layer described later is transparent.

In the present embodiment, first, FIG.
An insulating film 3b similar to that described above is formed. Further, the silicon layer 4b formed on the step structure is processed into a shape having a thin line portion orthogonal to the step and a source-side electrode portion 21b and a drain-side electrode portion 22b as in FIG. Subsequently, the silicon layer 4b is thinly oxidized to form a tunnel insulating film 8. The insulating film 8 can be replaced with another tunnel insulating film, for example, a silicon nitride film, and can be formed by film deposition instead of oxidation. Silicon layer 4
When b is thermally oxidized to form a tunnel insulating film, the thickness is about 1 to 3 nm.

Next, on such a structure, a second silicon layer 4c having a thin line portion orthogonal to the thin line portion of the first silicon layer 4b and a source-side electrode portion 21c and a drain-side electrode portion 22c. Fine line part and source side electrode part 21d
And a second silicon layer 4d having a drain-side electrode portion 22d.

FIG. 14 shows an equivalent circuit of such a Coulomb blockade element. Positions P6 and P by insulating film 3b
The thin region of the silicon layer 4b formed by the step of P7 and P8 serves as a tunnel barrier similarly to the above, and acts as tunnel capacitances Csd, Cc1 and Cdd, respectively.
Thus, the silicon layer 4b sandwiched between the steps P6 and P7, and the silicon layer 4b sandwiched between the steps P7 and P8
Are silicon islands 31 and 32, respectively. The substrate 1 is connected to the silicon island 31 via a back gate capacitance Cb1 formed by the insulating films 2 and 3b, and similarly, the substrate 1 is connected to the silicon island 32 via a back gate capacitance Cb2.

On the other hand, as shown in FIG. 13C, the positions P9 and P9 are formed by the thin line portion of the silicon layer 4b and the insulating film 8.
Since a step is formed in the step 10, the second step
When the silicon layer 4d is formed, the silicon layer 4d becomes thinner at or near the step side wall. Thereby, the position P
9, the thin silicon region formed by the step of P10 becomes a tunnel barrier, and the tunnel capacitances Csu2 and Cdu.
2, the silicon layer 4d sandwiched between the steps P9 and P10 becomes the silicon island 33.

Similarly, when the second silicon layer 4c is formed, the silicon layer 4c becomes thinner at or near the step side wall formed by the thin line portion of the silicon layer 4b and the insulating film 8. This thin silicon region becomes a tunnel barrier, and the tunnel capacitance C
The silicon layer 4c acts as su1 and Cdu1, and the silicon layer 4c sandwiched between them serves as a silicon island 34. The silicon islands 33 and 34 are connected by a capacitor Cc2 formed by the insulating film 8. The tunnel capacitance Ci by the insulating film 8 is provided between the islands 31 and 34 and the islands 32 and 33 which are vertically overlapped.
1 and Ci2.

A feature of the Coulomb blockade device of the present embodiment is that a silicon oxide film or a silicon nitride film having a high barrier height can be used as a tunnel barrier (insulating film 8) connecting upper and lower silicon islands. That is, the tunnel resistance can be increased even though the thickness is small. In a single electron device, the tunnel resistance is a quantum resistance (about 25 k).
Ω), the thickness of the insulating film 8 can be reduced. That is, the capacitance between the upper and lower silicon islands can be increased. This means that a large correlation can appear between the entry and exit of a single electron into each of the upper and lower islands.

In the two-dimensional arrangement shown in the above embodiment, the tunnel barrier is an increase in the base energy for electrons or holes due to the quantum confinement effect due to the thin silicon layer. The barrier height is almost proportional to one square of the thickness of the constricted portion. However, since the confinement is caused by the surrounding being surrounded by the silicon oxide film, the barrier height by the silicon oxide film itself is reduced. It cannot be exceeded. Normally, the constricted tunnel barrier is much lower than the barrier height of the silicon oxide film.

In this embodiment, the insulating film 8 formed between the upper and lower islands is used as a tunnel insulating film. However, this is an ordinary insulating film (for example, a thick insulating film that does not tunnel).
It can also be. In this case, only capacitive connection occurs between the upper and lower islands, and no direct exchange of electrons occurs between the islands (capacitances Ci1 and Ci2 are not tunnel capacitances,
Normal non-tunneling capacity).

In this embodiment, the silicon layer 4b
Silicon layers 4c and 4d were formed on the silicon islands 31 and 32 formed in such a manner as to intersect with them, and the upper and lower silicon islands were connected via a thin tunnel insulating film 8. However, the second silicon layers 4c and 4d do not necessarily need to intersect with the region where the island is formed in the silicon layer 4b. It may be formed. In this case as well, a silicon island connected to the lead portion via a tunnel capacitor or a non-tunnel capacitor can be formed in the second silicon layer according to the thickness of the insulating film between the silicon layers.

8. Embodiment 8 Next, a single-electron memory element which is another application example using the above method will be described. 15A is a plan view of a Coulomb blockade device according to another embodiment of the present invention, FIG. 15B is a sectional view taken along line AA of FIG. 15A, and FIG. Fifteen
It is a BB sectional view taken on the line of (a). In FIG. 15A, each insulating film is transparent.

In this embodiment, first, a gate electrode 9 made of a conductive material such as a semiconductor or a metal is formed on the insulating film 2. The gate electrode 9 has a shape having a terminal end (the upper side in FIG. 15A) that stops halfway. The opposite end (the lower end in FIG. 15A) is connected to an external electrode as necessary. The gate electrode 9 serves as an adjustment gate of a reading single-electron transistor (hereinafter, referred to as SET) to be described later.

The gate electrode 9 is not always necessary. When not necessary, an insulating film having a similar shape may be formed. Further, by using a conductive material such as silicon for the substrate 1, the effect of the gate electrode 9 can be substituted. In this case, when a step having a recessed insulating film 2 is formed instead of a step having an upward protrusion like the gate electrode 9, the conductive substrate 1 becomes a single-electron island of the reading SET formed thereon. It is effective only because it couples strongly and capacitively.

Next, the gate insulating film 1 is formed on the gate electrode 9.
After forming 0, a silicon layer 4e having a thin line portion orthogonal to the gate electrode 9, a source-side electrode portion 21e, and a drain-side electrode portion 22e is formed on these structures. Note that the position of the thin line portion is a position slightly away from the terminal. This is to allow a space for forming a barrier island when a second silicon layer described later is formed.

Subsequently, after a thin insulating film 11 is formed on such a structure, the silicon layer 4 having a thin line portion orthogonal to the thin line portion of the silicon layer 4e and the source electrode portion 21f is formed.
Form f. Further, after forming the gate insulating film 12, gate electrodes 13a and 13b are formed.

FIG. 16 shows an equivalent circuit of such a Coulomb blockade element. The thin region of the silicon layer 4e formed by the step between the positions P11 and P12 formed by the gate electrode 9 and the insulating film 10 becomes a tunnel barrier similarly to the above, and acts as tunnel capacitances Cst and Cdt, respectively. Thus, the silicon layer 4e sandwiched between the steps of the positions P11 and P12 becomes the silicon island 35. The silicon island 35 has a gate capacitance Cb3 formed by the gate insulating film 10.
Is connected to the gate electrode 9 via. These configurations constitute a reading SET for extracting the presence or absence of electrons in the memory island, which will be described later, as an output.
Is a single electron island of the reading SET.

On the other hand, as shown in FIG. 15C, a step is formed at the position P13 by the electrode 9, the insulating films 10 and 11, and the position P1 is formed by the silicon layer 4e and the insulating film 11.
Since a step is formed in the step 4, when the second silicon layer 4f is formed on these step structures, the silicon layer 4f becomes thinner at or near the step side wall. Thus, the thin silicon region formed by the step between the positions P13 and P14 becomes a tunnel barrier, and the tunnel capacitances Cm1 and Cm
Acts as 2.

Then, the silicon layer 4f on the right side of the position P14, that is, the silicon layer 4f formed on the silicon layer 4e to be the island 35 becomes the silicon island 36, and the position P
The silicon layer 4f sandwiched between the steps 13 and P14 becomes the silicon island 37. Here, the island 36 is used as a single-electron memory node (memory island), and the adjacent island 37 is used as a barrier island (to prevent single electrons in the memory island from leaving, or electrons enter the memory island). Is used to prevent

The gate electrode 13a is connected to the silicon island 36 via the gate capacitance Cb4 of the insulating film 12, and the gate electrode 13b is connected to the silicon island 37 similarly via the gate capacitance Cb5 of the insulating film 12. You. The gate electrode 13a is for writing or erasing a single electron to or from a memory node.
3b is for adjusting the barrier islands to work optimally. It should be noted that there is no problem when the electrodes 13a and 13b are formed of a metallic material. However, when the electrodes 13a and 13b are formed of a semiconductor, it is necessary to increase the film thickness so that a tunnel capacitance is not formed when the electrode crosses a step. There is.

The islands 35 and 36 which are vertically overlapped are
The connection is established by the capacitance Ci of the insulating film 11. Thus, a Coulomb blockade device (single-electron memory device) having an equivalent circuit as shown in FIG. 16 can be manufactured. The basic operation of this circuit is as follows. First, a voltage is applied to the barrier adjustment gate electrode 13b so that the barrier island 37 is in the Coulomb blockade state (usually in the Coulomb blockade state under zero bias, but is not in contact with the surrounding conductive material). It may deviate due to the work function difference or the influence of floating charge).

When a positive voltage is applied to the memory gate electrode 13a (the initial value is a voltage at which the potential difference from the source electrode 21f becomes substantially zero), the Coulomb blockade of the barrier island 37 is broken, and the source electrode Single electrons are supplied to the memory island 36 through the barrier island 37 from 21f. When the voltage applied to the gate electrode 13a is returned to the initial value, the barrier island 37 enters the Coulomb blockade state, so that the electrons on the memory island 36 cannot exit. Therefore, a state is reached in which a single electron is stored in the memory island 36 (writing state).

To erase this, the gate electrode 13
A negative voltage may be applied to a so that the Coulomb blockade of the barrier island 37 is broken and electrons are emitted from the memory island 36 to the source electrode 21f via the barrier island 37. Here, writing and erasing are performed by adjusting the potential of the memory gate electrode 13a, but this can also be performed by adjusting the potential of the source electrode 21f. In addition, by controlling the potential of the barrier adjustment gate electrode 13b together with the rise and fall of the potential of the gate electrode 13a or the source electrode 21f, single electron writing and erasing can be performed with a smaller potential change.

Writing to such a memory island 36,
The increase / decrease of single electrons due to erasure is caused by the memory island 36 and the capacity Ci.
Can be read as a change in the conductance of the reading SET connected via the. This reading S
The change in the conductance of the ET becomes maximum when the potential of the memory island 36 comes before and after the Coulomb blockade of the reading SET has broken. This position is for reading S
It can be adjusted by the potential of the adjustment gate electrode 9 attached to the ET. In other words, the reading SE increases or decreases due to the writing or erasing of a single electron on the memory island 36.
It may be adjusted so that the Coulomb blockade of T is broken and the conductance changes greatly.

By applying the methods 7 and 8 of the embodiment, in the conventional Coulomb blockade device shown in FIG. 19, a deposited silicon fine wire crossing the fine wire portion 90 is deposited on the fine wire portion 90. The upper silicon island connected to the silicon island formed in the thin wire portion 90 via a tunnel capacitance or a non-tunneling capacitance can be formed in the deposited silicon fine wire.

Needless to say, by forming a silicon layer on a two-dimensionally arranged silicon island via an insulating film (including a tunnel insulating film) as shown in FIGS. The result is a silicon island array connected by tunnel capacitance. Furthermore, it goes without saying that the stacking of the silicon layer via the insulating film may be repeated.

9. Embodiment 9 In the above embodiment,
The method of forming amorphous silicon or polycrystalline silicon on an insulating film and converting it to a single-electron island was described. However, when a thermal oxide film was used as an insulating film to be formed thereon, the single-crystal silicon was used. This is advantageous in that the uniformity and reproducibility of the oxide film are better.

Therefore, when depositing amorphous silicon, a point in contact with the underlying substrate silicon is formed in advance by lithography and etching, and after forming the film, the film is formed at a relatively low temperature (600 ° C. ± 150 °) for a long time. By annealing, amorphous silicon can be made into single crystal silicon. By repeating such a process over multiple layers, single-electron islands made of single-crystal silicon can be manufactured in a stacked structure. Also,
In the above embodiment, an example in which silicon is used for an island or an electrode has been described. However, another semiconductor, for example, germanium or a mixed crystal of silicon and germanium may be used.

[0078]

According to the present invention, the thickness of the step side wall or the vicinity of the side wall is made thinner than that of the thin wire portion as described in claim 1, so that a tunnel having higher energy than the thin wire portion is formed at both ends of the thin wire portion. A barrier is formed, and a conductor island is formed in the thin wire portion. Therefore, as in the conventional Coulomb blockade element, the periphery of the conductor island is surrounded by an electrode, or the width of the electrode is widened and a tunnel barrier is formed by thermal oxidation. And the conductor islands can be arbitrarily arranged. As a result, the conductor islands can be integrated at a high density, the islands can be made closer, and various elements can be easily created by connecting the conductor islands.

Further, a thin film having a thin line portion is formed on a step structure in which a metal film or a semiconductor film is covered with an insulating film, and the thickness of the step side wall or the vicinity of the side wall is reduced. By making it thinner than the thin wire part, a tunnel barrier with higher energy than the thin wire part is formed at both ends of the thin wire part,
A conductor island is formed in the thin wire portion, and the conductor island is connected to a metal film serving as an electrode or a semiconductor film serving as an electrode or a conductor island via an insulating film serving as a non-tunneling capacitor or a tunneling capacitor. Therefore, it is possible to realize a Coulomb blockade element in which the conductor island, the non-tunneling capacitor, the tunneling capacitor, and the electrodes are three-dimensionally arranged. As a result, the conductor islands can be integrated at a high density, and the conductor islands can be connected to easily create more various elements.

According to a fourth aspect of the present invention, there is provided a thin film formed of a semiconductor such that a step structure is formed and a film thickness formed on or near a step wall is smaller than a film thickness formed on a flat portion. Is formed on a stepped structure, and this thin film is processed into a shape with a fine wire portion. At both ends of the thin wire portion, a tunnel barrier having higher energy than the fine wire portion is automatically formed, and a conductor island is formed in the fine wire portion. Therefore, unlike the conventional Coulomb blockade device, there is no need to surround the conductor island with an electrode, or to form a tunnel barrier by thermal oxidation by widening the electrode. They can be arranged arbitrarily. As a result, various connection structure elements in which the conductor islands are integrated at a high density can be realized by a simple manufacturing process.

According to a fifth aspect of the present invention, a step structure in which a metal film or a semiconductor film is covered with an insulating film is formed, and a film formed on the step side wall or in the vicinity of the side wall is formed in a flat portion. A thin film made of semiconductor is formed on the step structure so as to be thinner than the thickness, and this thin film is processed into a shape having a thin line portion. At both ends of the thin line portion, a tunnel barrier having higher energy than the thin line portion is automatically formed. A conductor island is formed in the thin wire portion, and the conductor island is formed, for example, with a metal film serving as an electrode or a semiconductor film serving as an electrode or a conductor island via an insulating film serving as a non-tunneling capacitor or a tunneling capacitor. Since the connection is made, a Coulomb blockade element in which the conductor island, the non-tunneling capacitor, the tunneling capacitor and the electrode are three-dimensionally arranged can be realized. As a result, it is possible to realize a more diverse connection structure element in which conductor islands are integrated at a high density by a simple manufacturing process, and to realize more various elements by repeating formation of a multilayer structure.

Further, by forming a slope on the step side wall as described in claim 6, a thin film is formed on the flat portion and the side wall at a film thickness ratio substantially corresponding to the slope. The film thickness ratio between the flat portion and the sidewall serving as a tunnel barrier can be controlled by the inclination angle of the sidewall.

Further, by forming the thin film with anisotropic film deposition shape, the thickness formed on the step side wall or the vicinity of the side wall is larger than the film thickness formed on the flat portion. A structure that is also thin can be easily realized.

Further, by forming a thin film by reacting chemical species diffused from the gas phase, the film thickness formed on the step side wall or in the vicinity of the side wall is formed on the flat portion. It is possible to easily realize a structure that is thinner than the film thickness.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view of a Coulomb blockade device according to a first embodiment of the present invention.

FIG. 2 is an energy band diagram schematically showing the principle of the Coulomb blockade device of FIG.

FIG. 3 is an equivalent circuit diagram of the Coulomb blockade device of FIG.

FIG. 4 is a plan view and a cross-sectional view of a Coulomb blockade device showing another embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of the Coulomb blockade device of FIG.

FIG. 6 is a cross-sectional view of a Coulomb blockade device showing another embodiment of the present invention.

FIG. 7 is a plan view and a cross-sectional view of a Coulomb blockade device showing another embodiment of the present invention.

8 is an equivalent circuit diagram of the Coulomb blockade device of FIG.

FIG. 9 is a plan view of a Coulomb blockade device showing another embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram of the Coulomb blockade device of FIG. 9;

FIG. 11 is a plan view of a Coulomb blockade device showing another embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of the Coulomb blockade device of FIG.

FIG. 13 is a plan view and a cross-sectional view of a Coulomb blockade device showing another embodiment of the present invention.

14 is an equivalent circuit diagram of the Coulomb blockade device of FIG.

FIG. 15 is a plan view and a cross-sectional view of a Coulomb blockade device showing another embodiment of the present invention.

16 is an equivalent circuit diagram of the Coulomb blockade device of FIG.

FIG. 17 is a bird's-eye view of a conventional Coulomb blockade element viewed from obliquely above.

18 is an equivalent circuit diagram of the Coulomb blockade device of FIG.

FIG. 19 is a bird's-eye view of another conventional Coulomb blockade element viewed obliquely from above.

[Description of Signs] 1 ... Substrate, 2, 3, 3a-3d, 7, 8, 11 ... Insulating film, 4, 4a-4f ... Silicon layer, 5, 5b, 10, 1
2 .... gate insulating film, 6, 6a, 6b, 9, 13a, 13
b: gate electrode, 20, 20a: thin line portion, 21, 22,
21a to 21f, 22a to 22e ... electrode portions.

Claims (8)

[Claims] 1. A Coulomb blockade element having a thin film made of a semiconductor formed on a step structure made of an insulating film having at least two steps and a flat portion sandwiched between the steps. A Coulomb blockade device, wherein the formed thin film has a thin line portion serving as a conductor island for confining charges on the flat portion, and a film thickness on a step side wall or near the side wall is smaller than that of the thin line portion. . 2. A Coulomb blockade element in which a thin film made of a semiconductor is formed on a step structure in which a metal film or a semiconductor film having at least two steps and a flat portion sandwiched between the steps is covered with an insulating film. The thin film formed on the step structure has a thin line portion serving as a conductor island for confining charges on the flat portion, and the film thickness on the step side wall or near the side wall is smaller than that of the thin line portion. Coulomb blockade element. 3. The Coulomb blockade device according to claim 2, wherein the insulating film is a tunnel insulating film. 4. A step of forming a step structure made of an insulating film having at least two steps and a flat portion sandwiched between the steps, and a film thickness formed on the step side wall or in the vicinity of the side wall is formed on the flat part. A step of forming a thin film made of a semiconductor on the step structure so as to be thinner than the film thickness, and a step of processing the thin film into a shape having a thin wire portion serving as a conductive island for confining electric charges. A method for manufacturing a Coulomb blockade element. 5. A step of forming a step structure in which a metal film or a semiconductor film having at least two steps and a flat portion sandwiched between the steps is covered with an insulating film, and a film thickness formed on the step side wall or in the vicinity of the side wall. Forming a thin film made of a semiconductor on a step structure so that the film becomes thinner than the film thickness formed on the flat portion, and processing the thin film into a shape having a thin wire portion serving as a conductor island for confining electric charges. And a method of manufacturing a Coulomb blockade device. 6. The method for manufacturing a Coulomb blockade device according to claim 4, wherein said stepped side wall has an inclination. 7. The method for manufacturing a Coulomb blockade device according to claim 4, wherein the thin film is formed with an anisotropic film deposition shape. 8. The method for manufacturing a Coulomb blockade device according to claim 4, wherein the thin film is formed by reacting a chemical species diffused from a gas phase. .