JPH1093081A - Semiconductor element, semiconductor storage device and manufacturing method of semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a self-align contact technique for enabling provision of contact holes at intervals according to design specification, when applied to a transistor having a gate length based on the design value. SOLUTION: A transistor has a gate electrode 19 covered at its sidewall and upper face with an insulating film, diffusion layers 25a, 25b formed on underlying base of semiconductors at both sides of the gate electrode 19, wiring lines 31a, 31b, and contact holes 29a, 29b for connection of the wiring lines 31a, 31b with the diffusion layers 25a, 25b. Further, a spacing d1 between the gate electrode 19 and contact holes 29b, 29b at their adjacent ends is set to have a dimension of a design specification or less. A margin m1 of the wiring line to the contact holes 29a 29b in its gate length direction is set to be the interval d1 or less. However, the margin m1 may be 0 or negative.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a gate electrode, a semiconductor memory device using the same, and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art LSI (Large Scale Integrated Circui)
One of the technologies that can achieve higher integration of t) is self-aligned contact (SAC).
There is a technology (for example, Reference I: Applied Physics Vol. 64, No. 11 (199
5), PP.1148-1149). This technique is to reduce the distance between the gate electrode and the contact hole by allowing a part of the contact hole to overlap on the sidewall film of the gate electrode (see FIG. 1 on page 1148 of Document I, Middle column 4-1
1 line). This technology uses a NOR type ROM (Read Onl
This is particularly useful for high integration of semiconductor storage devices such as a y memory) and a flash memory. For example, in the case of a flash memory manufactured according to a design standard of 0.5 μm, the distance d ₁ between the gate electrode and the contact hole without the SAC technology.
Needs to be 0.5 μm. However, by using the SAC technique, the distance d ₁ can be set to a value smaller than a value according to the design standard, for example, a value of about 0.3 μm, which is a margin for mask alignment. Therefore, high integration of the LSI can be achieved.

[0003]

[SUMMARY OF THE INVENTION However, when simply reduce the distance d ₁ between the gate and the contact hole, problems such as occur following. About this FIG.
This will be described with reference to FIG.

FIG. 19 is a schematic plan view of a field effect transistor (hereinafter, transistor), and FIG.
FIG. 20 is a schematic cross-sectional view of the transistor (a cross-sectional view taken along a line II in FIG. 19). However, here, an example of a transistor having a wide gate width is illustrated. That is, an example of a transistor having a large current driving capability is shown. In addition, the plan view shows the main components in a see-through state, and some components are knitted or hatched to clarify the boundaries between the components. In the cross-sectional view, hatching indicating a cross section is partially omitted. In these FIGS. 19 and 20,
11 is a silicon substrate (see FIG. 20), 13 is an insulating film for isolation between elements (see FIG. 20), 15 is an active region, 17
Is a gate insulating film (see FIG. 20), 19 is a gate electrode, 2
Reference numerals 1 and 23 denote an upper surface insulating film and a side wall insulating film provided on the upper surface and the side wall of the gate electrode, respectively (see FIG. 20).
5a and 25b are diffusion layers serving as source / drain regions, 27 is an interlayer insulating film (see FIG. 20), 29a and 29
b are contact holes provided in the interlayer insulating film, 3
Each of 1a and 31b is a wiring connected to the diffusion layer. Note that the gate electrode 19 is an example composed of polysilicon 19a and silicide 19b. Also, the diffusion layer 2
5a is a low impurity concentration layer 25aa and a high impurity concentration layer 2
5ab, and the diffusion layer 25b is a low impurity concentration layer 25.
This is an example composed of ba and a high impurity concentration layer 25bb. That is, an example of the diffusion layers 25a and 25b according to the LDD (Lightly Doped Drain) structure is shown.

In a transistor, as shown in FIG. 19, it is preferable that the contact holes 29a and 29b on both sides of the gate electrode 19 are opposed to each other with the gate electrode 19 interposed therebetween. This is because the current path becomes the shortest, so that advantages such as a reduction in voltage drop due to the diffusion layer can be obtained. Needless to say, it is preferable that the contact holes on the source side and the drain side are arranged at intervals in accordance with the design standard in the gate width direction. This is because the effective gate width can be increased (details will be described later with reference to FIG. 21). However, the gate electrode 19 and the contact hole 2
In case of small distance d ₁ between 9a (29 b), both sides of the contact hole 29a of the gate electrode 19 without even any contrivance, when the face of the 29 b, wiring 31
a, 31b cannot be formed.
The details are as follows. In most cases, the gate length L is a design criterion determined in consideration of the processing accuracy in the manufacturing process and the minimum distance that can secure the electrical insulation required for the semiconductor element (hereinafter referred to as “normal”). , Which may be abbreviated as “design standard”.) (Hereinafter also referred to as “ordinary design standard value”), so that it is the minimum dimension. That is, if the normal design reference value is, for example, 0.5 μm, the gate length is set to about 0.5 μm. Also,
In order to effectively use the SAC technique, the distance d ₁ between the gate electrode and the contact hole is set to a normal design reference value or a value smaller than the normal design reference value. Here, assuming that the normal design standard value is 0.5 μm, an example in which the distance d ₁ is 0.3 μm, that is, smaller than the normal design standard value will be considered. At such time, the contact hole 29a (29
When conventional design standard value eg 0.5μm margin m ₁ along the gate length direction of the wiring 31a (31b) with respect to b), the wiring 31a, 31b spacing d ₂ between the 0.1μm
It will be about. Since such a value exceeds the processing limit of the current fine processing technology, the wiring 31a, 31
b cannot be formed.

In order to avoid the above problem, FIG.
As shown in FIG. 1, a method of alternately arranging the contact holes 29a and 29b on both sides of the gate electrode 19 without opposing each other is adopted. In this case, the wirings 31a, 31
The minimum interval between b can be an interval in the direction oblique to the gate length direction (d _{x in} FIG. 21). Therefore, the dimensions of each part of the element along the gate length direction can be made the same as those of the element described with reference to FIG. FIG. 21 shows an example in which the contact holes 29a and the contact holes 29b are alternately arranged at an angle of 45 degrees. However, if the contact holes are alternately arranged as described above, the contact hole interval P between the source side and the drain side will be wider than that described with reference to FIG. Specifically, in the case of the arrangement example of FIG. 21, source - scan side, a contact hole interval P at the drain side, respectively, P = (2 × diameter of the contact hole a + 2 × spacing interconnects d _X / (2) ^{1 / 2} + 4 × margin m ₁ ). Therefore, a = 0.6 μm, d _x = 0.5 μm,
Assuming that m ₁ = 0.5 μm, P = 2 × 0.6 + 2 ×
0.5 / (2) ^1/2 + 4 × 0.5 ≒ 4 μm. In the semiconductor device in which the distance d ₁ between the gate electrode and the contact hole is larger than the normal design reference value of 0.5 μm, the contact hole distance P can be set to 1 μm in principle. The interval P becomes considerably large. The current flowing through the transistor flows through the shortest path between the source side contact and the drain side contact. Then, in the case of the example of FIG. 21, it is considered that the current mainly consists of components flowing obliquely to the gate length direction. Therefore, the interval P between the contact holes
As the size of the contact hole increases, a portion having a poor current path function increases between the contact holes. Therefore, it can be said that the larger the interval P between the contact holes, the smaller the effective gate width, which causes a problem that the current driving capability is reduced.

As a method of avoiding the above-mentioned problem that the current driving capability is reduced due to the increase in the contact hole interval, it is conceivable to increase the impurity concentration of the diffusion layers 25a and 25b. However, an LSI such as a flash memory that uses a high voltage inside the LSI
In a high-voltage LSI such as a liquid crystal display driver, the impurity concentration of the diffusion layers 25a and 25b is rather reduced. Because when you do this
(1) Since the depletion layer in the portion of the diffusion layers 25a and 25b in contact with the field expands, the junction breakdown voltage of the transistor can be improved. (2) Also, the insulating film for element isolation (field insulating film) ) Threshold V _t of the underlying parasitic transistor
Is increased without lowering the junction breakdown voltage of the transistor. A flash memory is one of the typical semiconductor devices to which the SAC technology is applied. Therefore, contact holes 29a on both sides of gate electrode 19,
The above method of alternately arranging the 29b without opposing each other is not preferable in view of the above point (the point that there is also a semiconductor device in which the impurity concentration of the diffusion layer cannot be increased).

In applying the SAC technology to a transistor having a gate length of a normal design reference value, the source side,
It is desired to realize a technique in which a plurality of contact holes can be arranged on the drain side at intervals according to a normal design standard value, and the contact holes on the source side and the drain side can be opposed to each other.

[0009]

According to the invention of a semiconductor device of this application (also referred to as a first invention), a gate electrode whose side wall and upper surface are covered with an insulating film, and a gate electrode on both sides of the gate electrode are provided. A diffusion layer formed in a semiconductor base portion, contact holes provided on both sides of the gate electrode for connecting a wiring to the diffusion layer, and a semiconductor element including the wiring, wherein the gate electrode and the both sides of the gate electrode are provided. A first gap formed between each of the contact holes, and a first gap extending from the contact hole in a gate length direction of the wiring and being equal to or less than the first gap. A first margin, which is a wiring margin, is provided. That is, a margin (first margin) of the wiring extending in the gate length direction with respect to the contact hole is set to a value equal to or less than an interval (first interval) between the gate electrode and the contact hole. I do.

The first interval is determined according to a design standard (“ordinary design standard”) determined in consideration of the processing accuracy in the manufacturing process and the distance at which electrical insulation can be ensured in the semiconductor element (“normal design standard”). In this case, a transistor having a smaller distance between the gate electrode and the contact hole is realized, so that a transistor which is small and can be expected to operate at high speed is expected. Further, in the embodiment of the present invention, the first margin may be 0 (when the contact hole diameter is equal to the wiring width) or may be negative (when the contact diameter is greater than the wiring width).

According to this semiconductor device, a plurality of contact holes are formed on both sides of the gate electrode in the gate width direction at intervals according to a normal design standard, and formed on one side. Even if the formed contact hole is formed so as to face the contact hole formed on the other side, the distance between the source side wiring and the drain side wiring is at least the same value as the gate length, that is, the normal design standard value. Can be. Therefore, it is possible to provide a semiconductor element that effectively utilizes the SAC technology and that exhibits a desired current driving capability.

Further, in the semiconductor device of the present invention, the distance between the contact hole and the gate electrode can be made smaller than a normal design standard value, and the contact holes can be opposed to each other with the gate electrode interposed therebetween. Therefore, a semiconductor device having the shortest current path and a wide effective gate width is realized. Therefore, even if the diffusion layer is formed of a diffusion layer having a low impurity concentration, it can be said that the drain current does not decrease much. Therefore,
Since it is not necessary to use the high impurity concentration layer, the number of steps for forming the high impurity concentration layer can be reduced, so that the manufacturing process of the semiconductor element can be simplified. Moreover the fact that the diffusion layer can be composed of a diffusion layer of low impurity concentration, LSI or the use of high voltage internally kept high both threshold V _t of the junction breakdown voltage and the parasitic transistor at a high voltage system LSI.

According to the invention of the semiconductor memory device of this application, in a semiconductor memory device having a memory cell array, a row decoder and a column decoder, one or both of a row decoder and a column decoder include a switching element included therein. It is constituted by a decoder constituted by the semiconductor element of the first invention.

A decoder is a circuit that requires a high current driving capability and needs to be miniaturized. On the other hand, the semiconductor device of the first invention is a semiconductor device suitable for high integration and exhibiting a desired current driving capability as described above. Therefore, the decoder including the semiconductor element of the first invention has a high current driving capability and is small, so that a small-sized semiconductor memory device having desired characteristics is realized.

According to the method of manufacturing a semiconductor device of this application, a gate electrode having a sidewall and an upper surface covered with an insulating film, a diffusion layer formed in a semiconductor base portion on each side of the gate electrode, Contact holes respectively formed on both sides of the gate electrode for connecting a wiring to a diffusion layer, and in manufacturing a semiconductor device including the wiring, a contact hole is formed between the gate electrode and each of the contact holes on both sides thereof. The contact hole is formed such that an interval of 1 is formed, and a first margin, which is a wiring margin extending in the gate length direction of the wiring with respect to the contact hole, is equal to or less than the first interval. The method is characterized in that the wiring is formed.

According to the manufacturing method of the present invention, the distance between the gate electrode and the contact hole is normally designed so that the contact hole on the source side and the contact hole on the drain side face each other with the gate electrode interposed therebetween. Even when these contact holes are formed so as to be equal to or less than the reference value, at least a value in accordance with a normal design standard can be secured as the distance between the source side wiring and the drain side wiring.
Therefore, it is possible to easily manufacture a semiconductor device that effectively utilizes the SAC technology and exhibits a desired current driving capability.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. The drawings used in the description schematically show the dimensions, shapes, and arrangements of the components so that these inventions can be understood. In each of the drawings, the same components as those shown in FIGS. 19 and 20 are denoted by the same reference numerals, and redundant description may be omitted.

1. First Embodiment FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a schematic sectional view thereof. However, FIG. 1 shows the same notation as FIG. 19 (the same applies to FIGS. 13 and 14 below). FIG. 2 shows the same notation as FIG. 20 (the same applies to other cross-sectional views below).

The semiconductor device according to the first embodiment is characterized in that the wiring 3 for the contact hole 29a (29b) is formed.
1a first to the margin (first margin) m ₁ extending in the gate length direction, is formed between the contact hole 29a of the gate electrode 19 and a source or for drain (29 b) of (31b) is that there as a distance d ₁ the following values. With such a configuration, even if the gate length L is a normal design reference value and the contact hole on the source side and the contact hole on the drain side are opposed to each other with the gate electrode 19 interposed therebetween, and it can be the distance d ₂ between the drain side of the wire to the usual design standard value or more. Therefore, (1) the gate length L is a normal design standard value, and (2)
The gate electrode 19 and the contact hole 29a, the interval between the 29 b (first interval) d ₁ is below normal design standard value,
(3) A plurality of contact holes are arranged along the gate width direction on both sides of the gate electrode at an interval according to a normal design standard, and (4) a contact hole on the source side and a contact hole on the drain side. A semiconductor element having a structure in which the contact hole faces the gate electrode 19 with the gate electrode 19 interposed therebetween can be realized. Therefore, the semiconductor device of the first embodiment is a semiconductor device that effectively utilizes the SAC technology and has a high current driving capability.

The semiconductor device according to the first embodiment can be manufactured, for example, by the following procedure. This description is made with reference to FIGS.
Refer to. Here, FIGS. 3 to 5 are process diagrams showing the state of the sample in the main process in the manufacturing process by a cross-sectional view corresponding to FIG.

First, a silicon substrate 1 as a semiconductor substrate
First, a well (not shown) and an active region 15 are sequentially formed by a well-known method. Next, this sample is thermally oxidized to form a gate insulating film 17 having a thickness of, for example, 20 nm (FIG. 3A).

Next, a polysilicon layer 19x is formed on this sample.
Is formed to a thickness of, for example, 150 nm, and the polysilicon layer 19x is doped with phosphorus. Next, for example, a tungsten silicide layer 19y is
It is formed with a thickness of 0 nm. Next, an insulating film 2 is formed on this sample.
Here, a nitride film (SiN film) 21a is formed with a suitable thickness as 1a. This nitride film 21a becomes the upper surface insulating film 21 after patterning for forming a gate electrode later. In addition, it functions as an etching stop layer when forming a contact hole (FIG. 3).
(B)).

Next, a resist pattern for forming a gate electrode is formed on the nitride film 21a.
a, the tungsten silicide layer 19y and the polysilicon layer 19x are respectively etched. Thus, a gate electrode 19 having a so-called polycide structure and an upper surface insulating film 21 are obtained (FIG. 3C).

Next, in order to form an LDD structure, first, L
Mask pattern formation and ion implantation for forming the low impurity concentration layers 25aa and 25ba in the DD structure are performed. Thereby, low impurity concentration layers 25aa and 25ba are formed on both sides of the gate electrode 19 in a self-aligned manner (FIG. 4).
(A)). Of course, when manufacturing an N-channel transistor and a P-channel transistor on a semiconductor base, respectively, a mask pattern is formed and ion implantation is performed according to each transistor. For an N-channel transistor, for example, phosphorus is added to, for example, about 2 × 10 ¹³ / cm
Implantation is performed at a dose of about ² to form an n ⁻ layer. For a P-channel transistor, for example, boron or BF
_2, for example by injecting at about 2 × 10 ¹³ / cm ² dose of about P ^- forming a layer.

Next, an insulating film (sidewall insulating film) is formed on the side wall of the gate electrode 19 (FIG. 4B). Specifically, a nitride film is formed to a suitable thickness here as an insulating film (not shown) for forming a sidewall insulating film on the sample on which the low impurity concentration layers 25aa and 25ba have been formed. Next, the insulating film for forming the sidewall insulating film is anisotropically etched. In this etching, the insulating film for forming the side wall insulating film selectively remains on the side wall of the stacked body composed of the gate electrode 19 and the upper surface insulating film 21, so that the side wall insulating film 23 can be formed on the side wall of the gate electrode 19. The sidewall insulating film 23 functions not only as a mask during ion implantation for forming the high impurity concentration layers 25ab and 25bb later, but also as an etching stop layer when forming a contact hole later. Have.

Next, a lithography step and an ion implantation step for forming the high impurity concentration layers 25ab and 25bb in the LDD structure on this sample are performed in this order.
Thus, high impurity concentration layers 25ab and 25bb are formed in a predetermined region on both sides of the gate electrode 19 in a self-aligned manner. The ion implantation conditions here can be, for example, as follows. For an N-channel transistor, for example, arsenic is implanted at a dose of, for example, about 5 × 10 ¹⁵ / cm ² .
For a P-channel transistor, for example, BF ₂ is implanted at a dose of, for example, about 1 × 10 ¹⁵ / cm ² . Thereafter, each of the impurity layers 25aa, 25ab, 25ba, 2
Heat treatment for activating 5bb is performed, and diffusion layer 25 is formed.
a and 25b are obtained (FIG. 4C).

Next, on this sample, for example, a BPSG film (Boro Phospho Silo) is formed as an insulating film 27a for forming an interlayer insulating film.
icate Glass) is formed with a thickness of, for example, 800 nm (FIG. 5A).

Next, a mask pattern for forming a contact hole is formed on the insulating film 27a for forming an interlayer insulating film (not shown), and thereafter, the insulating film 27a is selectively etched. Contact holes 29a and 29b are formed (FIG. 5B). However, in forming the contact hole, the gate electrode 19 and the contact hole 2 were formed.
9a (29 b) so that the distance d ₁ of the end between the respective adjacent becomes less normal design standard value, perform lithography and etching. Specifically, here, after forming the contact holes 29a and 29b, the B as the insulating film 27a is formed so that a part of each may overlap the side wall film 23.
Etch the PSG film. That is, the SAC technique is used.

In the above process, the gate electrode 19 is used.
Since the nitride film is formed directly on the upper and side surfaces of the transistor, the transistor characteristics may be degraded by the stress of the nitride film. Therefore, the following method may be implemented to avoid this. Each of the upper surface insulating film and the side wall insulating film is formed of a SiO ₂ film or PSG (Phospho Silicate Glass). Then, a nitride film is formed on this sample as an etching stopper (not shown). Thereafter, a contact hole is formed as described above by forming an insulating film for forming an interlayer insulating film, forming a mask pattern for forming a contact hole, and selectively etching the insulating film. In the case of this method, even after the selective etching of the insulating film for forming the interlayer insulating film is completed, the step of removing the nitride film as the etching stopper is performed. However, since the influence of the stress of the nitride film is reduced, the reliability of the transistor can be improved.

On the sample on which the contact holes have been formed, an aluminum film (not shown), for example, as a metal film for forming a wiring is formed on the sample by, for example, sputtering, for example, for 800 minutes.
It is formed to a thickness of nm. Next, a mask pattern for forming the wirings 31a and 31b is formed on the wiring forming metal film, and then the wiring forming metal film is selectively etched to form the wirings 31a and 31b (FIG. 5 ( C)). However, when forming the wires 31a and 31b, the wires 31a (31b) for the contact holes 29a (29b) are formed.
The margin (first margin) m ₁ along the gate length direction in b) is
Lithography and etching are performed so that the distance d ₁ or less.

Thereafter, although not shown, an insulating film to be a passivation film is formed. Further, an opening is formed in the passivation portion corresponding to a portion to be a pad of the wirings 31a and 31b, and the wafer process is completed.

2. Second Embodiment According to the first embodiment, a semiconductor device that effectively utilizes the SAC technology and has a high current driving capability is obtained. However, the contact holes 29a (29
Since margin m ₁ wire 31a (31b) with respect to b) is small, if if there is mask misalignment in the lithography process for wiring formation by overetching during etching for wiring formation contact hole - le of There is a risk that the metal will be etched. Note that over-etching refers to performing excessive etching so that the metal is etched as desired in each part of the base even if the base has irregularities (hereinafter the same). Therefore this second embodiment, claims the measures to compensate for the points above room m ₁ is small. This will be described mainly with reference to manufacturing process diagrams shown in FIGS.

In the second embodiment, for example, up to the contact holes 29a and 29b are formed by the procedure described in the first embodiment (FIG. 6).
(A)).

Next, a BPSG film, for example, is formed on the entire surface of the wafer including the contact holes 29a, 29b as an insulating film 41a for forming an inner wall film by, for example, 200 nm by CVD.
m (FIG. 6B).

Next, the formed insulating film 41a is removed by an anisotropic etching technique. In this way, an inner wall film 41 for narrowing the opening size of the contact hole to a size smaller than the resolution limit by the lithography technique can be formed on the inner wall of each of the contact holes 29a and 29b (FIG. 6C).

Thereafter, the wirings 31a and 31b are formed in the same procedure as that described in the first embodiment. Thus, the semiconductor device of the second embodiment having the inner wall film 41 on the inner wall of each of the contact holes 29a and 29b is obtained (FIG. 7).

In the second embodiment, since the opening dimension of the contact hole can be made smaller than the resolution limit of the lithography technique, the allowance m ₁ of the wiring 31a (31b) with respect to the contact hole 29a (29b) is widened as a result. Become. Therefore, the margin for mask alignment in the lithography process for forming the wiring can be increased accordingly. Alternatively, the opposite idea may be taken. That is, the margin m ₁ may be designed (plotted) to be smaller than that in the first embodiment by the provision of the inner wall film.

3. Third Embodiment According to the first embodiment, a semiconductor device that effectively utilizes the SAC technology and has a high current driving capability is obtained. However, in the first embodiment, the wiring 31
a and 31b are formed of one type of material. On the other hand, in the third embodiment, the constituent material of the wiring is different between the portion inside the contact hole and the portion outside the contact hole. About this, FIG.
This will be described below with reference to FIG. Here, FIG. 8 is a schematic sectional view of a semiconductor device according to the third embodiment.

In the third embodiment, the wiring portion inside the contact hole is constituted by the first metals 31aa and 31ba, and the wiring portion outside the contact hole is formed by the first metal 31aa.
aa, 31ba capable of selective etching to the second
Metal 31ab, 31bb. First metal 31
aa and 31ba can be made of, for example, a high melting point metal, for example, tungsten, and the second metals 31ab, 31bb can be made of, for example, aluminum (including an aluminum alloy).

With such a wiring structure, the wiring portion inside the contact hole is not etched in the etching when forming the wiring portion outside the contact hole. Therefore, a semiconductor element using the SAC technology, in which an increase in wiring resistance and a decrease in reliability due to a wiring portion in the contact hole hardly occurs, is realized.

The semiconductor device according to the third embodiment can be manufactured, for example, by the following procedure. For example, according to the procedure described in the first embodiment, the contact hole 29
a, 29b (FIGS. 3A-5D).
(B)). Next, contact holes 29a, 29b
For example, tungsten (W) is deposited as a first metal on the sample including the inside by a CVD method. Then, etching is performed by an etch back method so that tungsten remains only in the contact hole. Next, a second
Metal such as aluminum is deposited by a sputtering method,
Then, this is patterned. In this case, a wiring made of the first and second metals can be obtained. In this way, it is possible to select an etching condition that has an etching resistance to the tungsten during the etching of the aluminum. Since the etching conditions can be selected in this manner, even when the aluminum is over-etched and reaches the inside of the contact hole, the tungsten in the contact hole is not etched. Therefore, wiring margin m for contact hole
₂ can be made smaller than in the first embodiment. The concept of the second embodiment (the concept of providing an inner wall film in a contact hole) may be combined with the third embodiment.

4. Fourth Embodiment In the third embodiment, an example has been described in which the wiring portion inside the contact hole and the wiring portion outside the contact hole are made of different materials. However, the film forming process and the etching process are increased by one each for the two types of materials. Therefore, in the fourth embodiment, the wiring is formed only of the high melting point metal. This will be described below with reference to FIG. Here, FIG. 9 is a schematic sectional view of the semiconductor device of the fourth embodiment.

In the fourth embodiment, for example, up to the contact holes 29a and 29b are formed by the procedure described in the first embodiment (FIGS. 3A to 3C).
FIG. 5 (B)). Next, the contact holes 29a, 2
A tungsten (W) film is deposited as a high melting point metal film on the sample including the inside 9b by a CVD method to a thickness of, for example, 500 nm. In the third embodiment, the etch back is performed thereafter, but in the fourth embodiment, the tungsten film is patterned into a predetermined shape without performing the etch back. Thus, the wirings 31x and 31y made of a high melting point metal (here, tungsten) and connected to the diffusion layers 25a and 25b are formed.

According to the fourth embodiment, the aluminum film forming step and the etching step required in the third embodiment can be omitted. However, wiring 3
Since the entire 1x and 31y are made of a high melting point metal, if a mask misalignment occurs in the lithography step for forming the wiring, one of the wirings in the contact hole is overetched in the subsequent etching step. There is a risk that the part will be cut off. However, even in such a case, since the wiring is a high melting point metal, electromigration (EM (Ele
ctro Migration)) and stress migration (SM
(Stress Migration)), so there is little problem of reduced reliability. Therefore, it can be said that a highly reliable wiring can be formed as compared with the first embodiment. Furthermore, it can be said that the wiring allowance m ₂ for the contact hole can be made smaller than in the first embodiment. Note that the idea of the second embodiment (the idea of providing an inner wall film in a contact hole) may be combined with the fourth embodiment.

5. Fifth Embodiment In the second embodiment and the fourth embodiment, the description has been given of the measures against over-etching when patterning the wiring forming metal. Here, in order to reduce the amount of over-etching, it is useful to flatten the base before forming the wiring. In particular, when a fine semiconductor element is to be formed by using the SAC technique as in the present invention, the flattening of the base before forming the wiring is more useful. The fifth embodiment is an example in which the countermeasure is taken. This will be described with reference to FIG. Here, FIG. 10 is a process drawing shown by a cross-sectional view.

In the fifth embodiment, for example, up to the insulating film 27a for forming an interlayer insulating film is formed by the procedure described in the first embodiment (FIG. 10).
(A)). Next, the surface of the insulating film 27 is, for example, CMP (C
The surface is flattened as much as possible by a chemical Machanical Polishing method (FIG. 10B). Alternatively, when forming the insulating film 27a for forming the interlayer insulating film, a highly flat insulating film may be formed by a self-flattening CVD method using ethanol or the like. Next, contact holes 29a and 29b are formed in the same procedure as in the first embodiment.
(C)) Next, wirings 31a and 31b are formed (FIG. 10).
(D)).

According to the fifth embodiment, the thin film for forming a wiring is formed on a base having a flat surface except for a contact hole. Therefore, the amount of overetching when patterning the wiring forming thin film can be reduced, and the risk of the wiring forming thin film portion in the contact hole being shaved can be reduced. Therefore, it is possible to prevent a decrease in the reliability of the wiring and an increase in the resistance of the wiring. The concept of the fifth embodiment may be combined with any of the second to fourth embodiments.

6 In the semiconductor device according to a sixth embodiment the present invention, the contact hole because it utilizes the SAC technology - can the distance d ₁ between the gate electrode and the normal design standard value following values - Le and gain. Needless to say, the contact hole interval P between the source side and the drain side can also be a value according to a normal design standard. That is, d ₁ can be set to, for example, the thickness of the sidewall insulating film, and if the design standard is 0.5 μm, the contact hole interval P can be set to 1.0 μm. Therefore, it is considered that even if the diffusion layer is formed only of the low impurity concentration layer, the drain current does not decrease much. In the sixth embodiment, the structure is claimed. This description is made with reference to FIG. Here, FIG. 11 is a sectional view of the semiconductor device of the sixth embodiment.

In the sixth embodiment, the source / drain regions are constituted only by the low impurity concentration diffusion layers 25x. Otherwise, the structure is the same as that described in the first embodiment. The diffusion layer 25x is formed, for example, of the low impurity concentration layers 25aa and 25ba in the first embodiment.
Can be formed according to the ion implantation conditions at the time of forming.

According to the semiconductor device of the sixth embodiment, the high impurity concentration layers 25ab and 25bb (see FIG. 1) can be eliminated. Therefore, high impurity concentration layers 25ab, 2
The lithography step and the ion implantation step for forming 5bb can be omitted. Specifically, the lithography step and the ion implantation step for each of the N-channel and P-channel transistors can be omitted.

Further, in the semiconductor device of the sixth embodiment, the following remarkable effects can be obtained. The threshold value of the parasitic transistor formed under the field insulating film is
It is proportional to the impurity concentration under the gate insulating film. On the other hand, the junction breakdown voltage of the semiconductor device is inversely proportional to the impurity concentration below the field insulating film. Therefore, the LS which must withstand high voltages such as a nonvolatile memory such as a flash memory or a driver for a liquid crystal display.
In I, Fi - junction withstand voltage of the semiconductor device itself when the threshold V _t attempts to set more than 15V parasitic transistor formed under the field insulating film is lowered to 15V or less, to satisfy both Becomes difficult. However, in the sixth embodiment, since the diffusion layer is the diffusion layer 25x having a low impurity concentration, the edge portion in contact with the element isolation region has a low impurity concentration. Therefore, junction breakdown voltage and Fi of the semiconductor device - each threshold V _t of the parasitic transistor formed under the field insulating film, both a high value, for example, it is possible to keep the respective values of more than 10V.

The idea of the sixth embodiment is described in the second.
The present invention may be combined with any of the ideas of the fifth to fifth embodiments.

7. Seventh Embodiment In the above-described sixth embodiment, an example in which the entire diffusion layer forming the source / drain region is a low impurity concentration layer has been described. However, in such a case, the contact resistance is increased, for example, by a factor of two or more as compared with the case of having a high impurity concentration layer (see FIG. 1), which may cause a decrease in the operation speed of the semiconductor element. The seventh embodiment insists on the countermeasure. This will be described with reference to FIG. Here, FIG. 12 is a cross-sectional view of the semiconductor device of the seventh embodiment.

In the seventh embodiment, the portion of the low impurity concentration diffusion layer 25x that opposes the contact hole is the high impurity concentration diffusion layer 25y, and the edge remains the low impurity concentration layer. . By doing so, the increase in contact resistance which is a concern in the sixth embodiment can be solved.

When the semiconductor device of the seventh embodiment is manufactured, first, up to the side wall insulating film 23, for example, according to the procedure described in the first embodiment (FIG. 3).
(A) to FIG. 4 (B)). Thus, the diffusion layer 25x having a low impurity concentration shown in FIG. 12 is obtained. Side wall insulating film 23
After the formation, in the first embodiment, ions are implanted for forming a high impurity concentration layer. However, in the seventh embodiment, first, an interlayer insulating film is formed and a contact hole is formed. I do. After that, impurities are implanted into the low impurity concentration diffusion layer 25x through the contact holes. As a result, the portion of the low impurity concentration diffusion layer 25x opposed to the contact hole becomes the high impurity concentration diffusion layer 25y.

8. Eighth Embodiment In the first embodiment, an example in which a plurality of contact holes are provided on each of the source side and the drain side has been described.
However, one contact hole having a long planar shape may be provided on each of the source side and the drain side. This will be described with reference to FIG. Here, FIG. 13 is a plan view of the semiconductor device of the eighth embodiment.

In the eighth embodiment, each of the contact holes 29x and 29y has a rectangular planar shape whose long side extends in the gate width direction. Moreover, the dimension of the long side is the dimension of the active region 15 (dimension along the gate width direction).
Is almost equal to These contact holes 29
x and 29y are hereinafter referred to as long contact holes for convenience of explanation. This long contact hole 29
The dimensions of the short sides of x and 29y are set to normal design reference values. Since this long contact hole is almost the same as the gate width, the wiring 31a (31b)
Thus, a current can be directly supplied to the diffusion layer 25a (25b) in the entire region along the gate width. Therefore, the increase in resistance due to the diffusion layer can be substantially ignored. This long contact hole is particularly suitable when the diffusion layer is constituted only by the low impurity concentration layer (in the case of the semiconductor element of the sixth embodiment).

9. Ninth Embodiment In each of the above embodiments, a margin m ₂ between the contact hole and the active region (see FIG. 1; also referred to as a second margin)
Was not specifically mentioned. However, in order to further improve the high integration of semiconductor devices, it is necessary to consider also the second margin m _2. The ninth embodiment is an example. This will be described with reference to FIGS. Here, FIG. 14 is a plan view of the semiconductor device according to the ninth embodiment, and FIG. 15 is a cross-sectional view taken along line II of FIG. 16 and 17 are views showing the steps of manufacturing the semiconductor device according to the ninth embodiment.

In the semiconductor device of the ninth embodiment, as shown in FIG. 14, contact holes 29a (29
certain margin m ₂ as smaller dimension than the misalignment amount of scheduled in lithography for the active region 15 b). Specifically, the edge of the contact hole coincides with the boundary between the active region and the field region,
The positional relationship is such that a part of the contact hole is located on the field region (element isolation region). Needless to say, at least a main portion of the diffusion layer 25a (25b), here, the high impurity concentration layer 25ab (25bb) is formed in a self-alignment manner with the contact hole 29a (29b) (see FIG. 15).

In the semiconductor device of the ninth embodiment, the active region 15 of the contact hole 29a (29b) is formed.
Since margin m ₂ is in the smaller size than the deviation amount adjustment that is scheduled in the lithographic art for, because it narrows the active region by that amount, it can be shortened in the plane area of the semiconductor device. Since the diffusion layers themselves (specifically, the high impurity concentration layers 25ab and 25bb themselves) are formed in a self-alignment manner with respect to the contact holes,
Even if the margin m ₂ is small, the edge of the diffusion layer 25 is formed as desired also near the boundary between the active region and the field region (see FIG. 15). Therefore, even if the margin m ₂ is reduced, a leak current at the boundary between the active region and the field region (that is, a leak current between the wiring and the N well or the P well) does not occur.

The semiconductor device according to the ninth embodiment can be manufactured, for example, by the procedure described below with reference to FIGS.

For example, according to the procedure described in the first embodiment, the low impurity concentration layers 25aa and 25ba are formed, and further, the side wall film 23 is formed (FIG. 16A). However, the area of the active region is reduced as much as the margin m ₂ between the active region and the contact hole can be reduced. In the first embodiment, ion implantation for forming a high impurity concentration layer is performed thereafter, but here, an insulating film 27a for forming an interlayer insulating film is formed (FIG. 1).
6 (B)). Next, contact holes 29a and 29b are formed in the insulating film 27a by lithography and etching. However, at this time, the allowance m of the contact hole 29a (29b) for the active region 15 is set.
₂ is set so as to have a size smaller than the amount of misalignment expected in lithography, and a contact hole is formed (FIG. 17A). Actually, the contact hole is formed such that the end of the contact hole is located on the boundary between the active region and the field region, or part of the contact hole is located on the field region. Next, impurities are further implanted into the low impurity concentration layers 25aa and 25ba through the contact holes. As a result, the high impurity concentration layers 25ab and 25bb are formed in a self-aligned manner with respect to the contact holes (FIG. 17B). Therefore, diffusion layers 25a and 25b having desired high impurity concentration layers 25ab and 25bb near the boundary between the active region and the field region are obtained (FIG. 15).

10. Tenth Embodiment (Example of Application to Semiconductor Memory Device) The semiconductor element of the present invention can be applied to various semiconductor devices manufactured using SAC technology. Among them, for example, DRAM, nonvolatile memory, flash memory and N
It is preferably applied to a semiconductor memory device such as an OR type ROM. This is because the demand for high integration is particularly large. In addition, it is preferable that the switching elements included in the row decoder and the column decoder in the semiconductor memory device are respectively constituted by the semiconductor elements of the present invention. This is because a row decoder drives a word line and a column decoder drives a bit line, so that a transistor having high current driving capability is required. If the memory cell array has been highly integrated and has a large capacity, the decoder must also be highly integrated and have a large capacity unless the area occupied by peripheral circuits in the semiconductor memory device becomes a bottleneck. This is because the conversion cannot be achieved.

FIG. 18A is a configuration diagram of a main part of a typical semiconductor memory device, and FIG. 18B is a configuration diagram of a row decoder and a column decoder provided in the semiconductor memory device. In FIG. 18A, reference numeral 51 denotes a memory cell array;
Is a memory cell, W is a word line, and B is a bit line. Further, 53 is a row decoder, 55 is a row address buffer, 57 is a sense amplifier, 59 is a column decoder, 61
Is a column address buffer. Since the functions of these components are well known, their description is omitted here.

Each of the row decoder 53 and the column decoder 59 usually includes a circuit based on a NAND circuit. Therefore, these decoders are constructed using a large number of transistors. FIG. 18B shows an example of a decoder simplified to two inputs (for example, Document II: “Custom IC Design Technology (Introduction to ASIC / VLSI Technology),
(Issued September 1, 1986), PJ Hicks, Kayama
Shin / Tetsuya Iizuka, translation, Soken Shuppan, page 51). The example of FIG. 18B also includes four transistors T1 to T4. It can be seen that a large-scale decoder requires an enormous number of transistors. By configuring these transistors with the semiconductor element of the present invention, a decoder that is small in size and has a desired current driving capability can be realized, and further downsizing of the semiconductor memory device can be expected.

[0066]

As is apparent from the above description, according to the invention of the semiconductor device of this application, the gate electrode whose side wall and upper surface are covered with the insulating film, the diffusion layer serving as the source / drain, and the diffusion layer A contact hole formed on both sides of the gate electrode for connecting a wiring to a layer, and a semiconductor device having the wiring, wherein a margin m ₁ along the gate length direction of the wiring with respect to the contact hole is set to the gate electrode. And a distance d ₁ between the contact hole and the contact hole. Therefore, a plurality of contact holes are formed on both sides of the gate electrode along the gate width direction and at intervals according to a normal design standard, and the contact holes formed on one side are formed on the other side. be formed so as to face the contact holes formed, the distance d ₂ of the source-side wiring and the drain side wiring can be the same value or normal design standard value to the gate length is also a minimum. Therefore, (i) the gate length of the normal design standard, (ii) the distance between the gate electrode and the contact hole is less than the normal design standard value, and (iii) the contact on the source side and the drain side respectively. Holes are arranged at regular design standard intervals, and (iv) a semiconductor device is realized in which the contacts sandwiching the gate electrode face each other. Therefore, it is possible to provide a semiconductor device that exhibits a desired current driving capability while effectively utilizing the SAC technology.

Further, according to the invention of the semiconductor memory device of this application, one or both of the row decoder and the column decoder provided in the memory device are constituted by the decoder in which the switching element included therein is constituted by the semiconductor element. I do. Therefore, a semiconductor memory device including a decoder having a small size and a desired current driving capability can be obtained, so that the semiconductor memory device can be downsized.

Further, according to the invention of the method of manufacturing a semiconductor device of the present application, wiring is performed such that a margin m ₁ of the wiring with respect to the contact hole along the gate length direction is equal to or smaller than a distance d ₁ between the gate electrode and the contact hole. To form Therefore, a plurality of contact holes are formed on both sides of the gate electrode along the gate width direction and at intervals according to a normal design standard, and the contact holes formed on one side are formed on the other side. Even if it is formed so as to face the formed contact hole, patterning of the source side wiring and the drain side wiring becomes possible. Therefore, a semiconductor device having the above-described configurations (i) to (iv) can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment.

FIG. 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment, which is a cross-sectional view focusing on a cut along a line II in FIG. 1;

FIG. 3 is a manufacturing process diagram for describing an example of a method for manufacturing a semiconductor device according to the first embodiment.

FIG. 4 is a manufacturing step diagram subsequent to FIG. 3 for illustrating an example of the method for manufacturing a semiconductor device of the first embodiment.

FIG. 5 is a manufacturing step diagram illustrating the example of the method for manufacturing the semiconductor device according to the first embodiment, which is subsequent to FIG. 4;

FIG. 6 is an explanatory diagram of the second embodiment, and is a main part process diagram for describing an example of a method for manufacturing a semiconductor device of the second embodiment.

FIG. 7 is a schematic sectional view of a semiconductor device according to a second embodiment.

FIG. 8 is a schematic sectional view of a semiconductor device according to a third embodiment.

FIG. 9 is a schematic sectional view of a semiconductor device according to a fourth embodiment.

FIG. 10 is an explanatory diagram of a semiconductor device according to a fifth embodiment, particularly showing a manufacturing process.

FIG. 11 is a schematic sectional view of a semiconductor device according to a sixth embodiment.

FIG. 12 is a schematic sectional view of a semiconductor device according to a seventh embodiment.

FIG. 13 is a schematic plan view of a semiconductor device according to an eighth embodiment.

FIG. 14 is a schematic plan view of a semiconductor device according to a ninth embodiment.

FIG. 15 is a schematic cross-sectional view of the semiconductor device of the ninth embodiment, which is a cross-sectional view focusing on a cut along the line II in FIG. 14;

FIG. 16 is a manufacturing process diagram for describing an example of a method for manufacturing a semiconductor device of the ninth embodiment.

FIG. 17 is a manufacturing step diagram illustrating an example of a method for manufacturing a semiconductor device according to the ninth embodiment, following FIG. 16;

18A and 18B are explanatory diagrams of an example of a semiconductor memory device to which the semiconductor element of the present invention is applied, wherein FIG.
(B) is an explanatory diagram of a decoder.

FIG. 19 is an explanatory view (1) of a problem.

FIG. 20 is an explanatory view (2) of the problem.

FIG. 21 is an explanatory view (3) of the problem.

[Explanation of symbols]

11: Semiconductor base (silicon substrate) 13: Device isolation insulating film (field insulating film) 15: Active region 17: Gate insulating film 19: Gate electrode 21: Upper surface insulating film 23: Side wall insulating film 25a, 25b: Diffusion layer 25x: Low impurity concentration diffusion layer 27: Interlayer insulating film 29a, 29b: Contact hole 31a, 31b: Wiring 31aa, 31ba: First metal 31ab, 31bb: Second metal 31x, 31y: Wiring made of high melting point metal 41: inner wall film for narrowing the opening size of the contact hole

Claims (26)

[Claims] 1. A gate electrode having a side wall and an upper surface covered with an insulating film, diffusion layers formed on respective semiconductor base portions on both sides of the gate electrode, and the gate electrode for connecting a wiring to the diffusion layer. A semiconductor element having contact holes formed on both sides thereof, wherein a first gap formed between the gate electrode and each of the contact holes on both sides thereof; A semiconductor element having a first margin, which is a wiring margin formed so as to extend in a gate length direction and be equal to or less than the first interval. 2. The semiconductor device according to claim 1, wherein the first interval is determined in consideration of processing accuracy in a manufacturing process and a minimum distance capable of securing electrical insulation required for the semiconductor device. A semiconductor element having a value equal to or less than a value according to a determined design standard. 3. The semiconductor device according to claim 1, wherein said contact hole is formed so that a part thereof overlaps a side wall insulating film of said gate electrode. 4. The semiconductor device according to claim 1, wherein the first margin is set to 0 or negative. 5. The semiconductor device according to claim 1, wherein a plurality of the contact holes are formed on both sides of the gate electrode and along the gate width direction. Wherein the contact hole is formed so as to face the contact hole on the other side. 6. The semiconductor device according to claim 1, wherein an inner wall film for narrowing an opening dimension of the contact hole to a dimension smaller than a resolution limit by a lithography technique is provided on an inner wall of the contact hole. Semiconductor element. 7. The semiconductor device according to claim 1, wherein the wiring is a wiring in which a portion inside the contact hole and a portion outside the contact hole are made of different materials. . 8. The semiconductor device according to claim 7, wherein a wiring portion in said contact hole is made of a refractory metal. 9. The semiconductor device according to claim 1, wherein said wiring is made of a refractory metal. 10. The semiconductor device according to claim 1, wherein the diffusion layer is a diffusion layer having a low impurity concentration at least in an edge portion in contact with an element isolation region. 11. The semiconductor device according to claim 10, wherein the diffusion layer is a diffusion layer having a high impurity concentration in a portion facing a contact hole. 12. The semiconductor device according to claim 1, wherein the contact hole has a rectangular planar shape having a long side in a gate width direction, and a dimension of the long side is equal to a dimension of the active region. A semiconductor element, wherein the contact holes are substantially equal. 13. The semiconductor device according to claim 1, wherein a second margin, which is a margin of the contact hole with respect to an active region, is smaller than an amount of misalignment expected in a lithography technique. A semiconductor element, wherein the high impurity concentration portion is a diffusion layer formed in a self-aligned manner with respect to the contact hole. 14. The semiconductor device according to claim 13, wherein the second margin is set to 0 or negative (a state in which a part of a contact hole is located on an element isolation region). . 15. A semiconductor memory device comprising a memory cell array, a row decoder and a column decoder, wherein one or both of the decoders include a switching element included therein. A semiconductor memory device comprising a decoder comprising elements. 16. A gate electrode having side walls and an upper surface covered with an insulating film, a diffusion layer formed on a semiconductor base portion on each side of the gate electrode, and the gate electrode for connecting a wiring to the diffusion layer. In manufacturing a semiconductor device having contact holes formed on both sides, the contact holes are formed such that a first space is formed between the gate electrode and each of the contact holes on both sides thereof. Forming a wiring such that a first margin, which is a wiring margin extending in a gate length direction of the wiring with respect to the contact hole, is equal to or less than the first interval. . 17. The method for manufacturing a semiconductor device according to claim 16, wherein the first interval is determined by a processing accuracy in a manufacturing process and a minimum distance capable of securing electrical insulation required for the semiconductor device. A method of manufacturing a semiconductor device, wherein the contact hole is formed so as to have a value equal to or less than a value according to a design standard determined in consideration. 18. The method for manufacturing a semiconductor device according to claim 16, wherein said contact hole is formed by a method (self-aligned contact technique) which allows a part of said contact hole to overlap on a sidewall insulating film of said gate electrode. A method for manufacturing a semiconductor device, comprising: 19. The method of manufacturing a semiconductor device according to claim 16, wherein the wiring is formed such that the first margin is 0 or negative. 20. The method according to claim 16, wherein an insulating film is formed on the entire surface of the wafer including the inside of the contact hole after forming the contact hole and before forming the wiring. Forming an inner wall film on the inner wall of the contact hole by removing the formed insulating film by an anisotropic etching technique so as to reduce an opening dimension of the contact hole to a size smaller than a resolution limit by a lithography technique. A method for manufacturing a semiconductor device. 21. The method of manufacturing a semiconductor device according to claim 16, wherein the wiring includes a first step of forming a wiring portion made of a first metal in the contact hole, and forming the wiring portion outside the contact hole. Forming a wiring portion made of a second metal that can be selectively etched with respect to the first metal. 22. The method of manufacturing a semiconductor device according to claim 16, wherein the wiring is formed using a refractory metal as a constituent material. 23. The method of manufacturing a semiconductor device according to claim 16, wherein the diffusion layer is formed by implanting impurities using the gate electrode before forming an element isolation insulating film and a sidewall film as a mask.
And a second step of implanting an impurity through the contact hole after the formation of the contact hole and before the formation of the wiring. 24. The method of manufacturing a semiconductor device according to claim 16, wherein, when forming the contact hole, a second margin, which is a margin with respect to an active region, is set to be smaller than an amount of misalignment expected in lithography. Forming a high impurity concentration portion of the diffusion layer after forming the contact hole by implanting an impurity through the contact hole. 25. The method for manufacturing a semiconductor device according to claim 24, wherein the second margin is set to 0 or negative. 26. The method for manufacturing a semiconductor device according to claim 16, wherein the contact hole is formed after performing a planarization process on an insulating film for forming the contact hole. Semiconductor device manufacturing method.