JPH1092959A - Double-layer polycrystalline silicon eeprom - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a one type double-layer polycrystalline silicon EEPROM in which a structure composed of an oxide thin film layer, a nitro compound thin film layer and an oxide thin film layer (0/N/0 thin film structure) is provided between a selection gate electrode and a control gate electrode. SOLUTION: An EEPROM(electrically erasable and programmable ROM) has a MONOS structure made of metal, oxide, nitro compound, oxide and semiconductor. In the EEPROM, a selection gate electrode 7 is formed on a substrate 1, a thin film multilayer (0/N/0 film layer) composed of an oxide thin film layer, a nitro compound thin film layer and an oxide thin film layer is formed on the selection gate electrode 7, a control gate electrode 15 is formed on the 0/N/0 film layer and a lightly-doped drain electrode(LDD) is formed between a drain electrode and a channel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a kind of EEPRO
In particular, the present invention relates to an M (Epirom. Electrically erasable ROM), and more particularly to a MON comprising a kind of double-layered polysilicon, metal, oxide, nitrate, oxide, and semiconductor.
OS (metal / oxide / nitride / o
The present invention relates to an EEPROM having an xide / semiconductor structure.

[0002]

2. Description of the Related Art There are four types of memories depending on the purpose of use.
Are classified into two types. It is an electrically changeable ROM
(Electrically alterable R
OM; EAROM), electrically erasable ROM (el
electrically erasable progr
ammablc ROM; EEPROM), EEPROM
An M-EAROM and a static RAM (SRAM) which is a nonvolatile memory. Different devices have already been developed and are serving different demands.

[0003] Basically, all of the above memories are Fow.
The ler-Nordheim tunnel is used. F
The Owler-Nordhejm tunnel is a conduction band in which carriers penetrate a potential barrier of interfacial energy between silicon and silicon oxide and enter an oxide. 1970
Early EAROMs used metal, nitrates and silicon as the gate pole region of p-type channel memory cells. When one voltage was applied to the gate electrode, carriers penetrated the thin silicon oxide layer, and the carriers fell into the oxide-nitride interface. The double-layer polysilicon ROM has one MONOS (metal / ox)
Ide / nitride / semiconductor
r) Transistor and one select transistor (cell
cttransistor). In erase mode, one positive voltage is applied to the source and drain poles, and the substrate and gate are grounded; conversely, in programming mode, one negative voltage is applied to the gate pole and the source and drain The pole is grounded.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a kind of double-layer polysilicon EEPROM. In particular, the structure of the present invention comprises an oxide thin film layer, a nitride thin film layer and an oxide thin film. It is assumed that a layered structure (O / N / O thin film structure) is interposed between a select gate electrode (select gate) and a control gate electrode (control gate).

[0005]

According to a first aspect of the present invention, there is provided a MONOS (metal / oxide) comprising two layers of polysilicon, a metal, an oxide, a nitride, an oxide, and a semiconductor.
e / nitride / oxide / semicond
a type of EEPROM (el
electrically erasable progr
an electrically erasable ROM (electrically erasable ROM) including a drain electrode and a gate electrode doped region formed between a field oxide layer and a gate oxide layer formed on a substrate to form an insulating layer. A select gate electrode formed on the gate oxide layer to isolate the gate oxide layer and the carrier channel; and a dielectric layer formed on the select gate and the carrier channel to store charge. A control gate pole formed on the dielectric layer and used to control the state of the EEPROM;
And a two-layer polysilicon EEPROM.

According to a second aspect of the present invention, there is provided a double-layer polysilicon EEPROM according to the first aspect, wherein the oxide includes:
Double-layer polysilicon E with a composite layer of nitrates and oxides formed in the soil of the select gate electrode and carrier channel
EPROM.

According to a third aspect of the present invention, there is provided a double-layer polysilicon EEPROM according to the first aspect, wherein the selection gate electrode is made of polysilicon.

According to a fourth aspect of the present invention, there is provided a double-layer polysilicon EEPROM according to the first aspect, wherein the gate oxide layer is composed of silicon dioxide.
It is a PROM.

According to a fifth aspect of the present invention, there is provided a double-layer polysilicon EEPROM according to the first aspect, wherein the dielectric layer is composed of a composite layer made of an oxide, a nitride, and an oxide.
It is a two-layer polysilicon EEPROM.

According to a sixth aspect of the present invention, there is provided a double-layer polysilicon EEPROM according to the first aspect, wherein the control gate electrode is composed of a polysilicon layer.
EPROM.

According to a seventh aspect of the present invention, there is provided the double-layer polysilicon EEPROM according to the first aspect, further comprising a lightly doped drain electrode (lightly doped drain;
LDD), double-layer polysilicon EEPRO
M.

An eighth aspect of the present invention is a method for forming a double-layer polysilicon EEPROM on a semiconductor substrate, wherein the first silicon dioxide layer is formed on the semiconductor substrate,
Forming a polysilicon layer on the first silicon dioxide layer, defining a first photoresist on the first polysilicon layer, etching the first polysilicon layer and the first silicon dioxide layer to select gate electrode and gate; Forming an oxide, forming a second silicon dioxide layer on the select gate electrode and the substrate, etching the second silicon dioxide layer to form sidewall spacers;
The lightly doped drain electrode (light
ly doped drain (LDD), remove sidewall spacers, form a dielectric layer on the select gate electrode and the substrate, form a second polysilicon layer on the dielectric layer, and form a second photoresist. A dual-polysilicon EEPROM, defined above the second polysilicon layer, wherein the second polysilicon layer and the dielectric layer are etched and doped with impurities to form drain and source poles. Manufacturing method.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a two-layer polysilicon EEPROM according to the eighth aspect, wherein the dielectric layer is composed of a composite layer made of an oxide, a nitride, and an oxide. This is a method for manufacturing a two-layer polysilicon EEPROM.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a two-layer polysilicon EEPROM according to the ninth aspect, wherein the thickness of the composite layer comprising the oxide, the nitride and the oxide is 200 to 300. Angstrom, a method of manufacturing a two-layer polysilicon EEPROM.

According to an eleventh aspect of the present invention, there is provided a method of manufacturing a two-layer polysilicon EEPROM according to the eighth aspect, wherein the first polysilicon layer is used for forming a select gate electrode. Manufacturing method.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a two-layer polysilicon EEPROM according to the eighth aspect, wherein the second polysilicon layer is used for forming a control gate electrode. Manufacturing method.

[0017]

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a two-layer polysilicon EE.
A PROM is provided, the structure of which is metal,
M consisting of oxide, nitrate, oxide, and semiconductor
It has an ONOS structure. In the EEPROM (E-PROM, electrically erasable ROM) of the present invention, a select gate electrode is formed on a substrate, and an oxide, a nitrate, and an oxide film layer (O / N / O film layer) are formed. Formed on the select gate pole,
A control gate electrode is formed on the O / N / O film layer, and a lightly doped drain electrode (LDD) is formed between the drain electrode and the channel.

The EEPROM of the present invention includes a select gate electrode, the select gate electrode is located on an element channel, the length of the select gate electrode is shorter than the length of the channel, and the O / N
A portion of the / O thin film structure covers the device channel, the control gate electrode is formed on the O / N / O thin film structure, and a lightly doped drain electrode (LLD) is provided between the drain electrode and the channel. Is formed. EEPROM of the present invention
This structure is used for a relatively thick tunnel oxide layer, provides relatively good data storage, and requires only low operating voltages. In addition, the present invention has a relatively strong anti-radiation property and can be applied to military use.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The double-layer polysilicon E of the present invention shown in FIG.
EPROMs include a drain pole and a source pole formed in a doped region of the device. Lightly doped drain (LDD1
1) is formed between the drain electrode and the channel, and is used to reduce the hot carrier effect near the drain electrode contact surface and reduce the high electric field. Also, a single silicon dioxide layer 5 is formed over the device channel and is used to form the gate oxide 5 and isolate the gate electrode and the carrier channel. The select gate electrode 7 is formed on the gate oxide 5, and the select gate electrode 7 is composed of the first polysilicon layer 7. One composite layer 13 is formed on the select gate electrode 7, and the composite layer 13 has a structure (O / N / O) composed of an oxide thin film layer, a nitride thin film layer, and an oxide thin film layer.
Thin film structure) and is used for storing electric charges. Part of the composite layer 13 is formed on the select gate electrode 7 and part is formed on the channel of the carrier. Further, one control gate electrode 15 is disposed along the composite layer 13 along the composite layer 13.
The control gate electrode 15 is formed of a second polysilicon layer.

The programming mode (programmm
In the ing mode, hot carriers permeate through the channel into the composite layer 13 having an O / N / O thin film structure,
The hot carriers are captured by the composite layer 13 and fall into the composite layer 13. At this time, a negative voltage is applied to the control gate, the control gate and the drain, and the source is grounded. In the erase mode, carriers are released from the composite layer 13 and reach the drain electrode. At this time, a positive voltage is applied to the drain electrode, and the select gate electrode 7 is turned off. In this state, carriers do not flow in the channel, and a negative voltage is applied to the select gate electrode 7. EEPROM of the present invention
Is used for relatively thick tunnel oxide layers, making it perform relatively well, and requires only low operating voltages. In addition, the present invention has a relatively strong anti-radiation property and can be applied to military use.

The method of manufacturing the EEPROM of the present invention is as follows. As shown in FIG. 2, the crystal plane is (10
0) is used as a semiconductor substrate 1 and a field oxide region 3
Is formed on the semiconductor substrate 1 to form an insulating layer for isolating the active region. The in-situ oxide layer region 3 is formed by forming a composite layer of silicon nitride and silicon dioxide by lithography and dry etching steps, followed by removing the photoresist, carefully wet-etching and drying, and then placing it in an oxygen vapor environment. A thermal oxidation treatment is performed, and a temperature of about 850 ° C. to 105
The silicon dioxide is generated between 0 ° C., and the thickness of the in-situ oxide layer region 3 is set to 4000 Å to 6000 Å. Further, the nitrated silicon layer is removed with hot phosphoric acid, the silicon dioxide layer is removed with a hydrofluoric acid solution, and the mask of the composite layer of this oxide is removed.
Furthermore, the region of in-situ oxidation is set to about 850 ° C.
To 1000 ° C. and a thickness of 150 Å to 350 Å, forming a first insulating layer 5. This oxide layer is used to form the gate oxide 5.

Subsequently, a first polysilicon layer 7 is formed on the first insulating layer. A photoresist is defined on the first polysilicon layer 7, and thereafter, the first polysilicon layer 7 and the first insulating layer are etched by using an etching technique, thereby forming the select gate electrode 7 and the gate oxide 5. . afterwards,
The photoresist is removed with a sulfuric acid solution. The first polysilicon layer 7 is formed by using a chemical vapor deposition method and has a thickness of 20.
00 angstrom. First polysilicon layer 7
May be made by further doping the polysilicon layer with impurities, or by using already doped polysilicon (in
-Situ doped polysilicon).

As shown in FIG. 3, a second silicon dioxide layer 9 is formed over the select gate electrode 7, gate oxide 5 and field oxide layer area 3. The above-mentioned second silicon dioxide layer 9 is etched by non-directional dry etching, so that the side wall spacer 9 (side-wall) is formed as shown in FIG.
spacer). Oxygen gas can be used for etching ions. Subsequently, an impurity is doped, whereby a lightly doped drain (lightly doped drain) is formed.
drain (LDD) 11 is formed, and then the sidewall spacers 9 are removed by wet etching.

Further, as shown in FIG. 5, one dielectric layer 13 is formed on the select gate electrode 7 and the substrate 1. The dielectric layer 13 has a structure including an oxide thin film layer, a nitride thin film layer, and an oxide thin film layer (O / N / O thin film structure), and is used for storing electric charges. The thickness of the dielectric layer 13 is 200 to 300 angstroms. Subsequently, a second polysilicon layer 15 is formed on the dielectric layer 13. The second polysilicon layer 15 is used for forming a control gate electrode. A photoresist is defined on the second polysilicon layer 15, and then the second polysilicon layer 15 and the composite layer 13 are etched by an etching technique, so that the control gate electrode 15 and the composite layer 1 are etched.
3 is formed, and then the photoresist is removed.

As shown in FIG. 7, impurities are introduced into the substrate 1 by ion implantation and heat treatment to form a drain electrode and a gate electrode which are relatively heavily doped with impurities. Finally, the EEPROM of the present invention is completed.

[0026]

The EEPROM of the present invention includes a select gate electrode, which is located on the device channel,
The length of the select gate pole is shorter than the length of the channel, and O /
A portion of the N / O thin film structure covers the device channel, the control gate electrode is formed on the O / N / O thin film structure, and a lightly doped drain electrode (LLD) is formed between the drain electrode and the channel. Is formed. EEPRO of the present invention
The M structure is used for a relatively thick tunnel oxide layer, provides relatively good data storage, and requires only low operating voltages. In addition, the present invention has a relatively strong anti-radiation property and can be applied to military use.

[Brief description of the drawings]

FIG. 1 is a sectional view of the present invention.

FIG. 2 is a cross-sectional view showing a control gate electrode formation and gate oxide formation step of the present invention.

FIG. 3 is a sectional view showing a step of forming a silicon dioxide layer on a control gate electrode according to the present invention.

FIG. 4 is a sectional view showing a step of forming a lightly doped drain electrode (LDD) of the present invention.

FIG. 5 is a sectional view showing a structure (O / N / O thin film structure) comprising an oxide thin film layer, a nitride thin film layer and an oxide thin film layer of the present invention and a step of forming a polysilicon layer on a control gate electrode. is there.

FIG. 6 is a sectional view showing a control gate electrode forming step of the present invention.

FIG. 7 is a cross-sectional view of a step of forming a doped drain electrode and a source electrode according to the present invention.

[Explanation of symbols]

5 ... silicon dioxide layer or gate oxide or
1st insulating layer 7 1st polysilicon layer or selection gate electrode 13 composite layer 15 2nd polysilicon layer or control gate electrode 1 substrate 3 field oxide layer region 9 ... Second silicon dioxide layer or side wall spacer

Claims (12)

[Claims] Claims 1. A two-layer polysilicon, metal, oxide,
MONOS composed of nitrates, oxides and semiconductors (me
tal / oxide / nitride / oxide /
a kind of E having a semiconductor structure
EPROM (electrically erasab
le programmable ROM (electrically erasable ROM), which is formed between a field oxide layer in a drain electrode and a gate electrode doping region, and is formed on a substrate as a gate oxide layer to form an insulating layer. And a select gate electrode formed on the gate oxide layer and separating the gate oxide layer and the carrier channel; and a dielectric layer formed on the select gate and the carrier channel and storing charge. A storage gate and a control gate electrode, formed in the soil of the dielectric layer and the EEP
A double-layer polysilicon EEPROM, including: one used to control the state of the ROM. 2. The double-layer polysilicon EE according to claim 1.
PROM, a double-layer polysilicon EEPROM in which a composite layer of the oxide, nitrate, and oxide described above is formed over a select gate electrode and a carrier channel. 3. The double-layer polysilicon EE according to claim 1,
A two-layer polysilicon EEPROM, wherein the select gate electrode is comprised of polysilicon. 4. The double-layer polysilicon EE according to claim 1.
A PROM, wherein the gate oxide layer is comprised of silicon dioxide, a two-layer polysilicon EEPROM. 5. The double-layer polysilicon EE according to claim 1,
In a PROM, wherein the dielectric layer comprises oxides, nitrates,
A two-layer polysilicon EEPROM composed of a composite layer made of an oxide. 6. The double-layer polysilicon EE according to claim 1, wherein:
A two-layer polysilicon EEPROM, wherein the control gate electrode is comprised of a polysilicon layer. 7. The double-layer polysilicon EE according to claim 1, wherein:
In PROM, a lightly doped drain electrode (lig)
A double-layer polysilicon EEPROM, including HTLY doped drain (LDD). 8. A type of double-layer polysilicon EEPROM.
Forming a first silicon dioxide layer on the semiconductor substrate, forming a first polysilicon layer on the first silicon dioxide layer, and forming a first photoresist on the first polysilicon layer. Etching the first polysilicon layer and the first silicon dioxide layer to form a select gate electrode and a gate oxide; and forming a second silicon dioxide layer on the select gate electrode and the substrate. Etching the second silicon dioxide layer to form sidewall spacers and doping impurities to form a lightly doped drain electrode (light);
ly doped drain (LDD), removing a sidewall spacer, forming a dielectric layer on the select gate electrode and the substrate, forming a second polysilicon layer on the dielectric layer, and forming a second photoresist. Defining the second polysilicon layer, etching the second polysilicon layer and the dielectric layer, and doping impurities to form a drain electrode and a source electrode; Production method. 9. The double-layer polysilicon EE according to claim 8.
A method of manufacturing a PROM, wherein the dielectric layer is composed of a composite layer comprising an oxide, a nitride, and an oxide. 10. The double-layer polysilicon E according to claim 9,
In the method of manufacturing an EPROM, the thickness of the composite layer composed of the above-mentioned oxide, nitrate and oxide is 200 to 30.
Double-layer polysilicon EEPR with 0 Å
OM manufacturing method. 11. The double-layer polysilicon E according to claim 8, wherein
A method for manufacturing a two-layer polysilicon EEPROM, wherein the first polysilicon layer is used for forming a select gate electrode. 12. The double-layer polysilicon E according to claim 8,
A method for manufacturing a two-layer polysilicon EEPROM, wherein the second polysilicon layer is used to form a control gate electrode.