JPH1091906A - Acoustic signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reproduce an acoustic signal at the time of reproducing it with slow motion by using a memory small in capacity. SOLUTION: A memory 5 is accessed in an annular state where the maximum value and the minimum value of an address value are connected. When the acoustic signal stored in a memory 5 is compressed in the base, its pitch is converted, and the signal is read out, and a writing address value is matched with a specific address value out of plural specific address values, a read-out address value is changed to an address value near the writing address value also, two read-out address counters 18, 19 are used in a period in which the read-out address value being varied by counting operation after that overtakes the writing address value. A signal level of a read out acoustic signal is gradually raised as variation of a read-out address value after a read-out address value is changed to an address near a writing address, and the acoustic signal is synthesized from a memory in a state in which a signal level of an acoustic signal is gradually reduced as variation of a read-out address value in a part near the front until a read-out address value overtakes a writing address value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal processing apparatus for converting a pitch of an audio signal while compressing the audio signal on a time axis.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus such as a magnetic tape recorder or a video tape recorder (VTR), a recorded magnetic tape is run at a running speed different from the running speed of a magnetic tape during recording to perform a reproducing operation. May be performed. That is, for example, the traveling speed of the magnetic tape of the magnetic tape recorder at the time of reproduction is made slower than the traveling speed of the magnetic tape at the time of recording, and the document is created while listening to the contents of the conversation reproduced from the magnetic tape. For example, in a VTR, when reproducing a recorded information from a recorded magnetic tape on which a video signal and an information signal such as an audio signal accompanying the video signal are recorded, a magnetic tape during a recording operation is used. The playback speed is higher than the running speed (so-called high-speed playback), so that the image content recorded on the magnetic tape can be confirmed within a shorter time than the time required for recording the image. Or reproduce at a running speed lower than the running speed of the magnetic tape during the recording operation (so-called slow-motion playback) to check the image content. Or to allow bets have come widely performed conventionally.

However, as described above, in a state where the running speed of the magnetic tape during the reproducing operation is made different from the running speed during the recording operation, the acoustic signal reproduced from the magnetic tape when the magnetic tape is running, The original audio signal recorded on the magnetic tape is an audio signal in which the pitch and time length of the audio signal have changed, corresponding to the ratio of the running speed of the magnetic tape during the reproducing operation and the recording operation. I have. If the sound signal in which the pitch has changed as described above (the sound signal in a state in which the pitch has been converted) remains, the information content may not be grasped. Therefore, when the video signal and the information signal such as an audio signal accompanying the video signal are recorded at high speed by a VTR, the time axis compression reproduced from the magnetic tape is performed. Signal obtained by intermittently elongating the reproduced sound signal in the divided state at predetermined time intervals to obtain a continuous reproduced sound signal in a state where the pitch is returned to the pitch of the original sound signal. 2. Description of the Related Art A video / audio reproducing apparatus provided with a processing unit has been conventionally proposed.

On the other hand, when the VTR is performing a slow motion reproducing operation, of the audio signals reproduced from the VTR, the audio signal is reproduced from an audio track provided on the edge of the magnetic tape in the longitudinal direction of the magnetic tape. Sound signal
Since the running speed of the magnetic tape is slower than the running speed at the time of recording, the reproduced sound signal becomes a reproduced sound signal in a state where the time axis is extended as shown in FIG. It will be difficult. FIG. 5A is a diagram showing a model of an acoustic signal at the time of recording, and FIG. 5B is a graph showing the running speed of the magnetic tape during the reproducing operation and the running speed of the magnetic tape during the recording operation. FIG. 4 is a diagram showing a modeled reproduction audio signal in the case of 1/3. In the drawing, Z1, Z2, etc. are reference numerals attached for convenience of explanation. [Z1, Z2,... In FIG. 5 are blocks of audio signals for each unit time T in the original audio signal (the audio signals are divided. Area of the configured unit)].

However, as shown in FIG. 5 (b), the original acoustic signal shown in FIG. 5 (a) is expanded three times in time axis [in FIG. 5 (a). . May be compared with the audio signal blocks (unit areas) Z1, Z2,... Shown in FIG. 5B. FIG. 5 (c) shows a reproduced sound signal having a pitch lower than the signal pitch, which is compressed to 1/3 on the time axis to return the pitch to the pitch of the original sound signal. As shown, since only an intermittent reproduced sound signal in which the signal period and the no-signal period are alternately obtained, the signal period and the silence period are different from the contents of the acoustic signal (for example, the contents of conversation). Is caused by irrelevance, so it sounds very hard to hear That. Therefore, when the VTR is performing the slow motion reproducing operation, the audio signal reproduced from the VTR is generally muted so that the audio signal is not output.

[0006]

However, in recent years, various tracking means have been put into practical use, so that even if the reproducing operation is performed by running the magnetic tape at a running speed different from that at the time of the recording operation, noiseless operation is performed. Along with the fact that high-quality slow-motion playback images can be easily obtained in this state, even during slow-motion playback, the audible state obtained by converting the pitch of the sound signal attached to the slow-motion playback image can be heard. If you add the sound of
It has come to be considered that the atmosphere is also favorable. Conventionally, as disclosed in, for example, Japanese Patent Application Laid-Open No. 60-4997, a reproducing operation has been performed at a tape traveling speed lower than that during a recording operation, and a state in which the original acoustic signal is expanded in time axis. When the reproduced sound signal reproduced as the original sound signal is continuously stored in the memory, and the read operation from the memory reads out the reproduced sound signal having the same pitch as the original sound signal in a time-axis compressed state, the sound By reading back the read start address of the signal block little by little, the signal-free period as shown in FIG. There has been proposed an audio signal processing device capable of obtaining a reproduced audio signal.

The above-described conventional audio signal processing apparatus has a large storage capacity so that the pitch conversion operation can be performed smoothly since the time length of the audio signal block is undefined. Memory is required. By the way, as a recent tendency regarding the manufacturing technology of this kind of electronic equipment, a configuration in which a signal processing circuit and a memory are incorporated into a one-chip large-scale integrated circuit has been often adopted. In a configuration of a conventional acoustic signal processing device, since a signal processing circuit and a memory cannot be configured as a one-chip large-scale integrated circuit, a predetermined pitch conversion can be performed by a memory having a small storage capacity. The appearance of an acoustic signal processing device having such a configuration has been expected.

[0008]

According to the present invention, a signal processing is performed on a memory in which access to a storage area of the memory is performed in a circular state in which a maximum value and a minimum value of a memory address value are continuous. Means for continuously writing the target audio signal, and means for reading the audio signal stored in the memory as an audio signal whose pitch has been converted by time axis compression. In the acoustic signal processing device, when a write address value matches one specific address value among a plurality of specific address values set at predetermined intervals in all address areas of the memory, The read address value is changed to an address value near the write address value of the write address value, and the read address value that changes by the subsequent counting operation is close to the write address value. A first read address counting means for performing a read address value counting operation during the period, and the first read address counting means for performing a read address value counting operation while the first read address counting means performs a read address value counting operation. Read address counting means, when the write address value matches another specific address value different from the specific address value whose read address value has been changed, corresponds to the other specific address value described above. While the read address value is changed to an address value near the write address value, and the read address value changed by the subsequent count operation is close to catching up with the write address value, the read address value counting operation is performed. The read address value in the second read address counting means for performing the As the read address value is changed by the counting operation after the address value is changed to an address value near the read address value, the signal level of the acoustic signal read corresponding to the read address value is gradually increased. The signal level of the acoustic signal read corresponding to the read address value as the read address value changes in a portion near the front until the read address value reaches a portion following the write address value by the counting operation of the counting means. , And means for synthesizing an acoustic signal read from the memory corresponding to the read address generated by the counting operation by the first and second read address counting means. An acoustic signal processing device is provided.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific contents of an audio signal processing device according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram of an acoustic signal processing device of the present invention,
2 and 3 are diagrams for explaining the operation of the acoustic signal processing device of the present invention, and FIG. 4 is a waveform diagram for explaining the operation.
In the audio signal processing apparatus of the present invention shown in FIG. 1, 1 is an input terminal of an audio signal, 2 is an output terminal, 3 is a low-pass filter, 4 is an analog-to-digital converter, 5 is a memory, and 6,7.
Is an operation unit, 8 and 9 are data holding units, 10 is an addition unit, 11
Is a digital-to-analog converter, 12 is a low-pass filter, 1
3 is a control unit, 14 is a write address counter, 15 is a frequency divider, 16 is a detection unit, 17 is a timing signal generation unit,
8 and 19 are read address counters, and 20 is a selection circuit. In the control unit 13, various control signals required for the operation of each component of the acoustic signal processing device, for example,
Write clock signal WCK, read clock signal RC
K, memory read / write selection signal RW, memory control signal CS, AD conversion signal ADCK, and DA conversion signal D
ACK, an address selection signal S, etc. are generated.

In the audio signal processing apparatus of the present invention shown in FIG. 1, an input signal to be subjected to audio signal processing, for example, recording information based on an audio signal recorded on a magnetic tape by a recording / reproducing apparatus is required at the time of recording. (For example, the reproduction time at 1 / N times speed is N times the recording time).
A time-axis-extended acoustic signal obtained by reproduction at (times twice) is supplied to the low-pass filter 3 described above. The low-pass filter 3 functions as an anti-aliasing filter for the analog-to-digital conversion operation in the analog-to-digital converter 4 used in the subsequent circuit. The time-axis-extended acoustic signal in a state in which the band is limited by the low-pass filter 3 is supplied to an analog-to-digital converter 4. In the analog-to-digital converter 4, a control unit 13 is provided.
Is converted into a digital signal (digital data) having a predetermined number of bits in each predetermined sampling period based on the AD conversion pulse ADCK given by And gives it to the memory 5. The memory 5 is configured to access the storage area in an annular state in which the maximum value and the minimum value of the address value are continuous, and the memory 5 is set to be subjected to signal processing. Digital data based on the sound signal is continuously written at a constant writing speed on the time axis.

In the following description, digital data is written to the memory 5 when the memory read / write selection signal RW is at a low level and the memory control signal CS is at a high level. Digital data is read from the memory 5 when the memory read / write selection signal RW is at a high level and the memory control signal CS is at a high level. Note that the writing of digital data to the memory 5 and the reading of digital data from the memory 5 are performed on a storage area specified by the address signal ADR supplied to the memory 5 via the selection circuit 20. Needless to say. The address signal ADR supplied to the memory 5 includes a write address signal WAD output from the write address counter 14 and a first read address output from the first read address counter 18 as described later. Signal RAD1
And the second read address signal RAD2 output from the second read address counter 19, and the address signal selected by the selection circuit 20.

Referring to FIG. 4 for describing the timing relationship between the write operation and the read operation in memory 5, W
CK is a write clock signal, RCK is a read clock signal, CS is a memory control signal, RW is a memory read / write select signal, and ADR is an address signal. FIG.
Describes a write clock signal WCK and a read clock signal RCK in which the cycle of the write clock signal WCK is three times as long as the cycle of the read clock signal RCK, which is performed in the following description in the specification. The description of the embodiment of the audio signal processing apparatus according to the present invention is based on the assumption that the audio signal to be processed is operating the VTR in the 1/3 slow motion (1 / 3x speed) playback mode. This is because the audio signal is reproduced when the audio signal is reproduced from the VTR.

The sound signal processing apparatus according to the present invention has an annular state in which the maximum value and the minimum value of the address value are continuous.
For the memory 5 that accesses the storage area,
When the sound signal to be subjected to the signal processing is continuously written, and the sound signal stored in the memory 5 is read out as the sound signal whose pitch has been converted by time axis compression, the memory 5 2, a plurality of specific address values [FIG. 2]
A1, A2... A6] in (a) above, when the write address value matches one specific address value (for example, A1) (for example, t2), the address value near the write address value (for example, t2) For example, in A1), the read address value is changed (for example, the read address value is changed to A1 at point ヲ), and the read address value that changes by the subsequent counting operation follows the write address value. (It is at time t5 that the read address value catches up with the write address value, and the address value at that time is A4.) A period until the vicinity (point ヲ, point ワ, point カ, point ヨ, point タ) During the period from point to point (d), the first read address counter 18 that performs a read address value counting operation generates a read address signal.

Also, the period during which the first read address counter 18 is generating a read address signal (the period of the point →→ the point ワ the point カ the point ヨ the point ヨ the point タ the point レ the point レ) ), The write address value matches another specific address value (A3) that is different from the specific address value (A1) from which the first read address counter 18 has started generating the read address signal. Time (t4)
In addition, an address value (for example, A3) near a write address value corresponding to the other specific address value (A3) described above,
While the read address value is changed (for example, the read address value is changed to A3 at the point of S), the read address value changing by the subsequent counting operation follows the write address value (the read address value is changed to A3). It is at time t7 that catches up with the write address value, and the address value at that time is A6).
A second read address counter 19 for performing a read address value counting operation during a period from point n to point na to point b).
Generates a read address signal.

Further, after the read address value in each of the read address counters 18 and 19 is changed to an address value (A1, A3) near the write address value, as the read address value changes by the counting operation,
The signal levels of the acoustic signals read in correspondence with the read address value are gradually increased by the arithmetic units 6 and 7, and the read address value is added to the write address value by the counting operation of the read address counters 18 and 19. As the read address value changes in a portion near the front before reaching the attached portion, the signal levels of the read audio signals corresponding to the read address value are gradually reduced by the arithmetic units 6 and 7, and A configuration in which sound signals in a state where predetermined operations have been performed by the operation units 6 and 7 are combined and output, and even when the memory 5 having a small storage capacity is used, good pitch conversion can be performed on the sound signals. Therefore, a more specific description will be given below with reference to FIGS. 2 and 3 and the like.

In FIG. 2A, the horizontal axis is time, the vertical axis is the address value of the memory 5, and the lower end of the vertical axis in FIG. 2 corresponds to the minimum address value of the memory 5. The uppermost end of the vertical axis corresponds to the maximum address value of the memory 5. A1, A2, shown on the vertical axis in FIG.
The symbols A3... Indicate predetermined specific address values. The bold solid line WAD in FIG. 2 indicates a change in the write address value, and RAD1 in FIG.
The change in the read address signal (read address value) generated by the read address counter 18 of FIG.
AD2 indicates a change in the read address signal (read address value) generated by the second read address counter 19. In FIG. 2, an audio signal to be subjected to signal processing in the audio signal processing device is reproduced from the VTR when the VTR is operated in the 1/3 slow motion (1/3 speed) reproduction mode. In order to explain the case where the read sound signal is read out as a sound signal in a state where the time axis is compressed to 1/3 by using the memory 5, it is shown as RAD1 and RAD2 in FIG. In this example, the change rate of the read address value on the time axis is three times the change rate of the write address value on the time axis.

By the way, in the acoustic signal processing apparatus of the present invention, the access to the storage area of the memory 5 at the time of the writing operation and the reading operation is performed by the maximum value and the minimum value of the address value of the memory 5 as described above. Are performed in an annular state in which the signal processing is continued, and the acoustic signal to be processed is continuously written in the memory 5 at a constant writing speed on the time axis. The change state on the time axis of the write address value of the memory 5 during the operation of writing the acoustic signal into the memory 5 is indicated by a solid line WA in FIG.
As shown by D, point a at time t1 in FIG.
From point b at time t7 to point c at time t7 → point d at time t13 → point e at time t13 → point to time t17, and so on.
It is represented as a sawtooth waveform having a constant slope with respect to the time axis, and the address value of the memory 5 changes in a ring-like state in which the maximum value and the minimum value are continuous.

In FIG. 2, corresponding to all address areas from the minimum address value of the memory 5 shown at the bottom of the vertical axis to the maximum address value of the memory 5 shown at the top of the vertical axis. The entire storage area of the memory 5 includes a plurality of predetermined specific address values A illustrated in FIG.
At A1, A2, A3,... A6, the area is divided into a plurality (six in the example of FIG. 2). Each area configured by the above-described division is indicated by an area Z1 and an area Z on the time axis in FIG.
2, area Z3 ... area Z6, area Z7, area Z8, area Z
9... Area Z12,. Each of the above-mentioned areas Z1, area Z2, area Z3,... Area Z6, area Z
7, region Z8, region Z9,... Region Z12,... Are mainly used in the following description to indicate the acoustic signals stored in the respective regions.

As described above, the write address signal (write address value) WAD output from the write address counter 14 to which the write clock signal WCK generated by the control unit 13 is supplied is supplied to the frequency divider 15 and the detection unit. 16, read address counters 18 and 19, and a selection circuit 20. In the frequency divider 15, the address signal of the most significant bit of the write address signal output from the write address counter 14 is frequency-divided by 2, and the signal level change mode instruction signal ST [see FIG. 2 (e)]. And supplies it to the timing signal generator 17. Further, the timing signal generator 17 is also supplied with the area boundary instruction signals Pa1, Pa2, Pa3 to Pa6 generated by the detector 16.

The above-mentioned area boundary indication signals Pa1, Pa2, P
a3 to Pa6 are write address counters 1 performing a circular counting operation by continuously setting the maximum value and the minimum value of the count value.
4 (write address value WAD... Write address signal WAD) is a plurality of predetermined specific numerical values (predetermined specific write address values A1, A
2.. A6) are generated by the detection unit 16 at each time point and are supplied to the timing signal generation unit 17. The above point will be specifically described with reference to FIG. That is, the count value of the write address counter 14 (write address value WAD... Write address signal WA)
Assuming that the change mode of D) is as shown by the thick solid line WAD in FIG. 2A, the count value (write address value WAD) of the write address counter 14 is represented by a point ヲ in the figure. At time t2 when a predetermined specific write address value A1 is reached, the detection unit 16
Then, an area boundary instruction signal Pa1 [see (f) of FIG. 2] is generated and supplied to the timing signal generator 17.

Further, the count value (write address value WAD) of the write address counter 14 becomes a predetermined specific write address value A2, as shown by a dot in FIG. At time t3, the detection unit 16 generates an area boundary instruction signal Pa2 [see (g) of FIG.
It is supplied to the timing signal generator 17. further,
At time t4 when the count value (write address value WAD) of the write address counter 14 reaches a predetermined specific write address value A3, as indicated by a dot S in FIG. In the detecting unit 16, the area boundary instruction signal Pa3
[See (h) of FIG. 2] and supplies it to the timing signal generator 17.

In the same manner, the count value (write address value WAD) of the write address counter 14 is previously determined at point (a), point (a), and point (b) in FIG. Specific write address values A4, A
At each of the times t5, t6, and t7 at which the A5 and A6 are reached,
The detector 16 generates the area boundary instruction signals Pa4, Pa5, and Pa6 (see (i), (j), and (k) in FIG. 2) and supplies them to the timing signal generator 17. As described above, the write address counter 14 performs an annular counting operation in which the maximum value and the minimum value of the count value are continuously performed.
The time t8, t9,
Also at t10,... t17, as shown in FIGS. 2 (a), (f) to (k), the detection unit 16 outputs area boundary instruction signals Pa1, Pa2 to Pa6, Pa1, Pa2. The signal is supplied to the timing signal generator 17.

The timing signal generator 17 includes a signal level change mode instruction signal ST (see FIG. 2E) supplied from the frequency divider 15 and an area boundary instruction signal supplied from the detector 16. Pa1, Pa2 to Pa6 [(f) in FIG.
(K)], the preset signal LD1 (or the load signal LD1) shown in FIG.
And the preset signal LD2 shown in FIG.
(Or the load signal LD2), the coefficient signal K1 for changing the signal level shown in FIG. 2B, and the coefficient signal K2 for changing the signal level shown in FIG. 2C.
And generate.

The above-mentioned timing signal generator 1
7, the preset signal LD1 (or the load signal LD1) is supplied to the first read address counter 18, and the preset signal LD2 (or the load signal L1) output from the timing signal generator 17 is provided.
D2) is supplied to the second read address counter 19. The preset signal L from the timing signal generator 17
First read address counter 18 to which D1 is applied
Is the time t when the preset signal LD1 is given to it.
Write address counter 1 for each of 2, t6, t10, t14,.
4 is preset to the write address value supplied to the first read address counter 18. Then, the first read address counter 18 sequentially outputs the read address value each time the read clock signal RCK is applied, with the preset write address value as an initial value.

Each time the preset signal LD1 generated by the timing signal generator 17 is applied at each of the times t2, t6, t10, t14,..., The first read address counter 18
Read address signal (read address value) R
The output operation of the AD1 will be described below by taking the period from time t2 to time t7 as a representative example. At the time t2, the preset signal LD1 is supplied to the first read address counter 18.
, The write address value A1 output from the write address counter 14 at time t2 is preset in the first read address counter 18. From the time t2, the first read address counter 18 sets the address value A1 at the point 時刻 in FIG. 2A as the initial address value A1, and sets the point ヲ → the point ワ → the The sequential read address values RAD1 in the path from the point to the point to the point to the point to the point to the point are sequentially output each time the read clock signal RCK is supplied.

When the preset signal LD1 is given to the first read address counter 18 at times t6, t10, t14,..., The time t6 to t9, the time t10 to the time t13, and the time t14 to the time t17 In each period, the output operation of read address signal (read address value) RAD1 performed by first read address counter 18 is the same as that described in the period from time t2 to time t5, for example, from time t6 to time t6. The first in the period of time t9
The read address counter 18 at the time t6
From FIG. 2A, the address value A5 at point A in FIG. 2A is set as the initial address value A5, and the point of point → point of point → point of u → point of no → point of o → point of ku → ya The sequential read address values RAD1 on the path from the point to the point are sequentially output each time the read clock signal RCK is applied.

For example, in the first read address counter 18 during the period from the time t10 to the time t13, the address value A3 at point S in FIG. 2A from the time t10 is set as the initial address value A3. , A point → a point → a point → a point → a point → a point d.
K is sequentially output each time K is given.
In the first read address counter 18 during the period from the time t14 to the time t17, the address value A1 at the point in FIG.
As 1, the sequential read address value RAD1 in the path from the point to the point to the point to the point to the point to the point to
Each time the read clock signal RCK is applied, it is sequentially output.

The second read address counter 19 to which the preset signal LD2 is supplied from the timing signal generator 17 is supplied from the write address counter 14 every time t4, t8, t12, t16... The write address value supplied to the second read address counter 19 is preset. Then, the second read address counter 19 outputs a sequential read address value each time the read clock signal RCK is applied, using the preset write address value as an initial value.

Each time the preset signal LD1 generated by the timing signal generator 17 is applied at each of the times t4, t8, t12, t16,...
Read address signal (read address value) R
The output operation of the AD2 will be described below by taking the period from time t4 to time t7 as a representative example. At the time t4, the preset signal LD2 is supplied to the second read address counter 19.
Is given, the write address value A3 output from the write address counter 14 at time t4 is preset in the second read address counter 19.

Then, the second read address counter 1
9, when the preset signal LD2 is generated from the timing signal generator 17 at the time t4 as shown in FIG. 2 (m) from the time t4 and is supplied to the second read address counter 19, 2 at the time t4 when the preset signal LD2 is given, the write address value A3 output from the write address counter 14 at that time is preset, and the second read address is read from the time t4. Counter 19
Is the address value A3 at point S in FIG. 2 (a) as the initial address value A3, and the path from point S to point T, point N, point N, and point B is sequentially determined. Are sequentially output each time the read clock signal RCK is applied.

When the preset signal LD2 is given to the second read address counter 19 at times t8, t12, t16,..., The times t8 to t11, t12 to t15, t16 to (FIG. In each period of time t19) not shown in the figure, a read address signal (read address value) RA
The output operation of D2 is the same as that described for the period from time t4 to time t7, for example, from time t8 to time t8.
In the second read address counter 19 during the period of time t11, the address value A1 at point A in FIG. → Sequential read address value RAD2 in the path from point D to point D to point D to point A
Are sequentially output each time the read clock signal RCK is applied.

For example, in the second read address counter 19 during the period from the time t12 to the time t15, the address value A5 at the point M in FIG. 2A from the time t12 is changed to the initial address value A5. The sequential read address value RAD2 in the path from the point of the point → the point of the point → the point of the point → the point of the point → the point of the point → the point of the point → the point of → the point of the filter
Are sequentially output each time the read clock signal RCK is applied. As described above, in the operation example shown in FIG. 2, from the first read address counter 18, the time t2 to the time t5, the time t6 to the time t9, and the time t10 to
The read address value RAD1 is given to the memory 5 as the address signal ADR via the selection circuit 20 during each of the time periods t13, t14 to t17,..., And the second read address counter 19 During each of the time periods t4 to t7, time t8 to time t11, time t12 to time t15, time t16 to (not shown time t19),... Is given to the memory 5.

In the selection circuit 20 to which the address selection signal S is given from the control unit 13, the write address value WAD supplied to the selection circuit 20 from the write address counter 14 and the first The read address value RAD1 supplied from the read address counter 18 to the selection circuit 20 and the read address value RAD2 supplied from the second read address counter 19 to the selection circuit 20 are selected and supplied to the memory 5. Perform the operation.

As described above, the timing signal generator 17
The coefficient signal K1 for signal level change shown in FIG. 2B generated in FIG. 2B is supplied to the arithmetic unit 6, and is also generated in the timing signal generating unit 17 shown in FIG. The coefficient signal K2 for changing the signal level is supplied to the arithmetic unit 7. The coefficient signal K for changing the signal level described above.
Reference numerals 1 and K2 denote the signal levels of the acoustic signals (digital data of the acoustic signals) supplied from the memory 5 to the arithmetic units 6 and 7 in the inclined portions shown in the figure as gradually increasing and decreasing in the figure. Thus, it is for increasing and decreasing gradually.
The coefficient signal for changing the signal level is output from one of the operation units 6 (or 7) as a result of the operation of one of the coefficient signals K1 (or K2) in the one operation unit 6 (or 7). When the signal level of the audio signal is gradually increased (or gradually decreased), the other signal K2
(Or K1), as a result of the operation in the other operation unit 7 (or 6), the signal level of the acoustic signal output from the other operation unit 7 (or 6) is gradually reduced (or gradually increased), In addition, the sound signals in a state where the sound signals output from the arithmetic units 6 and 7 are added can be smoothly connected.

The period from time t1 to time t2 in the coefficient signal K1 for changing the signal level shown in FIG.
A period from time t5 to time t6, a period from time t9 to time t10,
The period from time t13 to time t14, and time t in the coefficient signal K2 for signal level change shown in FIG.
3 → period of time t4, time t7 → period of time t8, time t11
In the period from time t12, from time t15 to time t16, the coefficient is a part where the coefficient is 0, and the time t3 to time t4 in the coefficient signal K1 for changing the signal level, the time t7.
→ period of time t8, time t11 → period of time t12, time t1
The period from 5 to time t16, the period from time t1 to time t2, the period from time t5 to time t6, the period from time t9 to time t10, and the period from time t13 to time t14 in the signal level change coefficient signal K2 are as follows: This is the part where the coefficient is 1 (maximum value).

In the example shown in FIG. 2, (b),
The coefficient signal K1 for signal level change shown in FIG.
The period during which the signal level of the acoustic signal is gradually increased or decreased by K2 is from time t2 to time t3, time t4 to time t5, and time t.
6 → time t7, time t8 → time t9, time t10 → time t11,
Time t12 → time t13, time t14 → time t15, time t16 →
Time t17 is shown. (D) of FIG.
FIG. 7 is a diagram illustrating a state of a combination of acoustic signals whose signal levels are gradually increased and decreased by the arithmetic operations in the arithmetic units 6 and 7 using the above-described coefficient signals K1 and K2 for changing the signal level, and their detailed contents. Is shown in FIG.

In FIG. 2D, Z1, Z2, Z3
.. Represent the acoustic signals read from the areas Z1, Z2, Z3,... In the memory 5, and the crosses indicate that the contents of the acoustic signals were written to the memory 5 before the time t1. Is shown. Further, for example, as in a period from time t10 to time t11, Z8, Z9, Z10 / Z4, Z
Periods indicated as 5, Z6 are shown in FIG.
This indicates a combination of acoustic signals as illustrated and described from time t10 to time t11 in (c).
In FIG. 3, vd means that the signal level is gradually decreasing, and vu means that the signal level is gradually increasing.

Next, by taking the period from time t9 to time t12 in FIG. 2 as a representative example, the contents of (a) to (d) of FIG. 2 and (d) of FIG. The details of the audio signal processing will be described with reference to FIGS. Now, in the audio signal processing device shown in FIG. 1, the digital data of the audio signal to be subjected to the signal processing is a write clock signal WCK in a state where the maximum value and the minimum value of the memory address value are continuous. The memory area of the memory 5 is continuously accessed on the time axis in the cycle of .times., And the memory 5 sequentially connects points a, b, c,... In FIG. Solid line W
The data is sequentially stored in a storage area determined according to a change mode of the write address exemplified by the AD.

In the acoustic signal processing apparatus shown in FIG. 1, the digital data of the acoustic signal written in the memory 5 in the above-described writing manner is such that the access to the storage area of the memory 5 is performed by the write clock signal WCK. Read clock signal RC having a cycle (in the case of the embodiment) of 1/3 of the cycle of
The first and second read address counters 18, which are configured to perform the counting operation at the timing of K,
This is performed using read address values (read address signals) RAD1 and RAD2 output from
The operation of reading the digital data of the audio signal from is performed. The above-described write operation and read operation in the memory 5 are performed by the memory control signal CS and the memory read / write selection signal R supplied from the control unit 13 to the memory 5.
W and the address signal ADR provided from the selection circuit 20 to the memory 5.

The address signal ADR supplied from the selection circuit 20 to the memory 5 is converted into a write address signal WAD or a read address by the address selection signal S supplied from the control unit 13 to the selection circuit 20. Signal RAD1 or read address signal R
AD2. The write clock signal WCK generated by the control unit 13 and the read clock signal RC
K has a predetermined period required for the time axis compression operation performed by the acoustic signal processing device.
The period of the write clock signal WCK and the period of the read clock signal RCK illustrated in FIG. 4 are the same as those of the embodiment of the audio signal processing apparatus in the case where the time axis of the audio signal is compressed at the time of 1/3 slow motion reproduction. In this case, the period of the write clock signal WCK is shown as three times the period of the read clock signal RCK.

As described above, the above-described first and second read address counters 18 in the storage area of the memory 5 where the digital data of the audio signal to be subjected to the signal processing are continuously stored. , 19, the read address value R output after time t9 in FIG.
The digital data of the audio signal read from the storage areas corresponding to AD1 and RAD2 are as shown in FIG. 2D and FIGS. 3A to 3C. That is,
At time t9, the second read address counter 19
The read address value RAD2 output from A is A4 corresponding to the point in FIG. 2A, and is output from the second read address counter 19 during the period from time t9 to time t10. Read address value RAD2
Is the address value A4 corresponding to the point F in FIG. 2A → the address value A6 corresponding to the point U → the address value A1 corresponding to the point T (the above-mentioned F, K, D, T, etc.). It is needless to say that each point is a representative point adopted for the sake of explanation, and that many address values exist on the line connecting the above-described points. The same applies to the description of the other written portions, which is performed by showing only the address value of each representative point shown in FIG. 2).

By the read address value RAD2 output from the second read address counter 19 from time t9 to time t10, the audio signal (audio signal data) read from the memory 5 is represented by (a) in FIG. In the storage area of the memory 5, the storage area Z5 corresponding to the write address existing on the line connecting the points レ and b in accordance with the read address value existing on the line connecting the point の and the point に お け る in). , Z6 read out from Z6
Due to the read address value existing on the line connecting Z6 and the points D and T in FIG. 2A, the storage area in the memory 5 exists on the line connecting the points C and K in the memory area. The audio signal Z7 read from the storage area Z7 corresponding to the write address. The above state is shown in FIG. 2D and the section from time t9 to time t10 in FIG.

Next, during a period from time t10 to time t11, both of the first read address counter 18 and the second read address counter 19 read the read address. Value RAD1, R
AD2 is output. First, the audio signal (data of the audio signal) read from the memory 5 by the read address value RAD1 output from the first read address counter 18 during the period from time t10 to time t11 is shown in FIG. In the storage area of the memory 5, the storage area Z4 corresponding to the write address existing on the line connecting the points S and B in the storage area in the memory 5 by the read address value existing on the line connecting the points S and The audio signals Z4, Z5, and Z6 read from Z5 and Z6, and are read from the memory 5 by the read address value RAD2 output from the second read address counter 19 during the period from time t10 to time t11. The acoustic signal (data of the acoustic signal) is represented by the read address value existing on the line connecting the points A and A in FIG. In the storage area in the memory 5, the storage area corresponding to the write address in the line connecting the points of the point and authors Ke Z
8, Z9, Z10 read out from the acoustic signals Z8, Z9,
Z10. The above state is shown in FIG. 2D and the section from time t10 to time t11 in FIG.

The read-out address value RAD1 output from the first read-out address counter 18 from the time t11 to the time t12 causes the sound signal (sound signal data) read from the memory 5 to be converted to the signal (a) in FIG. In the storage area of the memory 5, the storage area Z7 corresponding to the write address existing on the line connecting the points C and C in the storage area of the memory 5 by the read address value existing on the line connecting the points U and M in FIG. , Z8, Z9 read out from the audio signals Z7, Z8, Z9. The above state is shown in FIG. 2D and the section from time t11 to time t12 in FIG. In FIG. 2A showing a change state of the read address value output from the first and second read address counters 18 and 19, of the two read address counters 18 and 19 described above. In the period in which only the read address value output from one of the two is effectively used for reading data from the memory 5, the change state of the read address value is indicated by a thin solid line. In the period in which the read address value output from both of the read address counters 18 and 19 is effectively used for reading data from the memory 5, the change state of the read address value is indicated by a dashed line. I have.

As described above, from time t9 to time t12
During this period, the states of the acoustic signals sequentially read from the memory 5 are as shown by modeling in the period from time t9 to time t12 in FIGS. 2D and 3A. The audio signals sequentially read from the storage area of the memory 5 specified by the read address value RAD1 output from the first read address counter 18 are supplied to the arithmetic unit 6, and the second From the storage area of the memory 5 designated by the read address value RAD2 output from the read address counter 19 of FIG.
The sequentially read acoustic signals are supplied to the arithmetic unit 7.

As described above, the arithmetic unit 6 is provided with the coefficient signal K1 for changing the signal level as illustrated in FIG. 2B generated by the timing signal generating unit 17. Since the arithmetic unit 7 is provided with a coefficient signal K2 for signal level change as illustrated in FIG. 2C generated by the timing signal generating unit 17, 5 is supplied to the data holding unit 8 after being multiplied by the coefficient signal K1 for changing the signal level as illustrated in FIG. Also, from the memory 5 to the arithmetic unit 7
Is multiplied by the coefficient signal K2 for signal level change illustrated in FIG. 2C, and is supplied to the data holding unit 9. The calculation unit 6 described above
(Or 7) where the coefficient signal K1 (or K2) for changing the signal level is 0 (the coefficient is 0)
In, it goes without saying that the output from the arithmetic unit 6 (or 7) becomes 0.

After the data held in the data holding units 8 and 9 are added by the adding unit 10, the audio signal supplied from the adding unit 10 to the digital-to-analog converter 11 is arranged on the time axis. The state is as illustrated in FIG. As described above, FIG. 3C showing an operation explanatory diagram of the embodiment of the audio signal processing apparatus in the case of performing the time axis compression of the audio signal at the time of 1/3 slow motion reproduction is considered. ., Z2, Z3, Z4, Z5, Z6,..., Which are continuous on the time axis, and the acoustic signal whose time axis is compressed to １ ／ is a time t5 in the figure. ~ Time t6, time t7 ~ time t
8, time t9 to time t10, time t11 to time t12, time t13
In each period from time t14 to time t14, the sound read from the storage area designated by the read address value output from one of the two read address counters 18 and 19 (or 19). The signal is, for example, “Z1, Z2, Z3” → “Z3, Z4, Z
As in the case of “5” → “Z5, Z6, Z7”, the regions are intermittently arranged on the time axis while sequentially shifting the regions.

The time t5 to time t6 and the time t
7 to time t8, time t9 to time t10, time t11 to time t1
2. Periods between adjacent periods in each period such as time t13 to time t14, that is, time t6 to time t7, time t8 to
Time t9, time t10 to time t11, time t12 to time t13,
In each of the periods from time t14 to time t15, the read address values output from both of the two read address counters 18 and 19 cause one of the acoustic signals read from the other designated storage area to be read from the other storage area. The sound signal read from the storage area is in a so-called melted state, the sound signal read from the other storage area is in a so-called dark state, and the sound signal read from the two storage areas is At the same time, they are arranged on the time axis.

As described above, in the acoustic signal processing apparatus of the present invention, for example, 3
1 for acoustic signal with time axis extended twice
When the time axis compression is performed at / 3, the data is read from the storage area designated by the read address value output from one of the two read address counters 18 and 19 (or 19). 2 and FIG. 3, "Z1, Z2, Z3" → "Z3, Z4, Z
5 "→" Z5, Z6, Z7 ", the two read address counters 18, 18 between the acoustic signals intermittently arranged on the time axis, which are read while shifting the area.
With the read address values output from both of the storage areas 19, the audio signal read out from one of the storage areas, among the audio signals read out from each of the storage areas respectively designated, is brought into a so-called melted state, Since the sound signals read from the other storage area are arranged in a state where the sound signals read from the two storage areas are in a so-called dark state, the sound signals are arranged at a predetermined time. Even if the time axis compression operation of (1/3 in the embodiment) is performed,
There is no signal-free time, and there is no phase shift or sudden signal level at the connection between successive audio signals.
An easy-to-hear reproduction sound is easily obtained. Further, a memory having a small storage capacity can be used as the memory used for the above-described acoustic signal processing operation.

The digital-to-analog converter 11 supplied with the digital audio signal from the adder 10 performs a DA conversion operation using the DA conversion signal DACK and outputs an analog signal-type audio signal. The signal is sent to the output terminal 2 via the band-pass filter 12. The above description of the audio signal processing apparatus has been described that the time axis of the audio signal whose time axis is expanded by a factor of 3 compared to the time of the recording operation by the 1/3 slow motion reproduction operation is compressed by the time axis to 1/3. However, the present invention is not limited to the case where the audio signal to be subjected to the signal processing is the audio signal to be subjected to the signal processing regardless of the time axis compression ratio. Satisfactorily by setting the timing of the generation of the preset signals LD1 and LD2 and the timing of the generation of the coefficient signals K1 and K2 for changing the signal level in correspondence with the time axis compression ratio of it can.

[0051]

As is apparent from the above description, the sound signal processing apparatus of the present invention makes the access to the storage area of the memory continuous with the maximum value and the minimum value of the address value of the memory. Means for continuously writing an acoustic signal to be processed in a memory performed in a circular state, and a state in which the acoustic signal stored in the memory is pitch-converted by time axis compression. And a means for reading out as an audio signal of a specific one of the plurality of specific address values set at predetermined intervals in all address areas of the memory. When the write address value matches the new address value, the read address value is changed to an address value near the write address value, and the read address value is changed by a subsequent counting operation to change the read address value. The first read address counting means for performing a read address value counting operation during a period until the read address value approaches the write address value, and the first read address counting means counts the read address value. During the operation, when the first read address counting means determines that the write address value matches another specific address value different from the specific address value whose read address value has been changed. In addition, the read address value is changed to an address value near the write address value corresponding to the other specific address value, and the read address value changed by the subsequent counting operation is added to the write address value. A second read address counting means for performing a read address value counting operation in a period up to the vicinity of attaching As the read address value changes by the counting operation after the read address value is changed to an address value near the write address value in the output address counting means, the signal of the acoustic signal read corresponding to the read address value The level is gradually increased, and the read address value corresponds to the read address value as the read address value changes in a portion near the front until the read address value reaches a portion following the write address value by the counting operation of each read address counting means. Means for gradually reducing the signal level of the read sound signal, and sound read from the memory corresponding to the read address generated by the counting operation by the first and second read address counting means. And a means for synthesizing signals. In addition to enabling the audio signal to be heard during low-speed reproduction of a VTR or the like, the audio signal is read from the storage area designated by the read address value output from one of the two read address counters. Acoustic signals are intermittently arranged on the time axis while sequentially shifting the area, and different storage signals respectively indicated by the read address values output from both of the two read address counters. The acoustic signal read from each of the areas, the acoustic signal read from one of the storage areas is in a so-called melted state, and the acoustic signal read from the other storage area is in a so-called dark state.
In order that the sound signals read from the two storage areas are simultaneously arranged on the time axis, reading from the memory is started from an address position close to the write address, and the signal is gradually released. By increasing the level and gradually lowering the signal level near the write address, it is easy to hear without causing a phase shift or abrupt signal level at the connection between successive audio signals. Sound is used as a memory used for the acoustic signal processing operation.
It can be configured using small storage capacity,
The present invention can satisfactorily solve the above-mentioned problems.

[Brief description of the drawings]

FIG. 1 is a block diagram of an audio signal processing device of the present invention.

FIG. 2 is a diagram for explaining the operation of the acoustic signal processing device of the present invention.

FIG. 3 is a diagram for explaining the operation of the acoustic signal processing device of the present invention.

FIG. 4 is a diagram for explaining the operation of the acoustic signal processing device of the present invention.

FIG. 5 is a diagram for explaining the operation of the acoustic signal processing device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Output terminal, 3, 12 ... Low-pass filter, 4 ... Analog-digital converter, 5 ... Memory, 6, 7
... Arithmetic operation unit, 8, 9 data holding unit, 10 addition unit, 11
... Digital-to-analog converter, 13 ... Control unit, 14 ... Write address counter, 15 ... Divider, 16 ... Detection unit, 1
7 timing signal generator, 18, 19 read address counter, 20 selection circuit,

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[Procedure amendment]

[Submission date] November 7, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0025

[Correction method] Change

[Correction contents]

Each time the preset signal LD1 generated by the timing signal generator 17 is applied at each of the times t2, t6, t10, t14,..., The first read address counter 18
Read address signal (read address value) R
The output operation of the AD1 will be described below by taking the period from the time t2 to the time t5 as a representative example. At the time t2, the preset signal LD1 is supplied to the first read address counter 18.
, The write address value A1 output from the write address counter 14 at time t2 is preset in the first read address counter 18. From the time t2, the first read address counter 18 sets the address value A1 at the point 時刻 in FIG. 2A as the initial address value A1, and sets the point ヲ → the point ワ → the The sequential read address values RAD1 in the path from the point to the point to the point to the point to the point to the point are sequentially output each time the read clock signal RCK is supplied.

Claims (1)

[Claims] An audio signal to be subjected to signal processing for a memory in which access to a storage area of the memory is performed in a circular state in which a maximum value and a minimum value of an address value of the memory are continuous. And a means for continuously reading the sound signal stored in the memory, and a means for reading the sound signal stored in the memory as a sound signal whose pitch has been converted by time axis compression. When the write address value matches one specific address value among a plurality of specific address values set at predetermined intervals in the entire address area, an address near the write address value is set. The read address value is changed to the read address value, and the read address value is changed by the subsequent counting operation until the read address value approaches the write address value. A first read address counting means for performing a counting operation of a read value, and a first reading address counting means for performing the counting operation of the read address value while the first reading address counting means performs the counting operation of the read address value. Is different from the specific address value whose read address value has been changed, and when the write address value matches another specific address value, the vicinity of the write address value corresponding to the other specific address value described above A second operation of counting the read address value is performed until the read address value is changed to the address value and the read address value changed by the subsequent counting operation is close to catching up with the write address value. In the read address counting means, and in each of the above-mentioned read address counting means, the read address value is an address near the write address value. With the change of the read address value by the counting operation after the change to the read address value, the signal level of the acoustic signal read corresponding to the read address value is gradually increased. Thus, as the read address value changes in a portion near the front before the read address value reaches a portion following the write address value, the signal level of the acoustic signal read corresponding to the read address value is gradually reduced. And a means for synthesizing an acoustic signal read from the memory in correspondence with the read address generated by the counting operation of the first and second read address counting means.