JPH1091653A - Logical synthesis system, logical synthesis circuit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of logical synthesis processing and to effectively utilize a logical synthesis system by reducing parts to be manurally controlled. SOLUTION: The system is provided with a reading means 2 for reading out a logical circuit rule base storing logical circuit information not to be used for previously set logical synthesis, a retrieving means 3 for retrieving whether the same logical circuit as the read logical circuit rule base is included in a circuit to be applied to logical synthesis or not, a confirming means 4 for confirming whether the detected logical circuit is to be used for logical synthesis or not with a user, and a preparation means 5 for preparing a logical synthesis system controlling command including the information when the detected logical circuit is not used for logical synthesis. Since the leakage of retrieval is not generated and the command is automatically prepared by the means 5 after confirming the retrieved result with the user, missetting due to a command miss or the like can be removed. Consequently reliability in the use of the system can be improved and the operability of the system can also be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic synthesis system for searching for a logic circuit written in a rule base in a logic synthesis target circuit using a logic circuit rule base and performing logic synthesis. The present invention relates to a synthesis circuit and a logic synthesis method.

[0002]

2. Description of the Related Art Conventionally, logic synthesis systems include, for example,
There has been a system that searches whether a logic circuit written in a rule base exists in a logic synthesis target circuit and performs logic synthesis. In such a logic synthesis system, when performing logic synthesis, an operator manually sets a control command for the logic synthesis system to perform logic synthesis of a logic circuit.

[0003]

However, in the conventional logic synthesis system, since the operator synthesizes the logic circuit by manual setting, the logic synthesis system may be erroneously selected due to an erroneous selection of a target or an erroneous control command setting to the logic synthesis system. An incorrect logic synthesis process may be performed, and there is a problem in reliability.

In addition, this type of logic synthesis system has a problem in that a large-scale logic synthesis target circuit requires an enormous amount of time for logic synthesis processing, resulting in reduced workability.

An object of the present invention is to improve the reliability of logic synthesis processing by reducing the number of parts manually controlled when using a logic synthesis system, and to effectively use the logic synthesis system.

[0006]

A logic synthesis system and a logic synthesis circuit according to the present invention include, in addition to a logic synthesis system conventionally provided, a logic circuit rule containing logic circuit information which is not set as a target of logic synthesis. Reading means for reading the base, search means for searching whether the same logic circuit as the read logic circuit rule base exists in the logic synthesis target circuit, and whether or not the user is to be subjected to logic synthesis if found. And a creating means for creating a control command for a logic synthesis system including the information when not subject to logic synthesis.

According to the logic synthesis method of the present invention, whether or not a logic circuit written in the rule base exists in the input logic synthesis target circuit is automatically searched by the search means for the logic synthesis target circuit. Since there is no search omission and the command is automatically created by the logic synthesis system control command creation means after confirming the search result to the user, there is no setting error due to a command error or the like. As a result, reliability in using the system is improved, and workability can be improved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a logic synthesis system, a logic synthesis circuit and a logic synthesis method according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an overall configuration of an embodiment of a logic synthesis system using a circuit rule base according to the present invention. In FIG. 1, the logic synthesis system includes a logic synthesis target circuit input means 1, a logic circuit rule base reading means 2, a logic synthesis target circuit search means 3, a user confirmation means 4, a logic synthesis system control command. It comprises a creating means 5 and a logic synthesis system 6.

FIG. 2 shows a hardware configuration for realizing the present system. In FIG. 2, the logic synthesis system inputs a logic circuit information file 28 to be subjected to logic synthesis and a partial circuit rule base 29 not suitable for the logic synthesis from the magnetic disk device 23.

In this embodiment, the partial circuit loop base 29 input from the magnetic disk drive 23 is stored in the memory of the storage device 26 in the computer 21 and the logical synthesis is performed by the logic synthesis target circuit input means 1 shown in FIG. The processing in the system 6 is executed. At the time of confirmation means 4 to the user,
The display indicating the confirmation instruction is performed on the display device 24, and the confirmation instruction 27 is performed by the mouse device 22.

In the present embodiment, the control command 30 for the logic synthesis system indicating that the control command 30 is excluded from the target of the logic synthesis.
To the memory in the storage device 26, and the storage device 26
And the logic synthesis system 6 operating in the central processing unit 25.

FIG. 3 is a diagram showing the configuration of a logic circuit targeted by the present system and the locations of partial circuits that are not suitable for logic synthesis processing. Generally large-scale LSI
Is designed by dividing it into a group of functions, and the division unit is called a macro. The partial circuit that is not suitable for the target of the logic synthesis processing exists in the entire macro or a part of the inside of the macro.

FIG. 4 shows an LSI design flow to which the logic synthesis system according to the embodiment of the present invention is applied. FIG.
In step 41 (hereinafter, referred to as S41), a logic circuit is created or a hardware description language is created in S42. In S43 following S42, logic synthesis is performed when a hardware description language is created. Then, subsequent to S41 or S43, the entirety of the LSI to be combined with the logic circuit is combined, and in S45, it is determined whether or not the logic has been verified. After that, in the logic synthesis system 6 again, S
Optimization processing of a logic circuit such as 46 is performed. Here, if partial circuits that are not suitable for logic synthesis are excluded in advance from logic synthesis, timing problems during logic synthesis can be eliminated, and problems such as those found in the timing verification process can be prevented. it can. Even when a problem occurs in the timing verification process, it is possible to eliminate the duplication of the process of performing the logic synthesis process again, so that the process can be speeded up.

Next, an embodiment of the present invention will be described with reference to FIGS.
This will be described more specifically with reference to FIG. In these descriptions, description will be made with reference to FIGS. FIG.
3 is a circuit diagram showing an example of a logic circuit read by the logic circuit rule base reading means 2 of FIG. In FIG. 5, buffer 5
Numerals 1, 52 and 53 are composed of logic gates and are chain-connected successively as shown in the figure to increase the delay. Buffer 5
The output side of No. 3 is connected to the input terminal D of a flip-flop (hereinafter abbreviated as FF) circuit to delay the arrival time of the data line. Circuit connection information as shown in FIG. 5 can be stored in the circuit rule base 29.

FIG. 6 shows an example of the logic circuit of the search means 3 with the logic synthesis target circuit shown in FIG. This example of the logic circuit is a macro of a part of the LSI shown in FIG.
A search is made in the logic synthesis processing target circuit to see if there is one that matches the logic circuit shown in FIG. The same components as those in FIG. 5 are denoted by the same reference numerals, and detailed description is omitted. In FIG. 6, the data lines are traced back to the FFs 51 to 53 and recognized as flip-flops, and it is found that the same circuit as the logic circuit rule base exists.

If such a logic circuit is found,
Since the user may be subjected to the logic synthesis process, when the user instructs the user whether or not to perform the logic synthesis by an instruction from the mouse device 22, the display is displayed on the display device 24 according to the confirmation instruction. If it is excluded from the processing target of the logic circuit, a control command of the logic synthesis system as shown in FIG. 7 is created. This command is A
001 to A004 are left as they are. In the command of FIG. 7, an individual name (hereinafter referred to as an instance name) for identifying a partial circuit is used. After sending the control command of FIG. 7 to the logic synthesis system 6, the logic optimization system 6 performs logic optimization processing in S47.

FIG. 8 shows an example of the processed logic circuit. In the present embodiment, the logic gate 61 is formed by the logic optimization processing of S47 of the logic gates 64 and 65. However, when control is performed using the command of FIG.
It can be seen that 1,63-2 and 63-3 remain as they are. As a result, in this embodiment, control is not performed and S
47, the logic gate 63
-1, 63-2, and 63-3 disappear.

In the present embodiment described above, whether or not a logic circuit written in the rule base exists in the input logic synthesis target circuit is automatically searched by the search means for the logic synthesis target circuit. Since the search omission is eliminated, and after the search result is confirmed by the user, the command is automatically created by the control command creating means 5 for the logic synthesis system.
Setting errors due to command errors and the like are eliminated. As a result, reliability in using the system is improved, and workability can be improved. This makes it possible to accurately read a logic circuit rule base prepared before the logic synthesis processing and to exclude the logic circuit rule base from the logic synthesis target circuit, thereby eliminating the problem of erroneously performing the logic synthesis processing. By reducing the inconvenience of the operation due to the backward operation of performing the logic synthesis processing, the reliability in using the system is increased, and the workability can be improved.

[0020]

As described above, according to the present invention, the logic circuit rule base prepared in advance before the logic synthesis processing can be correctly read out and excluded from the logic synthesis target circuit. It is possible to eliminate the problem of performing the combining process, and to achieve effects such as reduction of backtracking of performing the logical combining process again.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a logic synthesis system using a circuit rule base according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the logic synthesis system of FIG. 1;

FIG. 3 is a diagram illustrating a configuration of a logic in an LSI and a location of a partial circuit that is not suitable for a logic synthesis process;

FIG. 4 is a flowchart showing a process in an LSI design flow to which the present system is applied.

FIG. 5 is a circuit diagram showing an example of a circuit registered in a logic circuit rule base.

FIG. 6 is a circuit diagram showing one circuit extracted from FIG. 3;

FIG. 7 is a diagram illustrating an example of a control command for specifying a non-logic synthesis target to be transmitted to the logic synthesis system.

FIG. 8 illustrates an example of a logic circuit output optimized using the present system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logic synthesis target circuit input means 2 Logic circuit rule base reading means 3 Logic synthesis target circuit search means 4 Confirmation means to user 5 Logic synthesis system control command creation means 6 Logic synthesis system 21 Computer 22 Mouse device 23 Magnetic Disk 24 display device 25 central processing unit 26 storage device 29 circuit rule base 30 control command 31 LSI 51 to 53 buffer 54 flip-flop circuit 64 logical product circuit 65 logical sum circuit

Continuing on the front page (72) Inventor Takuo Nakagi 1-403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside of NEC Corporation (72) Inventor Takeharu Nemoto 1, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 403, NEC Telecom System Co., Ltd.

Claims (6)

[Claims] 1. A logic synthesis system for performing logic synthesis by determining whether a logic circuit written in a logic circuit rule base exists in a logic synthesis target circuit, wherein information written in the logic circuit rule base is Input means for inputting, determining means for determining whether or not a hardware description language input separately matches a logical circuit in the logic circuit rule base; and the logical circuit input by the input means by the determining means An exclusion means for excluding from a target of automatic logic circuit synthesis when a logic circuit in the logic circuit rule base matches in the rule base and the hardware description language. 2. A reading means for reading the logic circuit rule base in advance, and a search means for searching whether or not a logic circuit written in the logic circuit rule base exists in the logic circuits to be subjected to logic synthesis. The logic synthesis according to claim 1, further comprising: logic synthesis target exclusion means for excluding from the logic synthesis target when a search target is found based on a search result from the search means. system. 3. A logic synthesis circuit for performing logic synthesis by determining whether there is a logic circuit written in a logic circuit rule base in a logic synthesis target circuit, wherein the information written in the logic circuit rule base is An input circuit for inputting, a judgment circuit for judging whether a logic circuit in the rule base matches in a hardware description language input separately, and a judgment signal outputted from the judgment circuit, An exclusion circuit that outputs an exclusion signal for excluding from the logic synthesis target when the input logic circuit rule base matches the logic circuit in the logic circuit rule base in a hardware description language. Logic synthesis circuit. 4. A read circuit for reading the logic circuit rule base in advance, and a search circuit for searching whether there is a logic circuit written in the logic circuit rule base among the logic circuits to be subjected to logic synthesis. Based on a search signal output from the search circuit, searching for the presence of the logic circuit written in the logic circuit rule base, and, if a search target is found, a logic synthesis to exclude from the logic synthesis target The logic synthesis circuit according to claim 3, further comprising: an object exclusion circuit. 5. A logic synthesis system for performing logic synthesis by determining whether a logic circuit written in a logic circuit rule base exists in a logic synthesis target circuit, wherein information written in the logic circuit rule base is Inputting; determining whether or not the logic circuit in the logic circuit rule base matches the logic circuit in the separately input hardware description language; and inputting the logic circuit rule base and the hardware description language into the hardware description language. Excluding from the subject of automatic logic circuit synthesis when the logic circuits in the logic circuit rule base match, a logic circuit method comprising: 6. A step of reading the logic circuit rule base in advance, and a step of searching whether or not a logic circuit written in the logic circuit rule base exists in the logic circuits to be subjected to logic synthesis. The method according to claim 5, further comprising: searching for the existence of the logic circuit written in the logic circuit rule base, and, when a search target is found, excluding the search target from the logic synthesis target. Logic synthesis method.