JPH1091591A - Parallel processing method for hierarchical multiprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for efficiently parallelly processing an intra- procedure loop composed of an inside loop and an outside loop through a hierarchical multiprocessor. SOLUTION: The initial value of loop parameter of the outside loop is set to an inter-cluster communication register GCRO and plural clusters 1 are activated. Each time the present cluster possesses the value of loop parameter of the outside loop to be partially charged while referring to and updating the inter-cluster communication register GCRO according to a Fetch & Add instruction, a representative processor 11 of each cluster 1 sets that value to an intra-cluster shared area IN and sets the initial value of the inside loop to an intra-cluster communication register LCRO. The representative processor 11 of each cluster 1 and other processors from 12-1 to 12-n possess the value of loop parameter of the inside loop to be partially charged by a present program while referring to and updating the intra-cluster communication register LCRO according to the Fetch & Add instruction and execute the processing of a repetition part determined by this value and the value of loop parameter of the outside loop set in the intra-cluster shared area IN as one task.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for parallel processing of an intra-procedure loop in a program by a plurality of processors, and more particularly to a multi-procedure loop including an inner loop and an outer loop. The present invention relates to a method for performing parallel processing in each processor.

[0002]

2. Description of the Related Art An intra-procedure loop composed of an inner loop and an outer loop, such as a double DO loop which often appears in a program for scientific calculation, is composed of a plurality of clusters each including a plurality of processors. As a conventional method of performing parallel processing in each processor constituting a hierarchical multiprocessor, for example, as shown in Japanese Patent Application Laid-Open No. 1-152571, an inner loop is expanded and converted into a single loop repetition processing. Is equally divided by the total number of processors in all clusters, and each
To run as a single task on each processor (hereafter,
(Referred to as a first conventional method).

On the other hand, in a normal tightly-coupled multiprocessor in which a plurality of processors are connected one-dimensionally, Japanese Patent Laid-Open Publication No. 3-218556 discloses a method of performing parallel processing in a procedural loop composed of a single loop by each processor. There are the following two methods described in the gazette.

The start value and the end value of the loop variable are set in one inter-processor shared register, and each processor exclusively refers to and updates the inter-processor shared register so that the open value in the inter-processor shared register is equal to or less than the end value. Is indicated, the start value in the inter-processor shared register is increased by an increment value per loop, and the loop is executed with the start value (hereinafter, referred to as a second conventional method).

[0005] The start value and the end value of each divided range obtained by dividing the range that the loop variable can take are set in an inter-processor shared register corresponding to each processor, and each processor stores the end value stored in its own inter-processor shared register. When the processing part of the intra-procedure loop is repeatedly executed until the number of times indicated by is reached, and when the execution is completed up to the closing number of times, if the unprocessed processing part remains by referring to the inter-processor shared register corresponding to another processor, Is a method of transferring a part of a range of a loop variable relating to the unprocessed loop part to an inter-processor shared register corresponding to the own processor and continuing the loop processing (hereinafter, referred to as a third conventional method). When each processor finishes executing up to the closing value stored in its own inter-processor shared register, it determines which other processor's inter-processor shared register to refer to by referring to all the remaining inter-processor shared registers. And a method of referring to one or more predetermined inter-processor shared registers.

[0006]

When an intra-procedure loop composed of an inner loop and an outer loop is processed in parallel by each processor constituting a hierarchical multiprocessor, a single loop is formed as in the first conventional method. In this method, all the double loops cannot always be formed into a single loop, so that the versatility is poor. Even if a single loop can be formed, the overhead associated with the single loop is generated, and if the processing of any of the processors is delayed, the other processor cannot take it over. There is a problem that the time until the processing is completed is delayed.

In order to solve such a problem, it is conceivable to apply the second conventional method to the first conventional method.
That is, the double loop is converted into a single loop, the start value and the end value of the loop variable are set in one inter-processor shared register, and each processor in all clusters exclusively refers to and updates the inter-processor shared register. When the opening value in the inter-processor shared register indicates a closing value or less, the opening value in the inter-processor shared register is increased by an increment value per loop, and the loop is executed with the opening value. According to this method, all the processors dynamically update the processing by referring to and updating one inter-processor shared register. Therefore, even if the processing of any one of the processors is delayed, the influence on the whole is small. However, each time each processor executes the loop once, each processor refers to one inter-processor shared register. Therefore, the number of executions of the loop is the same as the contention between the inter-processor shared registers and the interconnection network connecting the clusters. Data communication occurs, which causes the execution time of the procedure to increase.

As another solution, it is conceivable to apply a third conventional method to the first conventional method. That is, the start value and the end value of each divided range obtained by dividing the range of the loop variable of the loop obtained by converting the double loop into the single loop are set in the inter-processor shared register corresponding to each processor, and each processor corresponds to itself. The processing part of the intra-procedure loop is repeatedly executed until the number of times indicated by the closing value stored in the inter-processor shared register is reached, and when the execution is completed up to the closing number of times, the processing is performed by referring to the inter-processor shared register corresponding to another processor. In this method, when the processing part remains, a part of the range of the loop variable relating to the unprocessed loop part is transferred to the inter-processor shared register corresponding to the own processor, and the loop processing is continued. According to this method, the reference to the inter-processor shared register corresponding to the other processor is performed after the end of the loop of the number of times assigned to the own processor, so that the possibility of occurrence of contention of the inter-processor shared register is reduced. However, in this method, although each processor is configured to take over a part of the unprocessed portion of the other processor after finishing its assigned portion, if the processing of any processor is delayed, The time until the processing of the entire loop in the procedure is completed tends to be delayed. The reason is that when each processor finishes executing up to the closing value stored in its own corresponding inter-processor shared register, the method of referring to all the remaining inter-processor shared registers, when the number of processors is very large, This is because it takes time to find an inter-processor shared register in which an unprocessed portion remains. Also, in the method of referring to one or more predetermined inter-processor shared registers, if a delay occurs in the referring processor, even if there is another processor that has completed the processing, the processing is not performed. This is because underwriting becomes impossible.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method capable of efficiently performing a parallel processing of an intra-procedure loop composed of an inner loop and an outer loop by a hierarchical multiprocessor.

[0010]

According to the present invention, the processing of an in-procedure loop constituted by an inner loop and an outer loop is divided into a plurality of tasks, and each task is constituted by a plurality of processors. A parallel processing method executed by individual processors constituting a hierarchical multiprocessor in which a plurality of clusters are connected to each other by an interconnection network, wherein an initial value of a loop variable of an outer loop is stored in an intercluster communication register that can be referenced and updated from all clusters. Is set, and a specific one of the plurality of processors in each cluster exclusively refers to and updates the inter-cluster communication register to obtain a loop variable of an outer loop to be executed in the own cluster. Set the shared area in the cluster that can be referenced from all processors in the cluster, and update the reference from all processors in the cluster. The start value of the loop variable of the inner loop is set in the communication register within the cluster, and each processor in each cluster exclusively refers to and updates the intra-cluster communication register in its own cluster to execute the execution in its own cluster. Acquiring a loop variable of a loop, and executing a processing part of an in-procedure loop determined by the acquired inner-loop loop variable and an outer-loop loop variable set in the intra-cluster shared area as one task. And

Specifically, (a) a step of setting a start value of a loop variable of an outer loop in an inter-cluster communication register that can be referenced and updated from all clusters; and (b) a plurality of processors in each cluster. One specific processor exclusively obtaining the value of the inter-cluster communication register and increasing the original value by the increment value of the loop variable of the outer loop; and (c) changing the value obtained in step b to the outer loop. When the specific value is not larger than the final value of the loop variable, the specific processor sets the obtained value in the first cluster shared area that can be referred to by all processors in the own cluster, and sets the acquired value from all processors in the own cluster. Setting a start value of a loop variable of an inner loop in a reference-updatable intra-cluster communication register; and (d) step b.
If the value obtained in step 2 is larger than the final value of the loop variable of the outer loop, the specific processor sets the end of processing in a second cluster shared area that can be referred to by all processors in its own cluster, (E) synchronizing all processors for each cluster after completion of step c or d;
(F) after establishing the synchronization in step e, each processor in each cluster refers to the second intra-cluster shared area in its own cluster; and (g) the second intra-cluster shared area referred to in step f. When the area indicates the end of the processing, each processor in each cluster ends the processing of the intra-procedure loop; and (h) the second intra-cluster shared area referred to in step f does not indicate the end of the processing. In this case, each processor in each cluster exclusively obtains the value of the intra-cluster communication register in its own cluster and increases the value by the increment value of the loop variable of the inner loop; and (i) step h. If the value obtained in step 2 is not greater than the end value of the loop variable of the inner loop, the processor that has obtained the value And executing the processing portion of the procedure in the loop defined by the cluster in the loop variable of the set outer loop in the shared area as a single task,
(J) when the value obtained in step h is larger than the final value of the loop variable of the inner loop, the process returns to step b by synchronizing all processors for each cluster.

Further, according to the present invention, a specific processor of each cluster is used as a representative to synchronize among all clusters by using an inter-cluster communication register for synchronization processing which can be referenced and updated from all clusters, In this case, all processors are synchronized for each cluster by using an intra-cluster communication register for synchronous processing that can be referenced and updated from all processors.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a hierarchical multiprocessor to which the present invention is applied. The hierarchical multiprocessor of this example includes a plurality of clusters 1 and an interconnection network 2 that connects these clusters so that they can communicate with each other. One or more inter-cluster communication registers 3 that can be referenced and updated from all clusters 1 through the interconnection network 2 are connected to the interconnection network 2.

Each cluster 1 includes a plurality of processors 11,
12-1 to 12-n, a shared memory 13 shared by these, and data transfer control means 15 for controlling data transfer with another cluster through the interconnection network 2. Here, during the parallel processing of the intra-procedure loop, one of the plurality of processors in each cluster 1 operates as a representative processor. In FIG. 1, reference numeral 11 is assigned to the representative processor, and reference numerals 12-1 to 12-1 are assigned to the other processors.
12-n is provided for distinction. Also, the shared memory 1
In 3, one or more intra-cluster communication registers 14 that can be referenced and updated by all processors in the cluster are provided.

The inter-cluster communication register 3 stores the cluster 1
It is used for the transfer and synchronization of frequently accessed data between the clusters. The transfer of other data between the clusters 1 is performed via the shared memory 13, the data transfer control means 15, and the interconnection network 2. The intra-cluster communication register 14
It is used for transferring and synchronizing frequently accessed data between processors in each cluster 1, and other data is transferred between processors via the shared memory 13.

FIG. 2 shows a general form of an intra-procedure loop to be subjected to parallel processing and a dividing method for the parallel processing. In the figure, J is a loop variable (iteration) of the outer loop, where the open value is 1, the end value is M, and the increment value is 1
(Omitted in the figure). I is a loop variable of the inner loop. Here, the start value is 1, the end value is N, and the increment value is 1 (omitted in the figure). Tij is a generalization of an executable statement included in the range of a double DO loop. In the present invention, the outer loop is processed in parallel between the clusters, and the inner loop is processed in parallel in the cluster. That is, T _1,1 , T _2,1 , T _3,1,.
T _{N, 1} , T _1,2 , T _2,2 , T _3,2 , ..., T _{N, 2} , ...,
Each of T _{1, M} , T _{2, M} , T _{3, M} ,..., T _{N, M} is executed as one task, and the loop variable J of the outer loop has the same task (for example, T _1,1 , T _{2, 1,} T _3,1, ..., etc. T _{N, 1} set) is processed in the same cluster.

The processing of the intra-procedure loop composed of the inner loop and the outer loop as shown in FIG. 2 is divided into a plurality of tasks, and the individual processors constituting the hierarchical multiprocessor of FIG. 1 perform parallel processing. FIG. 3 shows an example of the operating environment in this case.

In FIG. 3, the same reference numerals as those in FIG. 1 denote the same parts, GCR0 and GCR1 indicate inter-cluster communication registers, LCR0 and LCR1 indicate intra-cluster communication registers,
N and finish are shared areas in the cluster set on the shared memory 13.

The inter-cluster communication register GCR0 and the intra-cluster communication register LCR0 are registers for holding loop variables. Among these, the inter-cluster communication register GCR0 holds the loop variable J of the outer loop in the intra-procedure loop, and the intra-cluster communication register LCR0 holds the loop variable I of the inner loop. The initial value 1 of the loop variable J of the outer loop is initially set in the inter-cluster communication register GCR 0, and thereafter, is exclusively updated by the representative processor 11 of each cluster 1. Further, the initial value 1 of the loop variable I of the inner loop is initially set in the intra-cluster communication register LCR0 by the representative processor 11 of each cluster 1, and thereafter, all the processors 11, 12-1 to 12-n in the same cluster are set. Is updated exclusively by reference.

The inter-cluster communication register GCR1 and the intra-cluster communication register LCR1 are registers for holding variables for synchronization. Among them, the inter-cluster communication register GCR1 holds a variable for simultaneously synchronizing between the clusters (inter-cluster barrier synchronization), and the intra-cluster communication register LCR1 is simultaneously synchronized between all the processors in the cluster (intra-cluster barrier synchronization). ) Is held. The value 0 is initially set in the inter-cluster communication register GCR1. When synchronizing between clusters, the representative processor 11 of each cluster 1 exclusively references and updates the value. A value 0 is initially set in the intra-cluster communication register LCR1, and when synchronization is established between all the processors in the cluster, the reference is exclusively updated by all the processors in the cluster.

The intra-cluster shared area IN is stored in each cluster 1
Representative processor 11 is an inter-processor communication register GC
This area holds the value of the loop variable of the outer loop acquired from R0. The intra-cluster shared area IN is updated by the representative processor 11 and is referred to by the other processors 12-1 to 12-n.

The intra-cluster shared area “finish” is an area for holding a value indicating whether or not to end the parallel processing operation of the intra-procedure loop in each cluster 1. 0 is set as an initial value in the intra-cluster shared area finish, and when the value of the loop variable of the outer loop obtained by the representative processor 11 of each cluster 1 from the inter-processor communication register GCR0 exceeds its final value M. The value 1 is set. If the value of the intra-cluster shared area finish is 1, each processor in each cluster 1 ends the processing.

FIGS. 4, 5 and 6 are flowcharts showing an example of the processing executed by each processor constituting the hierarchical multiprocessor when performing the parallel processing of the intra-procedure loop. FIG. 5 shows a flow of a process related to so-called task scheduling for selecting a task to be executed by the processor, that is, a processing portion to be executed by its own processor in a loop within a procedure, FIG. 5 shows a flow of barrier synchronization within a cluster, and FIG. The flow of barrier synchronization will be described below. Note that these programs are generated at the time of compiling the source program including the intra-procedure loop, and the opening value, the closing value, the increment value, the number of clusters, the number of processors in the cluster, and the like of the inner loop and the outer loop of the intra-procedure loop. Embedded.

The operation of this embodiment will be described below with reference to the drawings.

When the intra-procedure loop as shown in FIG. 2 is processed in parallel by the hierarchical multiprocessor of FIG. 1, an execution environment as shown in FIG. 3 is constructed, and an outer loop loop is provided in the inter-cluster communication register GCR0. The initial value 1 of the variable J is set to 1 in the intra-cluster communication register LCR1 and the inter-cluster communication register GCR1 for synchronization, and 1 is set to the intra-cluster shared area finish (FIG. 4).
S1). Then, the program for executing the processing after step S2 in FIG. 4, the program in FIGS. 5 and 6, and the data necessary for executing the in-procedure loop are loaded into the shared memory 13 in each cluster 1, and each of the clusters 1 The processor is started.

When each processor is started, it starts executing from the processing in step S2 in FIG. 4, and first determines whether or not its own processor is a representative processor. In the case of FIG. 3, the representative processor is defined as the processor 11 in each cluster 1, and the other processors 12-1 to 12-n are not representative processors. Accordingly, the processor 11 subsequently executes the processing after step S3, and the remaining processors 12-1 to 12-n skip steps S3 to S8 and proceed to step S9.

At step S3, the representative processor 11 of each cluster 1 exclusively refers to and updates the inter-cluster communication register GCR0 according to the Fetch & Add instruction. Here, the Fetch & Add instruction is an operation described below.

F & A (CR, inc); temp ← CR; CR ← CR + inc; Return temp; where CR indicates a communication register to be accessed, and inc indicates an increment value thereof. In other words, Fetch & Add
The instruction returns the value of the communication register and, at the same time, increments the value of the communication register by the specified value (inc).

In this case, Fetch & A in step S3
The communication register in the dd instruction is set to GCR0, and inc is set to 1 which is the increment value of the loop variable of the outer loop. The initial value of the inter-cluster communication register GCR0 is the initial value 1 of the loop variable J of the outer loop,
Since the h & Add instruction is executed exclusively, step S3 is executed first among the representative processors 11 of the plurality of clusters 1.
The representative processor 11 that has executed (1) acquires 1 as a return value, and the value of GCR0 becomes 2 at that time. Therefore, the representative processor 11 that has executed step S3 next obtains 2 as the return value, and the value of GCR0 becomes 3 at that time. Thus, each representative processor 11 acquires the value of the loop variable J of the outer loop to be processed in its own cluster.

The representative processor 11 having acquired the value of the loop variable of the outer loop next confirms that the value is not larger than the final value M of the outer loop (NO in S4), and changes the value of the outer loop acquired this time. The intra-cluster shared area IN is set (S5), and the start value 1 of the loop variable I of the inner loop is set in the intra-cluster communication register LCR0 (S6).
Proceed to step S9. If the acquired value of the loop variable J of the outer loop is larger than the closing value M (YE in S4)
S) Since there is no outer loop to be executed by the own cluster, 1 is set to the intra-cluster shared area finish (S7), barrier synchronization between clusters is obtained (S8), and the process proceeds to step S9. This inter-cluster barrier synchronization will be described later.

Now, in the intra-cluster barrier synchronization of step S9, each processor executes the processing shown in FIG. First, the lock of the intra-cluster communication register LCR1 for intra-cluster barrier synchronization is acquired (S21), and the value is checked to see if it is 0 (S22). If the value of the intra-cluster communication register LCR1 is 0, this register LCR1
Is set to the number of processors in the own cluster (S23), 1 is subtracted from the set value (S24), and the intra-cluster communication register LCR1 is unlocked (S25). On the other hand, if the value of the intra-cluster communication register LCR1 is not 0 (NO in step S22), the value is subtracted by 1 (S2
4), the intra-cluster communication register LCR1 is unlocked (S25). Then, the processor waits until the value of the intra-cluster communication register LCR1 becomes 0 (S26).
At this point, the intra-cluster barrier synchronization process ends, and the process proceeds to the post-synchronization process.

The intra-cluster communication register LCR1 has been initialized to 0 in step S1 in FIG. 4, and steps S22 to S24 in FIG. 5 are exclusively performed by all processors in the cluster. The recognized processor recognizes that the value of LCR1 is 0, and after setting the number of processors in the cluster, subtracts 1 and proceeds to step S26. Next, the processor that has acquired the lock subtracts 1 since the value of LCR1 is not 0, and proceeds to step S26.
Thus, when the last processor of the cluster acquires the lock and subtracts 1 from the value of LCR1, the value of LCR1 becomes 0, and all processors in the cluster execute step S2.
By exiting all at once, the intra-cluster barrier synchronization ends.

The waiting of the processor in step S26 employs a spin lock, that is, a method of repeatedly testing until a condition is satisfied. However, a suspend lock, that is, a method of interrupting execution until a condition is satisfied, can also be realized.

Each processor that has completed the intra-cluster barrier synchronization in step S9 of FIG.
With reference to the value of ish (S10), if it is 1, the process is terminated. If it is not 1, the process proceeds to step S11 and subsequent processes.

Each processor of each cluster 1 that has proceeded to step S11 exclusively refers to and updates the intra-cluster communication register LCR0 by the Fetch & Add instruction. That is, the current value of the intra-cluster communication register LCR0 is obtained, and the original value is added by the increment value 1 of the loop variable I of the inner loop. The intra-cluster communication register LCR0 is initially set to the start value 1 of the loop variable I of the inner loop in step S6, and the Fetch of step S11 is performed.
Since the & Add instruction is executed exclusively by all the processors in the cluster, the processor that first executes step S11 transmits the & 1 instruction to the intra-cluster communication registers LCR0 to LCR1.
And the value of LCR0 is 2 at that time. Therefore, the processor that has executed the next step S11 is the LCR
It obtains 2 from 0, at which point the value of LCR0 becomes 3. Thus, each processor acquires the value of the loop variable I of the inner loop to be processed by its own processor.

Each processor that has obtained the value of the loop variable of the inner loop next confirms that the value is not larger than the final value N of the inner loop (NO in S12), and proceeds to step S12.
The process proceeds to step S13 to obtain the value of the intra-cluster shared area IN. Next, the value of the intra-cluster shared area IN is set as the value j of the loop variable J of the outer loop, and the value of the communication register LCR0 in the cluster obtained in step S11 is set as the value i of the loop variable I of the inner loop. The part of T _{i, j} is executed as one task (S14). Then, after the execution is completed, the process returns to step S11 to repeat the above-described processing. The value obtained from the intra-cluster communication register LCR0 in step S12 is the loop variable I of the inner loop.
If there is no inner loop to be executed by the own processor, the process proceeds to step S15 to perform barrier synchronization within the cluster shown in FIG. 5, and returns to step S2 to execute the above-described processing. repeat.

As a result of the processing described above, for example, the representative processor 11 of a certain cluster 1 reads the loop variable J of the outer loop from the inter-cluster communication register GCR0 in step S3.
Is obtained, and the processors 11, 12-1 to 12-n in the cluster obtain the loop variable I of the inner loop from the intra-cluster communication register LCR0 in step S11.
.. Are acquired as the values of, the respective processors 11, 12-1 to 12-n execute the processing of tasks such as T _1,1 , T _2,1 ,. Will do. Similarly, as the value of the loop variable J of the outer loop from the inter-cluster communication register GCR0, x
(= 2,..., M), the plurality of processors 11, 12-1 to 12-n execute step S1.
In 4, the tasks such as T _{1, X} , T _{2, X} ,... Are executed in parallel.

When the repetition processing of the inner loop within the range of the value of the loop variable J of the outer loop obtained this time is completed, all the processors in the cluster take the intra-cluster barrier synchronization shown in FIG. 5 in step S15. In step S2, the representative processor 11 acquires the value of the loop variable J of the outer loop to be processed next, and repeats the above-described processing.

If the value of the inter-cluster communication register GCR0 obtained in step S3 exceeds the final value M of the loop variable J of the outer loop, the representative processor 11 of that cluster stores 1 in the intra-cluster shared area finish. Is set (S7), and barrier synchronization between clusters is established (S7).
8).

In the inter-cluster barrier synchronization in step S8, each representative processor 11 executes the processing shown in FIG. First, the lock of the intra-cluster communication register GCR1 for inter-cluster barrier synchronization is acquired (S31), and the value is checked to see if it is 0 (S32). If the value of the inter-cluster communication register GCR1 is 0,
The number of clusters constituting the hierarchical multiprocessor is set in CR1 (S33), 1 is subtracted from the set value (S34), and the inter-cluster communication register GCR1 is unlocked (S35). On the other hand, the inter-cluster communication register G
If the value of CR1 is not 0 (NO in step S32),
The value is subtracted by 1 (S34), and the inter-cluster communication register GCR1 is unlocked (S35). Then, each representative processor sets the value of the inter-cluster communication register GCR1 to 0.
(S36), and when it becomes 0, the inter-cluster barrier synchronization process ends, and the process proceeds to the process after synchronization is established.

The inter-cluster communication register GCR1 is initialized to 0 in step S1 in FIG. 4, and steps S32 to S34 in FIG. 6 are exclusively performed between clusters.
First, the representative processor of the cluster that has first acquired the lock recognizes that the value of GCR1 is 0, and after setting the number of clusters, subtracts 1 and proceeds to step S36. Next, since the value of GCR1 is not 0, the representative processor that has acquired the lock subtracts 1 and proceeds to step S36. In this way, when the representative processor of the last cluster acquires the lock and decrements the value of GCR1 by 1, the value of GCR1 becomes 0, and the representative processors of all clusters exit from step S36 all at once, and the inter-cluster barrier synchronization ends. I do.

The waiting of the processor in step S36 employs a spin lock, that is, a method of repeatedly testing until a condition is satisfied. However, a suspend lock, that is, a method of suspending execution until a condition is satisfied, can also be realized.

Thereafter, as described above, all the processors in each cluster 1 synchronize with the intra-cluster barrier (S9).
Upon recognizing that the value of the cluster shared area finish is 1, the processing ends.

As described above, according to the present embodiment, the determination of the repetition part (selection of a task) and synchronization performed by each processor are performed in two stages using the inter-cluster communication register and the intra-cluster communication register. Contention for access to is reduced, and parallel processing can be performed efficiently.

[0046]

As described above, according to the present invention, the following effects can be obtained.

Since the double loop is processed in parallel without being formed into a single loop, a double loop that cannot be formed into a single loop can be processed, so that the present invention is versatile, and there is no overhead associated with the formation of a single loop.

Since all clusters dynamically update and refer to one inter-cluster communication register, and within each cluster, all processors dynamically update and refer to one intra-cluster communication register. Even if the processing of any one of the clusters or any of the processors in the cluster is delayed, the effect on the whole is small.

Since only one specific processor in each cluster references and updates the inter-cluster communication register, and only the processor in that cluster references and updates the intra-cluster communication register in each cluster, one inter-cluster communication register is used. In addition, the number of processors accessing one communication register in a cluster is reduced, and access competition can be reduced.

As described above, the intra-procedure loop including the inner loop and the outer loop can be efficiently processed in parallel by the hierarchical multiprocessor.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a hierarchical multiprocessor to which the present invention has been applied.

FIG. 2 is a diagram showing a general format of a loop in a procedure to be subjected to parallel processing and a dividing method at the time of the parallel processing;

FIG. 3 is a diagram showing an example of an operating environment in which the processing of an intra-procedure loop composed of an inner loop and an outer loop is divided into a plurality of tasks, and the individual processors constituting the hierarchical multiprocessor perform parallel processing. It is.

FIG. 4 is a flowchart illustrating an example of a process of selecting a processing portion to be executed by the own processor among processes executed by each processor constituting a hierarchical multiprocessor when performing parallel processing of an intra-procedure loop.

FIG. 5 is a flowchart illustrating an example of a process of barrier synchronization within a cluster, among processes executed by each processor configuring a hierarchical multiprocessor when performing parallel processing of an intra-procedure loop.

FIG. 6 is a flowchart illustrating an example of a process of barrier synchronization between clusters among processes executed by each processor configuring a hierarchical multiprocessor when performing parallel processing of an intra-procedure loop.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Cluster 2 ... Interconnection network 3, GCR0, GCR1 ... Inter-cluster communication register 11 ... Representative processor 12-1 to 12-n ... Other processor 13 ... Shared memory 14, LCR0, LCR1 ... Intra-cluster communication register 15 ... Data transfer control means IN, finish ... Shared area in cluster

Claims (3)

[Claims] 1. A process in an intra-procedure loop composed of an inner loop and an outer loop is divided into a plurality of tasks, and each task is divided into a plurality of clusters each composed of a plurality of processors by an interconnection network. A parallel processing method executed by individual processors constituting a connected hierarchical multiprocessor, in which an inter-cluster communication register that can be referenced and updated from all clusters is set to a start value of a loop variable of an outer loop, and a A specific one of the plurality of processors exclusively refers to and updates the inter-cluster communication register to obtain a loop variable of an outer loop to be executed in the own cluster, and can be referred to from all processors in the own cluster. Intra-cluster communication registers that can be set in The start value of the loop variable of the inner loop is set to the parameter, and each processor in each cluster exclusively refers to and updates the intra-cluster communication register in the own cluster to update the loop variable of the inner loop to be executed in the own cluster. Acquiring a loop variable of the acquired inner loop and a loop variable of the outer loop set in the intra-cluster shared area, and executing a processing portion of the intra-procedure loop as one task. A parallel processing method in a processor. 2. The process of an intra-procedure loop composed of an inner loop and an outer loop is divided into a plurality of tasks, and each task is divided into a plurality of clusters each composed of a plurality of processors by an interconnection network. (A) setting a start value of a loop variable of an outer loop in an inter-cluster communication register that can be referenced and updated from all clusters; b) a particular one of a plurality of processors in each cluster exclusively obtaining the value of the inter-cluster communication register and increasing the original value by the increment of the loop variable of the outer loop; (C) when the value obtained in step b is not larger than the final value of the loop variable of the outer loop, the specific processor The obtained value is set in the first intra-cluster shared area that can be referred to by all processors in the cluster, and the start value of the loop variable of the inner loop is set in the intra-cluster communication register that can be referenced and updated by all processors in the own cluster. Setting; and (d) if the value obtained in step b is greater than the closing value of the loop variable of the outer loop,
Setting the processing end in the second intra-cluster shared area that the specific processor can refer to from all processors in the own cluster, and performing synchronization between all clusters;
(E) synchronizing all processors for each cluster after the completion of step c or d; and (f) after establishing synchronization in step e, each processor in each cluster is connected to the second processor in its own cluster. Referring to the intra-cluster shared area; and (g) terminating the processing in the intra-procedure loop in each cluster when the second intra-cluster shared area referred to in step f indicates processing end. And (h) when the second intra-cluster shared area referred to in step f does not indicate the end of processing, each processor in each cluster exclusively stores the value of the intra-cluster communication register in its own cluster. Obtaining and increasing the value by the increment value of the loop variable of the inner loop; and (i) making the value obtained in step h higher than the final value of the loop variable of the inner loop. If not, the processor that has obtained the value sets the processing part of the in-procedure loop defined by the obtained loop variable of the inner loop and the loop variable of the outer loop set in the first intra-cluster shared area to 1 Executing as two tasks, and (j) step h.
If the value obtained in step (c) is larger than the final value of the loop variable of the inner loop, a step of synchronizing all the processors for each cluster and returning to step b. . 3. A specific processor of each cluster is used as a representative to synchronize among all clusters using an inter-cluster communication register for synchronous processing that can be referenced and updated from all clusters. 3. The parallel processing method in a hierarchical multiprocessor according to claim 2, wherein all processors are synchronized for each cluster using a communication register in the cluster for synchronous processing that can be referenced and updated.