JPH1084037A - Multilayer interconnection forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make feasible of the miniaturization of interconnection patterns by self-aligned interconnection layers with the connecting parts thereof in the multilayer interconnection forming method. SOLUTION: After the successive formation of TiON/Ti layer 30a, an Al alloy layer 30b, a W layer 30c, another Al alloy layer 30d and another TiN/Ti layer 30e, the layers 30e, 30d are patterned by dry-etching step using a thin resist film corresponding to the lower layer wiring patterns and the thick resist layer 32b corresponding to the connecting part patterns as masks. Next, the layer 30c is patterned by the dry-etching step using the residual parts of the layers 30e, 30d and the layer 32b as masks. Furthermore, the residual part of the layer 30d and the layers 30b, 30a are patterned by a dry-etching step using the residual part of the layer 30c and the layer 32b as masks so as to form the interconnection layer 30 having the interconnection part 30A and the connecting part 30B while removing the layer 32b. Finally, after the deposition and etching back of the interlayer insulating films, the upper layer wirings are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer wiring suitable for use in the manufacture of LSIs and the like, and more particularly to a method for forming a connection between a lower wiring and an upper wiring in a self-alignment manner with the lower wiring. Thus, the wiring pattern can be miniaturized.

[0002]

2. Description of the Related Art Conventionally, a method shown in FIG. 27 or FIG. 28 has been known as a method of forming a multilayer wiring of an LSI. In these figures, 1 is a semiconductor substrate such as silicon, 2
Is an insulating film such as silicon oxide formed over the surface of the substrate 1.

In the method shown in FIG. 27, after a wiring layer 3 is formed on an insulating film 2, an interlayer insulating film 4 is formed on the insulating film 2 so as to cover the wiring layer 3. Then, after forming a connection hole 4a corresponding to a part of the wiring layer 3 in the insulating film 4 by photolithography and dry etching, a wiring material such as an Al alloy is applied to cover the connection hole 4a and the insulating film 4. The deposited layer is patterned by photolithography and dry etching to form a wiring layer 5. The wiring layer 5 is connected to the wiring layer 3 via the connection hole 4a.

In the method shown in FIG. 28, after a wiring layer 3 is formed on an insulating film 2, a wiring material is deposited on the upper surface of the substrate, and the deposited layer is patterned by photolithography and dry etching to form a pillar. The connection portion 6 called the wiring layer 3
Form on top. Then, after forming the interlayer insulating film 7 thicker than the connection portion 6 so as to cover the wiring layer 3 and the connection portion 6 on the insulation film 2, the insulating film 7 is etched back until the connection portion 6 is exposed. Thereafter, a wiring layer 8 is formed on the remaining portion of the insulating film 7 in the same manner as described with reference to FIG. The wiring layer 8 is connected to the wiring layer 7 via the connection part 6. Note that a specific example of the method of FIG. 28 is, for example, Journal of the Electrochemical
Society, Vol. 137, No. 2, February 1990, pp. 609-613.

[0005]

According to the method described above with reference to FIG. 27, it is difficult to form the connection hole 4a in a fine pattern or to form the wiring layer 5 in the connection hole 4a in a good connection state. There is a problem that it is not easy.

Further, according to the method described above with reference to FIG. 28, although the problems relating to the formation of the connection hole and the connection state in the connection hole can be avoided, the number of photomasks and the number of steps increase because the connection portion 6 is formed. There is a problem.

Further, in either of the methods shown in FIGS. 27 and 28, when forming the connection hole 4a or the connection portion 6, the wiring layer 3
, The position may be misaligned. As a countermeasure for this, it has been practiced to increase the width of a part of the wiring layer 3 so as to have a margin for alignment. However, providing a margin for alignment in a part of the wiring layer 3 hinders miniaturization of the wiring pattern.

An object of the present invention is to provide a novel method for forming a multi-layered wiring which enables finer wiring patterns.

[0009]

A first multilayer wiring forming method according to the present invention comprises a step of forming a first wiring material layer on an insulating film covering a substrate, and a step of forming the first wiring material layer. A step of disposing an etching mask having a first mask portion corresponding to a desired wiring pattern and a second mask portion corresponding to a connection portion pattern continuous with the wiring pattern, The first mask portion is formed by patterning the first wiring material layer by a selective etching process using the etching mask, wherein the thickness of the mask portion is set to be larger than the thickness of the first mask portion; Forming a first wiring layer having a wiring portion corresponding to the above and a connection portion protruding from the wiring portion corresponding to the second mask portion; and after removing the etching mask,
Forming an interlayer insulating film on the insulating film so as to cover the first wiring layer and be thicker than a peak level of the connection portion;
Removing the interlayer insulating film in a planar manner until the connection portion is exposed to leave a flat portion of the interlayer insulating film; and connecting the flat portion of the interlayer insulating film to the connection portion on the flat portion. Forming a second wiring layer.

According to the first multilayer wiring forming method, an etching mask having a relatively thin first mask portion corresponding to a wiring pattern and a relatively thick second mask portion corresponding to a connection portion pattern is used. By patterning the first wiring material layer, a first wiring layer having a wiring portion corresponding to the first mask portion and a connection portion protruding from the wiring portion corresponding to the second mask portion is obtained. . In this case, since the etching mask is commonly used for forming the wiring portion and the formation of the connection portion, the connection portion is formed in a self-alignment manner with respect to the wiring portion, and the alignment of the connection portion with respect to the wiring portion is performed. Not required.

A second method for forming a multilayer wiring according to the present invention comprises:
Sequentially forming a first wiring material layer, a conductive layer for an etching stopper, and a second wiring material layer on an insulating film covering the substrate; and forming a desired wiring layer on the second wiring material layer. A step of arranging an etching mask having a first mask portion corresponding to a wiring pattern and a second mask portion corresponding to a connection portion pattern continuous with the wiring pattern, wherein the thickness of the second mask portion is Is set to be larger than the thickness of the first wiring portion, and the second wiring material layer is patterned by performing a first selective etching process using the etching mask to form the second wiring material layer. A first portion corresponding to the first mask portion of the etching mask and having a predetermined thickness and a second portion corresponding to the second mask portion of the etching mask and having a thickness larger than the predetermined thickness of Leaving the second mask portion of the etching mask and the first and second portions of the second wiring material layer and the second mask portion of the etching mask as a mask. Patterning the conductive layer by a second selective etching process, thereby forming the conductive layer into first and second layers of the second wiring material layer.
And leaving a second mask portion of the etching mask, and a third selection using the remaining portion of the conductive layer and the second mask portion of the etching mask as a mask. By patterning the first and second portions of the second wiring material layer and the first wiring material layer by etching, a wiring portion corresponding to a first mask portion of the etching mask and the etching mask Forming a first wiring layer having a connection portion corresponding to the second mask portion, wherein the wiring portion is formed between a remaining portion of the first wiring material layer and a remaining portion of the conductive layer. After removing the second mask portion of the etching mask, the connecting portion is formed of the remaining portion of the second portion of the second wiring material layer, and the connection portion is formed of the remaining portion of the second portion of the second wiring material layer. 1 wiring Forming an interlayer insulating film thicker than the peak level of the connection portion, and removing the interlayer insulating film planarly until the connection portion is exposed to leave a flat portion of the interlayer insulating film. And a step of forming a second wiring layer connected to the connection portion on the flat portion of the interlayer insulating film.

According to the second multilayer wiring forming method, a connection portion is formed in a self-aligned manner with respect to the wiring portion by using one etching mask for both the formation of the wiring portion and the formation of the connection portion. Therefore, it is not necessary to align the connection portion with the wiring portion.

Further, a conductive layer for an etching stopper is provided between the first wiring material layer and the second wiring material layer, and the second wiring material layer is processed to form a connection on the conductive layer. Since the wiring portion is formed by forming the conductive layer and the first wiring material layer, the thickness of the wiring portion corresponds to the total thickness of the conductive layer and the first wiring material layer. Is determined with high accuracy. Therefore, variations in the wiring thickness can be reduced.

[0014]

1 to 6 show a method of forming a multilayer wiring according to an embodiment of the present invention. Steps (1) to (6) corresponding to the respective drawings will be sequentially described. In the following description, the laminated structure of the conductive material is defined as X / Y or X /.
Where the leftmost layer such as the X layer is the uppermost layer and the rightmost layer such as the Y layer is the lowermost layer.

(1) An insulating film 12 made of silicon oxide or the like covering the surface of a semiconductor substrate 10 made of silicon, for example.
Is formed, a wiring material layer 14A is formed on the insulating film 12. As the wiring material layer 14A, for example, TiN / Ti /
Al alloy (Al-Si-Cu) / TiON / Ti = 40
/ 7/1500/100/20 [nm] (20
[Ti] of [nm] is formed by a sputtering method or the like.

Next, a positive resist layer 16A is formed on the wiring material layer 14A by a spin coating method or the like. And
The pattern on the photomask 18 is transferred to the resist layer 16A by a step-and-repeat type exposure device.

The photomask 18 has a relatively thin first light-shielding portion 22a corresponding to a desired wiring pattern and a connecting portion pattern continuous with the wiring pattern on one main surface of a transparent plate 20 such as a quartz plate. And a relatively thick second light-shielding portion 22b. If the transmittance of the transparent plate 20 to the transfer light L is 100%, the first light-shielding portion 22b is formed.
In (a), the thickness of the light shielding portions 22a and 22b is determined such that the desired transmittance (for example, 50%) is smaller than 100% and larger than 0%, and is 0% in the second light shielding portion 22b. is there. Therefore, if the diffraction of light is neglected, the first light-shielding portion 22a transmits at least a part of the light emitted from the light source, and the second light-shielding portion 22b blocks the light. Therefore, in the resist layer 16A, a strong light Ln is incident on a portion corresponding to a transparent portion of the photomask 18 having a transmittance of 100%, and a weak light Lm is incident on a portion corresponding to the first light shielding portion 22a. The light L does not enter a portion corresponding to the second light shielding portion 22b. The photomask 18
A specific example of the formation method will be described later with reference to FIGS.

(2) Next, the resist layer 16A is developed. As a result, the first light-shielding portion 22a corresponding to the first thin-film resist layer corresponding to the wiring pattern is formed.
An etching mask 16 having a mask portion 16a and a second mask portion 16b made of a relatively thick resist layer corresponding to the connection portion pattern corresponding to the second light shielding portion 22b is obtained on the wiring material layer 14A. . Second mask portion 16b
Is thicker than the first mask portion 16a.

(3) Next, the wiring material layer 1 is selectively dry-etched with a chlorine-based gas using the mask 16.
4A is patterned. The dry etching conditions at this time are, for example, gas flow rate: BCl ₃ / Cl ₂ / CH ₂ F ₂ = 100/150
/ 12 [sccm] Pressure: 8 [mTorr] RF Power: 90 [W] As a result of the patterning, the first
Wiring portion 14a corresponding to the mask portion 16a and the connection portion 1 protruding from the wiring portion corresponding to the second mask portion 16b.
4b is obtained on the insulating film 12. After that, the mask portion 16b is removed.

(4) Next, the wiring layer 14 is formed on the insulating film 12.
To form an interlayer insulating film 24. As the insulating film 24, a silicon oxide-based film is formed to a thickness of, for example, 2000 [nm] thicker than the peak level of the connection portion 14b by, for example, a plasma CVD (chemical vapor deposition) method or a normal pressure CVD method. .

(5) Next, the insulating film 24 is planarly removed by an etch-back process until the top of the connection portion 14b is exposed, leaving a flat portion of the insulating film 24. The etch-back condition at this time is, for example, as follows: Gas flow rate: CHF ₃ / CF ₄ / He = 20/20/90
[Sccm] Pressure: 260 [Pa] RF power: 275 [W]

(6) Next, a wiring material such as an Al alloy is deposited on the flat portion of the insulating film 24, and the deposited layer is patterned by photolithography and selective dry etching to form a connection portion. A second wiring layer 26 connected to 14b is formed. As a result, the wiring layer 26 is
4b is connected to the wiring section 14a.

According to the above-described embodiment, the connection portion 14b is formed in a self-aligned manner with respect to the wiring portion 14a by using the etching mask 16 in common for forming the wiring portion 14a and forming the connection portion 14b. Therefore, it is not necessary to align the connection portion 14b with the wiring portion 14a. Therefore,
Since the wiring layer 14 does not need to have a margin for alignment, the wiring pattern can be miniaturized. Further, one photomask 18 is sufficient, and it is not necessary to prepare separate photomasks for the wiring layer 3 and the connection portion 6 as in the method of FIG.

FIGS. 7 to 14 show a method of forming a multilayer wiring according to another embodiment of the present invention. Parts similar to those shown in FIGS. .

In the step shown in FIG. 7, a first wiring material layer 30P, a W (tungsten) layer 30c and a second wiring material layer 30Q are sequentially formed on the insulating film 12 covering the surface of the semiconductor substrate 10. The wiring material layer 30P is made of TiON /
An Al alloy (Al-S) having a thickness of 350 [nm] is formed on the barrier layer 30a (Ti is a lower layer) of Ti = 100/20 [nm].
(i-Cu) layer 30b. W layer 30c
Is provided as a conductive layer for an etching stopper, and is formed to a thickness of, for example, 100 [nm]. As an example, the wiring material layer 30Q is formed by forming a TiN / AlN layer on a 1000 nm thick Al alloy [Al-Si-Cu) layer 30d.
The anti-reflection layer 30e of Ti = 40/7 [nm] (Ti is a lower layer) is laminated. The layers 30a to 30e can be formed by a sputtering method or the like.

Next, a positive resist layer 32A is formed on the wiring material layer 30Q by a spin coating method or the like. And
In the same manner as described with reference to FIG.
The wiring pattern and the connection portion pattern corresponding to a and 22b are transferred to the resist layer 32A by the light L.
At this time, highly accurate pattern transfer can be performed by the action of the antireflection layer 30e.

In the step of FIG. 8, the resist layer 32A is subjected to a developing process. As a result, the first mask portion 32a made of a relatively thin resist layer corresponding to the wiring pattern and the second mask portion made of a relatively thick resist layer corresponding to the connection pattern are formed.
The etching mask 32 having the mask portion 32b is obtained on the wiring material layer 30Q.

In the step of FIG. 9, the wiring material layer 30Q is patterned by selective dry etching using a chlorine-based gas using the mask 32. The dry etching conditions at this time are, for example, gas flow rate: BCl ₃ / Cl ₂ / CH ₂ F ₂ = 100/150
/ 12 [sccm] Pressure: 8 [mTorr] RF Power: 90 [W] In this case, the first mask portion 32a
Is removed and dry etching is performed so as to leave the second mask portion 32b. When etching the Al alloy layer 30d, the W layer 30c functions as an etching stopper.

As a result of the patterning, the Al alloy layer 3
0d remains according to the wiring pattern corresponding to the first mask portion 32a, and the stack of the Al alloy layer 30d and the antireflection layer 30e remains according to the connection pattern corresponding to the second mask portion 32b. A portion remaining in the Al alloy layer 30d according to the wiring pattern is a relatively thin first portion.
Is thinned by dry etching even after the mask portion 32a is removed by dry etching, but is left at an appropriate thickness in consideration of use as an etching mask in the next step. .

In the step of FIG. 10, the W layer 30c is patterned by selective dry etching using an SF ₆ -based gas using the remaining portion of the Al alloy layer 30d, the remaining portion of the antireflection layer 30e, and the mask portion 32b as a mask. The dry etching conditions at this time can be, for example, gas flow rate: SF ₆ / Ar = 104/26 [sccm] pressure: 32 [Pa] RF power: 450 [W]. In this case, dry etching is performed so as to leave the mask portion 32b. As a result of the patterning, the W layer 30c remains according to the wiring pattern and the connection portion pattern.

In the step of FIG. 11, the remaining portion of the Al alloy layer 30d and the wiring material layer 30P are patterned by selective dry etching with a chlorine-based gas using the mask portion 32b and the remaining portion of the W layer 30c as a mask. The dry etching conditions at this time can be the same as those described above with reference to the step of FIG. When the etching of the remaining portion of the Al alloy layer 30d proceeds, the remaining portion of the W layer 30c acts as an etching stopper.

As a result of the patterning, the wiring portion 30A corresponding to the first mask portion 32a and the second mask portion 32
The wiring layer 30 having the connection portion 30B corresponding to the “b” is obtained on the insulating film 12. The wiring portion 30 </ b> A includes the wiring material layer 30.
The remaining portion of P (the remaining portion of the laminate of the barrier layer 30a and the Al alloy layer 30b) and the remaining portion of the W layer 30c are formed. The connection portion 30B is formed of the remaining portion of the wiring material layer 30Q (the Al alloy layer 30d).
And the remaining portion of the laminated antireflection layer 30e). After the patterning, the mask portion 32b is removed.

In the process of FIG. 12, a silicon oxide insulating film 34 is formed on the insulating film 12 so as to cover the wiring layer 30 in the same manner as described with reference to FIG. Formed to a thickness of

In the step of FIG. 13, the insulating film 34 is connected to the connecting portion 30B by an etch-back process in the same manner as described with reference to FIG.
Until the top of the insulating film 34 is exposed, leaving a flat portion of the insulating film 34.

In the step of FIG. 14, a second wiring layer 36 connected to the connection portion 30B is formed on the flat portion of the insulating film 34 in the same manner as described with reference to FIG. As a result, the wiring layer 36
The connection part 30B is connected to the wiring part 30A.

According to the embodiment shown in FIGS. 7 to 14, the etching mask 32 is commonly used for forming the wiring portion 30A and the connecting portion 30B so that the connecting portion 30B is self-aligned with the wiring portion 30A. Formed in the wiring section 30
It is not necessary to align the connection portion 30B with A. Therefore, the wiring layer 30 does not need to have a margin for alignment, and the wiring pattern can be miniaturized. Further, one photomask 18 is sufficient, and it is not necessary to prepare separate photomasks for the wiring layer 3 and the connection portion 6 as in the method of FIG.

Further, a W layer 30c is provided between the first wiring material layer 30P and the second wiring material layer 30Q, and the wiring material layer 30Q
Is processed to form the connection portion 30B on the W layer 30c, and the W layer 30c and the wiring material layer 30P are processed to form the wiring portion 30.
A is formed, so the thickness of the wiring portion 30A is
It is determined accurately according to the total thickness of the wiring material layer 30P and the W layer 30c. Therefore, variations in the wiring thickness can be reduced.

The multilayer wiring forming method described above with reference to FIGS. 1 to 6 or FIGS. 7 to 14 can be applied to the formation of a multilayer wiring of three or more layers. For example, the method of FIGS. 1 to 6 will be described. After the step of FIG. 5, the wiring layer 3 is formed on the flat portion of the insulating film 24 as shown in FIGS.
7 and an insulating film 38 are formed, and a wiring layer 39 is formed on the flat portion of the insulating film 38 in the same manner as described with reference to FIG. The wiring layer 37 is formed so as to be connected to the wiring layer 14, and the wiring layer 39 is formed so as to be connected to the wiring layer 37. A passivation film 40 is formed on the flat portion of the insulating film 38 so as to cover the wiring layer 39.

16 to 19 show a first example of manufacturing the photomask 18. FIG.

In the step of FIG. 16, a chromium oxide layer 4 is formed on one main surface of a transparent plate such as a quartz plate via a chromium layer 42.
A blank on which No. 4 is formed is prepared. Then, a positive resist layer 46A sensitive to an electron beam is formed on the chromium oxide layer 44 by a spin coating method or the like.

In the step shown in FIG. 17, the resist layer 46A is exposed by a direct drawing method using an electron beam. In this case, in the resist layer 46A, a portion corresponding to neither the wiring pattern nor the connecting portion pattern connected thereto is irradiated with a strong electron beam Es so as to enable removal of the resist, and a portion corresponding to the wiring pattern is The resist is irradiated with a weak electron beam Ea so that the resist can remain at a predetermined thickness, and a portion corresponding to the connection pattern is not irradiated with the electron beam.

In the step of FIG. 18, the resist layer 46A is subjected to a developing process. As a result, the etching mask 46 having the first mask portion 46a formed of a relatively thin resist layer corresponding to the wiring pattern and the second mask portion 46b formed of the relatively thick resist layer corresponding to the connection pattern is formed of chromium oxide. Obtained on layer 44.

In the step of FIG. 19, the lamination of the chromium layer 42 and the chromium oxide layer 44 is patterned by selective dry etching using a mask 46. As a result, the chrome layer 42 remains according to the wiring pattern corresponding to the first mask portion 46a, and the lamination of the chromium layer 42 and the chromium oxide layer 44 remains according to the connection pattern corresponding to the second mask portion 46b. The portion of the chromium layer 42 remaining according to the wiring pattern is thinned by the dry etching even after the relatively thin first mask portion 46a is removed by the dry etching. After the patterning, the mask portion 46b is removed.

In FIG. 19, the photomask 18 includes a transparent plate 20, and first and second light shielding portions 22a and 22b formed on one main surface of the transparent plate. First
Is formed of a relatively thin portion of the chrome layer 42 remaining according to the wiring pattern. The second light-shielding portion 22b is formed by stacking a relatively thick portion of the chrome layer 42 remaining according to the connection pattern and a portion of the chromium oxide layer 44 remaining according to the connection pattern.

FIGS. 20 to 26 show a second example of manufacturing the photomask 18. FIG.

In the process of FIG. 20, a transparent plate 20 such as a quartz plate is used.
A blank is prepared in which a semi-permeable film 52, a chromium layer 54, and a chromium oxide layer 56 are sequentially laminated on one main surface. As the semi-permeable film 52, a MoSi-based film (for example, MoS
iON) or a CrO-based material is preferably formed to a thickness of 50 to 100 [nm]. The thickness of the chrome layer 54 is 1
05 [nm]. On the chromium oxide layer 56, as an example, a negative resist layer 58A sensitive to an electron beam is formed to a thickness of 500 [nm]. When a negative type resist layer is used as the resist layer 58A, the exposure area can be smaller than when a positive type resist layer is used.

In the step of FIG. 21, the resist layer 58A is exposed to light by a direct drawing method using an electron beam. In this case, the electron beam E is applied only to a portion of the resist layer 58A corresponding to the connection pattern connected to the wiring pattern.
The electron beam is not irradiated on the portion corresponding to the wiring pattern and the portion not corresponding to any of the wiring pattern and the connection portion pattern. Exposure with an electron beam
It can be performed under the condition of a dose of 8.5 μC / cm ² .

In the step of FIG. 22, the resist layer 58A is developed. As a result, an etching mask 58 made of a resist layer corresponding to the connection pattern is obtained. Next, the chromium layer 54 and the chromium oxide layer 58 are patterned by a selective etching process using the mask 58, so that the chromium layer 54 and the chromium oxide layer 58 are left according to the connection pattern corresponding to the mask 58. The etching at this time can be performed by spraying an etching solution containing ceric ammonium nitrate, perchloric acid, or the like. In the etching process at this time, the semi-permeable film 52 functions as an etching stopper, and the semi-permeable film 52 remains without being substantially etched. After the etching, the mask 58 is removed. The mask 58 may be left, and the resist may be overcoated in the next step of FIG.

In the step shown in FIG. 23, a negative resist layer 60A responsive to the electron beam is formed on the semi-transmissive film 52 so as to cover the remaining portions of the chromium layer 54 and the chromium oxide layer 56 for 500 [n].
m]. When a negative type resist layer is used as the resist layer 60A, the exposure area can be smaller than when a positive type resist layer is used.

In the step of FIG. 24, the resist layer 60A is exposed to light by a direct drawing method using an electron beam. In this case, in the resist layer 60A, the electron beam Ew is irradiated only on the portion corresponding to the wiring pattern and the connection portion pattern connected thereto, and the electron beam is not irradiated on the portion not corresponding to any of the wiring pattern and the connection portion pattern. . Exposure with an electron beam is performed at a dose of 8.5 μC / c.
It can be carried out under the condition of m ^2.

In the step of FIG. 25, the resist layer 60A is developed. As a result, the etching mask 6 made of a resist layer corresponding to the wiring pattern and the connection portion pattern is formed.
0 is obtained. Next, the semi-transmissive film 52 is selectively etched with an SF ₆ -based gas using a mask 60.
Of the semi-transmissive film 52 by patterning
0 is left according to the wiring pattern and the connection pattern corresponding to 0.

In the step of FIG. 26, the mask 60 is removed. When the mask 58 is left in the step of FIG.
The mask 58 is also removed. In FIG. 26, photomask 1
Reference numeral 8 includes a transparent plate 20, and first and second light-shielding portions 22a and 22b formed on one main surface of the transparent plate. The first light shielding portion 22a is a portion of the semi-transmissive film 52 that remains according to the wiring pattern. The second light-shielding portion 22b is formed of a portion of the lamination of the semi-transmissive film 52, the chromium layer 54, and the chromium oxide layer 56 which remains according to the connection pattern.

According to the manufacturing method shown in FIGS. 16 to 19 or FIGS. 20 to 26, a photomask suitable for use in carrying out the present invention can be obtained. In particular, according to the manufacturing method shown in FIGS. 20 to 26, the thickness of the light shielding portion 22b can be accurately determined according to the thickness of the semi-transmissive film 52, so that a highly accurate photomask can be obtained.

The present invention is not limited to the above embodiment, but can be implemented in various modified forms. For example, the following changes are possible.

(1) When the resist layer is exposed and developed to form an etching mask, a direct drawing method using an electron beam may be used instead of a method of transferring a pattern from a photomask.

(2) When transferring a pattern from a photomask, an X-ray, an electron beam,
An information carrier such as an ion beam may be used.

(3) 100% transmittance in photomask
The transparent part and the light-shielding part with a transmittance of 0% are each transmitted with a transmittance of 0%
And the resist layer 16A or 32A may be of a negative type.

(4) As the resist layer 16A or 32A, a single layer is used, but a layer in which a plurality of layers of different types are laminated may be used.

(5) As a means for planarly removing the insulating film, a CMP (chemical / mechanical polishing) process or the like may be used instead of the etch-back process.

[0060]

As described above, according to the present invention, the connection between the lower layer wiring and the upper layer wiring is formed in a self-aligned manner with respect to the lower layer wiring. Therefore, the effect that the wiring pattern can be miniaturized can be obtained. Further, there is an advantage that the number of photomasks is smaller than that of the method of FIG.

Further, as shown in the embodiment of FIGS. 7 to 14, a conductive layer for an etching stopper is provided between the first and second wiring material layers, and the second wiring material layer is processed to form a conductive layer. When the connection portion is formed on the layer and the wiring portion is formed by processing the conductive layer and the first wiring material layer, the thickness of the wiring portion corresponds to the total thickness of the conductive layer and the first wiring material layer. This has the effect of reducing variations in the wiring thickness.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate showing a resist exposure step in a multilayer wiring forming method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a resist development step following the step of FIG.

FIG. 3 is a cross-sectional view showing a wiring patterning step and a resist removing step subsequent to the step of FIG. 2;

FIG. 4 is a cross-sectional view showing an insulating film forming step following the step of FIG. 3;

FIG. 5 is a cross-sectional view showing an etch-back step following the step of FIG. 4;

FIG. 6 is a cross-sectional view showing a wiring layer forming step following the step of FIG. 5;

FIG. 7 is a cross-sectional view of a substrate showing a resist exposure step in a multilayer wiring forming method according to another embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a resist developing step following the step of FIG. 7;

9 is a cross-sectional view showing a step of selectively etching a first wiring material layer subsequent to the step of FIG. 8;

10 is a cross-sectional view showing a step of selectively etching a W layer following the step of FIG. 9;

11 is a cross-sectional view showing a step of selectively etching a second wiring material layer following the step of FIG. 10;

FIG. 12 is a cross-sectional view showing an insulating film forming step following the step of FIG. 11;

13 is a cross-sectional view showing an etch-back step following the step of FIG.

FIG. 14 is a cross-sectional view of the substrate showing a wiring layer forming step following the step of FIG. 13;

FIG. 15 is a sectional view showing a modified example following the step of FIG. 5;

FIG. 16 is a cross-sectional view showing a step of forming a resist layer in a first example of manufacturing a photomask.

FIG. 17 is a cross-sectional view showing a resist exposure step that follows the step of FIG. 16;

FIG. 18 is a cross-sectional view showing a resist developing step that follows the step of FIG. 17;

FIG. 19 is a cross-sectional view showing a selective etching step and a resist removing step subsequent to the step of FIG. 18;

FIG. 20 is a cross-sectional view showing a step of forming a resist layer in a second example of manufacturing a photomask.

21 is a cross-sectional view showing a resist exposure step that follows the step of FIG. 20.

FIG. 22 is a sectional view showing a resist developing step and a selective etching step following the step of FIG. 21;

FIG. 23 is a cross-sectional view showing a resist layer forming step following the step in FIG. 22;

24 is a cross-sectional view showing a resist exposure step that follows the step of FIG. 23.

FIG. 25 is a cross-sectional view showing a resist developing step and a selective etching step following the step of FIG. 24;

FIG. 26 is a cross-sectional view showing a resist removing step following the step of FIG. 25;

FIG. 27 is a cross-sectional view of a substrate illustrating an example of a conventional method for forming a multilayer wiring.

FIG. 28 is a cross-sectional view of a substrate showing another example of a conventional multi-layer wiring forming method.

[Explanation of symbols]

10: semiconductor substrate, 12, 24, 34: insulating film, 14
A, 30P, 30Q: wiring material layer, 14, 26, 30, 3
6: wiring layer, 16A, 32A: resist layer, 16, 3
2: etching mask, 18: photomask, 30c: W
Layer (conductive layer for etching stopper).

Claims (2)

[Claims] A step of forming a first wiring member layer on an insulating film covering the substrate; and forming a first mask portion corresponding to a desired wiring pattern on the first wiring member layer. A step of arranging an etching mask having a second mask portion corresponding to a connection portion pattern continuous with the wiring pattern, wherein the thickness of the second mask portion is set to be larger than the thickness of the first mask portion. And a wiring portion corresponding to the first mask portion by patterning the first wiring material layer by a selective etching process using the etching mask, and from the wiring portion to the second mask portion. Forming a first wiring layer having a correspondingly protruding connection portion; and, after removing the etching mask, covering the first wiring layer on the insulating film so as to cover a peak level of the connection portion. Thicker A step of forming an interlayer insulating film; a step of removing the interlayer insulating film planarly until the connection portion is exposed to leave a flat portion of the interlayer insulating film; and a flat portion of the interlayer insulating film. Forming a second wiring layer connected to the connection portion on the second wiring layer. 2. A step of sequentially forming a first wiring material layer, a conductive layer for an etching stopper, and a second wiring material layer on an insulating film covering a substrate; A step of disposing an etching mask having a first mask portion corresponding to a desired wiring pattern and a second mask portion corresponding to a connection portion pattern continuous with the wiring pattern, A mask having a thickness set to be larger than a thickness of the first mask; and a second selective etching process using the etching mask, wherein the second wiring material layer is patterned by the second selective etching. A first portion of the wiring material layer corresponding to the first mask portion of the etching mask and having a predetermined thickness, and a thickness corresponding to the second mask portion of the etching mask and larger than the predetermined thickness Sa Leaving a second portion having the second mask portion of the etching mask and first and second portions of the second wiring material layer and a second mask portion of the etching mask. The conductive layer is patterned by a second selective etching process using as a mask, the conductive layer is left in a pattern corresponding to the first and second portions of the second wiring material layer, and the etching mask is formed. And a third selective etching process using the remaining portion of the conductive layer and the second mask portion of the etching mask as a mask. And the second part and the first part
And forming a first wiring layer having a wiring portion corresponding to the first mask portion of the etching mask and a connection portion corresponding to the second mask portion of the etching mask. A step in which the wiring portion is formed by laminating a remaining portion of the first wiring material layer and a remaining portion of the conductive layer, and the connection portion is formed by a remaining portion of the second portion of the second wiring material layer. And after removing the second mask portion of the etching mask,
Forming an interlayer insulating film thicker than the peak level of the connecting portion over the insulating film so as to cover the first wiring layer; and removing the interlayer insulating film planarly until the connecting portion is exposed. Forming a second wiring layer connected to the connecting portion on the flat portion of the interlayer insulating film by a method of forming a second wiring layer on the flat portion of the interlayer insulating film.