JPH1083958A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to arrange a phase shift region with the relationship with various patterns being excellently maintained, by selecting the suitable resist processes respectively for the shapes of the pattern to be formed. SOLUTION: A metal film 263 is formed on the surface of a substrate 262. Photoresist is applied on the upper surface of the metal film 263. Then, an electron beam is radiated on the specified part of the resist by an electron-beam exposure method or the like based on the integrated circuit pattern data of a semiconductor integrated circuit device, and a specified pattern is transferred on the resist. Thereafter, a mask 209 having the specified pattern is manufactured after the processes of development, the etching of the specified part, the removal of the resist and the like. Then, by using the manufactured mask 209, the original image of the integrated circuit pattern on the mask 209 is projected on a wafer 215, on which the resist is applied. At the same timer with the wafer being moved stepwise, the image is transferred on the entire surface by repeating the projecting exposure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure technique, and more particularly to a technique effective when applied to a photolithography process of a semiconductor device.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor integrated circuits has increased and the design rules of circuit elements and wiring have reached the order of submicrons, circuit patterns on masks have been formed on semiconductor wafers using light such as g-line and i-line. In the photolithography process of transferring data onto the wafer, a serious problem is that the accuracy of the circuit pattern transferred onto the wafer is reduced. For example, the transmission regions P1 and P2 formed on the mask 20 as shown in FIG.
When the circuit pattern including the light shielding region N is transferred onto the wafer, a pair of transmission regions P1 and P
Since the phases of the light L immediately after passing through each of the two light beams are in phase as shown in FIG. 3B, the two light beams interfere with each other at a portion of the wafer which is originally a light-shielding region and strengthen each other (see FIG. (C), and as a result, as shown in FIG. (D), the contrast of the projected image on the wafer is reduced and the depth of focus is reduced, so that the pattern transfer accuracy is greatly reduced.

As means for solving such a problem, there has been proposed a phase shift technique for preventing a decrease in contrast of a projected image by changing a phase of light transmitted through a mask. For example, Japanese Patent Publication No. 62-59296 discloses that a transparent film is provided on one of a pair of transmission regions sandwiching a light-shielding region, and a phase difference is generated between light transmitted through the two transmission regions during exposure. There is disclosed a phase shift technique in which the interference light is weakened at a place on the wafer which is originally a light shielding area. That is, when a circuit pattern formed on the mask 21 as shown in FIG. 11A is transferred onto a wafer, a pair of transmissive regions P sandwiching the light shielding region N are provided.
A transparent film 22 having a predetermined refractive index is provided on one of P1 and P2. By properly adjusting the thickness of the transparent film 52, the light immediately after passing through each of the transmission regions P1 and P2 has a phase difference of 180 degrees as shown in FIG. In the light shielding region N on the wafer, these lights interfere with each other and are weakened (FIG. 3C). As a result, as shown in FIG. 2D, the contrast of the projected image on the wafer is improved, the resolution and the depth of focus are improved,
The transfer accuracy of the circuit pattern formed on the mask 21 is improved.

Japanese Patent Application Laid-Open No. 62-67514 discloses that a fine opening pattern is formed by removing a part of a light-shielding region of a mask, and then any of a transparent region existing in the vicinity of the opening pattern is formed. By providing a transparent film on one side and generating a phase difference between the light transmitted through the transmission area and the light transmitted through the aperture pattern, the amplitude distribution of the light transmitted through the transmission area is prevented from spreading in the horizontal direction. Is disclosed.

In the specification of the present application, a phase shift method in which a normal pattern (main pattern) and a shifter pattern (accompanying pattern, complementary pattern) for providing a phase inverted to the normal pattern are provided on one mask. The “mask phase shift method” is referred to as “on-mask phase inversion shift method” particularly when the amount of phase shift is (2n + 1) π; (where n is an integer).

Further, Japanese Patent Application Laid-Open No. 60-109228 discloses that two masks are simultaneously irradiated to improve the throughput of projection exposure, thereby simultaneously exposing portions corresponding to different chips of one wafer. A method is disclosed. Japanese Patent Application Laid-Open No. 60-107835 discloses that one exposure light is divided into two parts, thereby illuminating the same part of two masks having the same pattern, combining them, and exposing the wafer. Discloses a technique for performing exposure without any problem even if a mask defect is present on one side.

[0007]

However, a phase shift region is provided in a part of the transmission region of the mask, and a phase difference is generated between light passing therethrough and light passing through a transmission region in the vicinity thereof. In the conventional phase shift technique, since a plurality of various integrated circuit patterns are complicatedly arranged on an actual mask, it is extremely difficult to select a place where the phase shift region is arranged, and thus there is a remarkable restriction on the pattern design.

The inventor of the present invention considers the relationship between the shape of an integrated circuit pattern to be formed and a resist process in the process of manufacturing an integrated circuit using the phase shift technique, and determines the mask pattern by the shape of the pattern to be formed. The positive and negative types of resist to be exposed are selected and used properly, and by mixing a positive type resist and a negative type resist in one semiconductor device manufacturing method, a plurality of various patterns formed on a mask can be formed. While maintaining a good relationship,
It has been noticed that it is possible to arrange the phase shift regions.

It is an object of the present invention to provide a phase shift technique which solves the above-mentioned problems.

An object of the present invention is to provide a projection exposure technique capable of extending the exposure limit of a fine pattern by ultraviolet and far ultraviolet light to a further fine range.

An object of the present invention is to provide a mask pattern layout technique useful for manufacturing a semiconductor device using a phase shift method.

An object of the present invention is to provide a projection exposure technique effective for exposing a periodic fine pattern.

An object of the present invention is to provide a projection exposure technique effective for exposing an opening pattern.

Japanese Patent Application Laid-Open No. 1-283925 discloses a technique in which an opening is formed in a positive resist layer using a phase shift mask having a dot-shaped light transmitting portion, and a technique in which dots are formed in a negative resist layer using the same mask. Although a technique for forming a pattern is described, the relationship between a desired pattern shape and a resist process is not taken into consideration, and a positive type or a negative type resist is selectively used depending on the shape of an integrated circuit pattern to be formed. However, it does not disclose that a positive resist and a negative resist are mixed and used in one semiconductor device manufacturing process.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to one aspect of the present invention, a desired pattern for exposing a resist layer provided on a semiconductor substrate is formed by developing a first region and a second region surrounded by the first region. In the case of a pattern (opening pattern) in which the first region is left and the second region is removed, a positive resist is selected, and a pattern (isolated pattern) in which the first region is removed and the second region is left. In some cases, a negative resist is selected, and in a method of manufacturing one semiconductor integrated circuit device,
This is a method of manufacturing a semiconductor device in which a positive resist and a negative resist are used separately and mixed.

[0017]

According to the above-mentioned means, in a manufacturing process of one semiconductor device, an appropriate resist process can be selected depending on a shape of a pattern to be formed. Manufacturing is facilitated, and a semiconductor device having a fine pattern can be manufactured accurately.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following description of the embodiments of the present invention will be made into a plurality of sections for convenience, but each embodiment is not separate.
It corresponds to a part of a process related to a single invention or a modified example.
Therefore, description of the overlapping part will not be given unless it is particularly necessary. Further, with respect to reference numbers used in the following embodiments, those having the same last two digits shall have the same or similar structure or function unless otherwise specified.

(1) Embodiment 1 FIG. 1 shows a phase shift mechanism 1 of an exposure apparatus which is I according to Embodiment 1 of the present invention.

The phase shift mechanism 1 includes a beam expander 4, mirrors 5, 6, 9, half mirrors 7, 8, a corner mirror 10, and a corner mirror 10 provided between the light source 2 of the exposure apparatus and the sample 3 to be irradiated. The optical system comprises an optical path length varying mechanism 11 for minutely driving the mirror 10, a pair of lenses 12a and 12b, a reduction lens 13, and the like. A mask 14 on which an original image of a pattern to be transferred to the irradiation sample 3 is formed is positioned in the alignment system of the optical system. The mask 14 is, for example, a mask (reticle) used in a manufacturing process of a semiconductor integrated circuit device, and the irradiated sample 3 is, for example, a semiconductor wafer made of silicon single crystal.

The i-line (wavelength 365n) generated from the light source 2
The light L such as m) is expanded by the beam expander 4 and then refracted in the direction perpendicular to the main surface of the mask 14 via the mirror 5 and then goes straight through the half mirror 7 provided in the optical path. It is divided into two light L ₁ and the light L ₂ traveling in the direction perpendicular thereto to. Light L ₂ is refracted through the mirror 9 and the corner mirror 10, it is irradiated to another point of the mask 14 through the path different from the optical L _1. The two lights L ₁ and L ₂ transmitted through different portions of the mask 14 pass through the lenses 12 a and 12 b, are combined into one light L 1 via the mirror 6 and the half mirror 8, and then are reduced by the reduction lens 13. It is reduced and irradiated onto the irradiated sample 3 positioned on the XY table 15.

In the phase shift mechanism 1, since the two optical beams L ₁ and L ₂ from the half mirror 7 to the mask 14 have different optical path lengths, the phase shift mechanism 1 extends from the main surface of the mask 14 to the corner mirror 10. by varying the height (the length of the optical path of light L _2), it is possible to produce a desired phase difference between the two immediately after passing through the mask 14 of the light L _1, L _2. For example, the position of the corner mirror 10 when the phases of the two lights L ₁ and L ₂ immediately after passing through the mask 14 are the same as each other is defined as an origin, and the following equation

[0023]

D = (2m + 1) λ / 4 (1) By moving the corner mirror 10 in the vertical direction by the distance (d) defined by (λ: wavelength of light, m: integer),
The phases of the two lights L ₁ and L ₂ immediately after passing through the mask 14 can be opposite to each other (a phase difference of 180 degrees). The vertical movement of the corner mirror 10 is performed by using, for example, an optical path length variable mechanism 11 using a piezoelectric control element or the like.

FIG. 2 is an enlarged view of a cross section of the mask 14.

The mask 14 has, for example, a refractive index of 1.4.
It is made of about 7 transparent synthetic quartz glass or the like, and a metal layer 16 of Cr or the like having a thickness of about 500 to 3000 ° is formed on its main surface. At the time of exposure, the metal layer 16 becomes a light-shielding area A through which light does not pass, and the other area becomes a transmission area B through which light passes. The integrated circuit pattern is constituted by the light shielding area A and the transmission area B, and has, for example, a size five times the actual size.

FIGS. 3A and 3B show an example of a corrected circuit pattern formed on the mask 14. FIG. FIG.
The circuit pattern P1 shown in FIG. ₁ includes a shaded area A indicated by oblique lines and an L-shaped transmission area B surrounded by the shaded area A, for example. On the other hand, the transmission region B of the circuit pattern P ₂ shown in (b) has a transmissive region B and the same shape of the circuit pattern P _1, and the interior of the transmission region B in which the size is enlarged, the circuit pattern transmission region B and the same shape of P _1, has a pattern of arranging the light-shielding region a of the same size. That is, the transmission region B of the circuit pattern P ₂ is consistent with substantially the periphery of the transmissive area B of the circuit pattern P ₁ pattern. These two circuit patterns P ₁ , P
Reference numeral ₂ denotes a pair of patterns for transferring a circuit pattern P (hatched portion) as shown in FIG. 3C onto the wafer with high accuracy, and both are arranged at predetermined positions of the mask 14 at predetermined intervals. ing.

Next, a method of forming the mask 14 will be briefly described.

First, the surface of a synthetic quartz glass plate is polished and washed, and then, for example, a film having a thickness of 500 to 3
A Cr film of about 2,000 ° is deposited by a sputtering method, and then a photoresist is applied on the entire surface of the Cr film. Next, based on the integrated circuit pattern data coded in advance on a magnetic tape or the like, an integrated circuit pattern is drawn on the photoresist by an electron beam exposure method, and then the exposed portions of the photoresist are removed by development, and the exposed Cr film is exposed. Is removed by wet etching to form an integrated circuit pattern. The pattern data of the pair of circuit patterns P ₁ and P ₂ may be obtained by enlarging or reducing the data of the light shielding area A or the transmission area B of one of the circuit patterns, or by inverting the data of one of the circuit patterns and the other of the circuit patterns. And can be automatically created by taking a logical product with the data of Pattern data of, for example, the circuit pattern P ₂ is automatically created by taking the data obtained by enlarging the pattern of the through region B of the circuit pattern P _1, the logical product of the inverted data of the transmission region B of the circuit pattern P ₁ be able to.

The integrated circuit pattern formed on the mask 14
In order to transfer the pattern onto the wafer 3,
The wafer 3 coated with the strike is exposed to the X of the exposure apparatus shown in FIG.
The mask 14 is positioned on the Y table 15 and the mask 14 is aligned.
Positioning to the injection system. Mask 14 is a half mirror
One light L divided by -7₁Is the pair of circuits
Pattern P₁, P_TwoOne of the circuit patterns P₁above
When irradiated, the other light L_TwoIs the other circuit
Pattern P_TwoIt is performed so that it is accurately irradiated on the top. next,
Move the corner mirror 10 vertically and pass through the mask 14
Two lights L immediately after₁, L_TwoAre out of phase with each other
Adjustment of the phase difference as described above. Positioning and mask 14
Two lights L₁, L_TwoTo accurately adjust the phase difference of
For example, as shown in FIGS.
Such a pair of alignment marks M ₁, M_TwoUse
Mark M₁, M_TwoAre shaded areas A indicated by oblique lines.
For example, a square surrounded by the light shielding area A
And a transparent region B of
Their dimensions and shape are exactly the same. Mask 14
Positioning and light L₁, L_TwoAdjustment of the phase difference
Mark M₁Light L transmitted through₁And mark M_Two
Light L transmitted through_TwoMeans that they interfere with each other and disappear completely
The mark M on the wafer 3₁, M_TwoIs the projected image M of
It is not formed. That is, the projected image on the wafer 3
By determining the presence or absence of M, the position of the mask 14 can be determined.
M and light L₁, L_TwoAdjustment of the phase difference of
Can be easily determined.

After the positioning of the mask 14 and the adjustment of the phase difference between the lights L ₁ and L ₂ are performed in this manner, the original image of the integrated circuit pattern formed on the mask 14 is optically
/ 5 is projected onto the wafer 3 and the above operation is repeated while the wafer 3 is sequentially moved stepwise.

[0031] FIG. 4 (a) is a cross-sectional view of the mask 14 in the circuit pattern P ₁ is formed region, and FIG. 4 (b)
Is a cross-sectional view of the mask 14 in the circuit pattern P ₂ is formed regions.

[0032] The circuit pattern light L ₂ immediately after the transmission region B has passed through the transmission region B immediately after transmitting light L ₁ and the circuit pattern P ₂ of P _1, shown in FIG. 4 (a), (b) Thus, the phases are opposite to each other. Further, the transmission region B of the circuit pattern P ₂ is because it matches the pattern of the peripheral portion of the transmission region B of the circuit pattern P _1, the amplitude of the combined beam L of the two light L _1, L ₂ the figure ( It becomes like c). Therefore, when the combined light L is irradiated onto the wafer 3, as shown in FIG. 3D, the combined light L interferes and weakens at the boundary between the original lights L ₁ and L ₂ . As a result, as shown in FIG. 3E, the contrast of the image projected on the wafer 3 is greatly improved, and the resolution and the depth of focus are greatly improved.

[0033] Until this manner the exposure apparatus of the first embodiment, the light L generated from the light source 2 is divided two to the light L _1, L _2, of the two light L _1, L ₂ reaches the mask 14 Of the two lights L ₁ and L ₂ immediately after passing through the mask 14, the phases of the two lights L ₁ and L ₂ are made opposite to each other.
₁ and L ₂ are synthesized and irradiated onto the wafer 3. The mask 14 of the first embodiment, the transmission region B of one of the circuit pattern P ₂ is a pair that match the pattern of the peripheral portion of the other circuit pattern P ₁ in the transmission region B circuit pattern P
₁ and P ₂ . Therefore, by transferring the integrated circuit pattern formed on the mask 14 onto the wafer 3 using the exposure apparatus, the light L ₁ transmitted through the transmission region B of the circuit pattern P _{1 and} the transmission of the circuit pattern P ₂ are transmitted. The light L obtained by synthesizing the light L ₂ transmitted through the region B interferes with each other at the boundary between the original lights L ₁ and L ₂ and is weakened, so that the contrast of the image projected on the wafer 3 is reduced. This is greatly improved, and the circuit pattern P can be transferred onto the wafer with high accuracy.

Therefore, the following effects can be obtained in the first exposure method of the first embodiment.

(1) Unlike the conventional phase shift technique, there is no need to provide a phase shift means such as a transparent film on the mask, so that there is no restriction on the pattern design. In I of the first embodiment, when transferring one circuit pattern onto a wafer, it is necessary to form a pair of circuit patterns on a mask. It can be automatically created by enlarging or reducing the data in the transmission area or by taking the logical product of the inverted data of one circuit pattern and the data of the other circuit pattern.

(2) The step of inspecting the transparent film for defects, which is indispensable in the conventional phase shift technique, is not required. In I of the first embodiment, the defect inspection of a pair of circuit patterns can be performed in the same manner as a normal mask by comparing with the original pattern data. Also, the dimension inspection can be performed by laser measurement or the like in the same manner as a normal mask. Therefore, the mask inspection process does not become complicated.

(3) Since no phase shift means such as a transparent film is provided on the mask, cleaning can be performed in the same manner as in a normal mask. Therefore, it is possible to create a mask free of foreign matter as much as a normal mask.

(4) According to the above (1) to (3), it is possible to improve the transfer accuracy of the circuit pattern without requiring much time and labor for manufacturing the mask.

FIGS. 6 (a) and 6 (b) show I of the first embodiment.
11 is another example (II of the first embodiment) of a pair of circuit patterns formed on the mask of FIG.

Each of the circuit pattern P ₁ shown in FIG. 7A and the circuit pattern P ₂ shown in FIG. 7B is surrounded by a shaded area A indicated by oblique lines and surrounded by the shaded area A, for example. And a rectangular transmission area B. A pair of circuit patterns P ₁ and P ₂ are a pair of patterns for transferring a circuit pattern P (hatched portion) as shown in FIG. The parts are arranged at predetermined intervals. The circuit pattern P is
Four patterns P _A , having the same size and shape,
It consists of P _B , P _C , and P _D. Transmission region B of the circuit pattern P _1
A corresponds to the pattern P _A, transmission region B _C of the circuit pattern P ₁ corresponds to the pattern P _C. Further, the transmission region B _B of the circuit pattern P ₂ in the pattern P _B, the transmission region B _D of the circuit pattern P ₂ respectively correspond to the pattern P _D.
That is, the circuit pattern P is a pattern in which the transmission areas B of the pair of circuit patterns P ₁ and P ₂ are alternately arranged.

FIG. 7A is a partial sectional view of the mask 14 in a region where the circuit pattern P ₁ is formed.
(B) is a partial sectional view of the mask 14 in the circuit pattern P ₂ is formed regions.

[0042] The circuit pattern light L ₂ immediately after the transmission region B has passed through the transmission region B immediately after transmitting light L ₁ and the circuit pattern P ₂ of P _1, shown in FIG. 7 (a), (b) like,
The phases are opposite to each other. Further, the combined light L of the two light L _1, L _2, the boundary portions of the original light L _1, L ₂ as shown in FIG. 1 (c) to approach each other. Therefore, this combined light L 'is irradiated on the wafer 3, as shown in FIG. 2 (d), weakened by interfering with the original light L _1, L ₂ of the boundary portion. As a result, as shown in FIG. 3E, the contrast of the image projected on the wafer 3 is greatly improved, and the resolution and the depth of focus are greatly improved.

FIGS. 8 (a) and 8 (b) show I of the first embodiment.
11 is still another example (III of Embodiment 1) of a pair of circuit patterns formed on the mask of FIG.

The circuit pattern P ₁ shown in FIG. 3A comprises a shaded area A indicated by oblique lines and a square transmission area B surrounded by the shaded area A. on the other hand,
Transmission region B of the circuit pattern P ₂ shown in (b) is arranged on the outside of each side of the transmission region B of the circuit pattern P _1. The pair of circuit patterns P ₁ and P ₂ are shown in FIG.
Are a pair of patterns for transferring a circuit pattern P (hatched portion) onto the wafer with high accuracy, and both are arranged at predetermined positions of the mask 14 at predetermined intervals.

FIG. 9A is a partial cross-sectional view of the mask 14 in a region where the circuit pattern P ₁ is formed.
Figure (b) is a partial sectional view of the mask 14 in the circuit pattern P ₂ is formed regions.

[0046] The circuit pattern light L ₂ immediately after the transmission region B has passed through the transmission region B immediately after transmitting light L ₁ and the circuit pattern P ₂ of P _1, shown in FIG. 9 (a), (b) like,
The phases are opposite to each other. Further, the combined light L of the two light L _1, L _2, the boundary portions of the original light L _1, L ₂ as shown in FIG. 1 (c) are close to each other. Therefore, this combined light L 'is irradiated on the wafer 3, as shown in FIG. 2 (d), weakened by interfering with the original light L _1, L ₂ of the boundary portion. As a result, as shown in FIG. 3E, the contrast of the image projected on the wafer 3 is greatly improved, and the resolution and the depth of focus are greatly improved.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

In the above description, the case where the invention made by the present inventor is mainly applied to a mask used in a manufacturing process of a semiconductor integrated circuit device, which is a background of application, has been described. The present invention is not limited thereto, and can be widely applied to all exposure techniques for transferring a predetermined pattern formed on the mask by irradiating the sample to be irradiated with light transmitted through the mask.

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

A mask formed with a predetermined pattern including a light-shielding region and a transmission region is irradiated with light, and the light transmitted through the transmission region of the mask is irradiated onto a sample to be irradiated, thereby forming the mask. When transferring a predetermined pattern onto the sample to be irradiated, the light generated from the light source is split into two lights, and the two light rays are changed in optical path length until reaching the mask, whereby the mask is masked. According to the exposure method of the present invention in which the phases of the two lights immediately after passing through different portions are opposite to each other, and then the two lights are combined and irradiated onto the irradiation target sample, the predetermined transmission area on the mask At a place where one light that has passed through the mask and the other light that has passed through the other transmission area on the mask are located close to each other on the sample to be irradiated, the two lights interfere with each other at their boundary area and are weak. Because fits the contrast of the projected image is greatly improved.

As a result, it is possible to improve the pattern transfer accuracy without requiring much time and labor for manufacturing the mask.

(2) Embodiment 2 A typical one of the inventions disclosed in this embodiment will be described as follows.

The first invention has a first pattern and a second pattern having a light-shielding region and a transmission region, respectively.
A mask for irradiating the two types of patterns with at least partially coherent two lights having a phase difference, synthesizing transmission patterns of the lights, and forming a desired pattern on a sample to be irradiated. Therefore, at the boundary where the accuracy of the desired pattern is required, the light transmitted through the transmission region of the first pattern and the light transmitted through the transmission region of the second pattern interfere and weaken each other. The first pattern and the second pattern are formed on the same substrate, or the first pattern and the second pattern are separately formed on two substrates.

In the invention of the second exposure apparatus, the light source for generating the at least partially coherent light beam, the light beam splitting means for splitting the coherent light beam into two,
An optical phase shift member placed on one of the optical paths from the light beam splitting means until the light beam is synthesized again, and an optical system for synthesizing the light beam transmitted through the first pattern and the second pattern into a single light beam And an optical system for reducing and projecting the single luminous flux onto the sample to be irradiated, wherein the optical phase shift member controls the phase of the light transmitted through the first pattern and the phase transmitted through the second pattern. Was shifted to 180 degrees to create a desired pattern synthesized on the sample to be irradiated.

In the invention of the third exposure method, the first pattern and the second pattern on the first mask are irradiated with at least partially coherent two lights having a phase difference, respectively, A desired pattern was formed on a sample to be irradiated by combining light transmission patterns.

In this specification, an at least partially coherent light beam refers to a light beam having sufficient coherence to achieve the effect of interference and destruction.

Further, in this embodiment, the boundary portion includes not only the boundary of the line segment constituting the pattern of the desired pattern but also the region sandwiched between the two line segments.

According to the above means, the light transmitted through the transmission area of the first pattern and the light transmitted through the transmission area of the second pattern interfere with each other at the boundary where the accuracy of the desired pattern is required. The first and second patterns on the mask forming the first and second patterns are irradiated with at least partially coherent two lights each having a phase difference so as to weaken each other. Since the desired patterns are formed on the sample to be illuminated by synthesizing the transmission patterns of the light, the transfer accuracy of the boundary where the desired pattern accuracy is required can be improved.

FIG. 12 is a structural view of a main part of an exposure optical system as an embodiment of an exposure apparatus using a mask according to the present invention, and FIGS.
Is a plan view of a main part of the mask of the present invention using the exposure optical system, FIGS. 16 to 18 respectively correspond to FIGS.
FIG. 4 is an explanatory diagram illustrating amplitude and intensity of light that has passed through a mask.

The exposure apparatus of this embodiment is roughly divided into four functionally.
Consists of two elements. The first element irradiates the mask 209 with two light beams having a phase difference (first element), the second element composed of the mask 209 (second element), and the third element that transmits two transmitted lights of the mask 209. An element (third element) that synthesizes and irradiates the irradiated sample 215 in a reduced size, and a fourth element that includes an alignment mechanism that adjusts the synthesis of a single light beam (fourth element)
Element).

The first element includes a light source 201 that emits partially coherent light, an expander 202 that expands the light emitted from the light source 201, mirrors 203 and 206 that bends the optical path, and a part of the incident light that transmits. The half mirror 204 partially reflects the light, and the phase shift member 205 changes the phase of light. The third element includes lenses 201 and 211 for converting two transmitted lights from the mask 209 into parallel light, a mirror 212, a half mirror 213, a reduction lens 214 for reducing light, a sample to be irradiated 215, and a movable object. It comprises a sample stage 216. The fourth element includes an alignment mechanism 207 for moving the mirror 203, the half mirror 204, the lens 210, and the mirror 212, and a control circuit 208 therefor.

In the above description, the mirror 203 is provided to reduce the size of the entire apparatus.
3, the light from the expander 202 may be directly incident. The half mirror 204 has a function of dividing the light from the expander 202 into two, and is arranged on the first pattern 209 a on the mask 209. The phase shift member 205 is placed between the half mirror 204 and the mirror 206 or between the mirror 212 and the half mirror 213, and has a function of shifting the phase by a predetermined amount. As the phase shift member 205, for example, synthetic quartz glass having a refractive index of 1.47 is used. The mask 209 is disposed and the phase shift member 205
The first light flux 230 from the mirror 212 without the
And the second light flux 231 from the lens 211 has a phase difference of 0, the thickness d of the phase shift member is λ for the wavelength of the light source and n for the refractive index of the member.

[0063]

D = mλ / 2 (n-1) (2) (m: integer) is used.

The phase shift member 205 is used because of the light transmitted through the phase shift member 205 and the light not transmitted through the phase shift member 205 out of the light transmitted through the two transmission regions during exposure. This is for generating a phase difference of 180 degrees between them. For example, the wavelength λ of the light irradiated at the time of exposure
Is 0.365 μm (i-line) and the refractive index n of the phase shift member 205 is 1.5, the phase shift member 205
Thickness X ₁ may be the m (integer) times of 0.365 .mu.m.

The mirror 206 is a mirror for making the light transmitted through the half mirror 204 and the light transmitted through the phase shift member 205 parallel. Note that the two patterns 209a and 209b on the mask 209 are two lights 330 and 331.
Are arranged so as to be orthogonal to.

The lenses 210 and 211 are usually arranged so that the centers of the optical axes thereof coincide with the centers of the patterns 209a and 209b, respectively. The half mirror 213 is for combining the two lights 230 and 231. The mirror 212 has a function of bending the light 230 for the synthesis.

The alignment mechanism 207 for the fourth element is a mechanism for moving a part of the optical system of the exposure apparatus necessary for positioning, and uses a piezoelectric element or the like. In FIG. 12, the mirror 203, the half mirror 204, the lens 210, and the mirror 212 are configured to move, but the type and number of optical elements to be moved naturally change depending on the configuration of the exposure apparatus. The method for controlling the movement of the alignment mechanism 7 will be described later.

Next, the structure of the mask 209 of the present invention, which is the second element, will be described.

First, it is assumed that the pattern (desired pattern) to be formed on the sample 215 to be irradiated is an inverted L-shaped pattern 229 having a two-dimensional spread as shown in FIG. FIGS. 13A and 13B are plan views of an example of a first pattern 209a and a second pattern 209b, respectively, formed on a mask 209 to form such a desired pattern. The arrangement is performed while maintaining the relative positional relationship in consideration of the desired pattern (c) synthesized in 215.

Both the first pattern 209a and the second pattern 209b are formed from a combination of a light shielding area and a transmission area. These patterns may be formed on a single substrate, or may be separately formed on two glass substrates. However, in this case, the difference in the thickness of the glass substrate is also corrected by the thickness of the phase shift member. In FIG. 13, the transmissive area is shown by a white surface, and the light-shielding area is shown by oblique lines.

The transmission pattern 232 in FIG. 13A has an inverted L-shaped transmission area, and the transmission pattern 236 in FIG. 13B has a slightly smaller inverted L-shaped transmission area in the inverted L-shaped transmission area. A shielding region 234 is provided, and is configured to have a band-shaped transmission region 236.

Next, the operation of the present invention will be described.

At least partially coherent light source 2
The light emitted from 01 is expanded by the expander 202,
After bending the optical path with the mirror 203, the half mirror 20
4 divides the light into two light beams. Half mirror 20
4 is usually one having a transmission of 50% and a reflection of 50% (more strictly speaking, one having the same reflectance and transmittance). A phase shift member 205 is disposed on the optical path to one optical system of the two light beams. The light transmitted through the phase shift member 205 is given a phase difference of 180 degrees,
Pattern 209b. On the other hand, the light transmitted through the half mirror 204 is the first pattern 2 of the mask 209.
09a.

The two light beams transmitted through the two patterns 209a and 209b formed on the mask 209 are converted into parallel light beams by the lenses 210 and 211 again and then combined. That is, the first pattern transmitted through the first pattern 209a
After the optical path of the light 230 is bent by the mirror 212, the second light 231 having passed through the lens 211 and the half mirror 213 are combined into a single light flux.

After that, using the reduction lens 214, the mask 2 is applied to the irradiated sample 215 held on the movable sample table 216.
Irradiation is performed in a state where two patterns 209 a and 209 b on 09 are combined, and a desired pattern is formed on the irradiation target sample 215.

Here, when projecting the desired pattern shown in FIG. 13C, if the transmitted light of the first pattern 209a and the transmitted light of the second pattern 209b are combined with a phase difference of 180 degrees, the reason is as follows. Whether the transfer accuracy of the pattern of the mask 209 is improved will be described.

First, as described above, the first pattern 232 of the mask 209 is formed into a pattern 232 having an outer periphery slightly larger than the outer periphery of the desired pattern 229 and having a transmissive area inside the first pattern 232 in consideration of the reduction magnification. I do. Then, the second transmission pattern 236 is formed into the first
And a band-shaped transmission pattern 236 formed when a shielding pattern 234 having the same size as the desired pattern 229 to be obtained is drawn from the pattern 232.

With this configuration, the light transmitted from the second transmission pattern 236 and the light transmitted from the first transmission pattern 23 are provided in the peripheral area 238 of the desired pattern 229 to be obtained.
The transmitted light from the band-like region 236 inside the second pattern 2 is weakened by light interference, and the boundary of the desired pattern 229 can be sharpened. The desired pattern 229 is the second pattern.
Is combined with the transmission area 234 on the first pattern side having the same size as that of the first pattern side, so that the exposure is the same as normal exposure and a pattern is formed.
In FIG. 13C, a portion irradiated with light is indicated by hatching, and a portion that is weakened by interference is indicated by a white area 2.
38, and has a pattern opposite to that of FIGS. 13 (a) and 13 (b).

FIGS. 16A and 16B respectively show the mask 2
09, the first pattern 209a and the second pattern 20
It is the figure which showed the YY sectional drawing of 9b. Reference numeral 262 indicates a substrate, and reference numeral 263 indicates a shielding member. FIG. 16 (a),
(B) shows the amplitude of the light immediately after transmission through the mask. In each of the transmission region 232 and the transmission region 236 of the mask, the light (b) transmitted through the phase shift member and the light transmitted through the phase shift member 205 are transmitted. There is no light (a)
It can be seen that a phase difference of 180 degrees occurs. FIG.
(C) is a diagram showing the amplitude of light transmitted through the first pattern and the second pattern and immediately after synthesis.

If irradiation is performed only with the first pattern 232, the amplitude of light on the wafer becomes gentle at the periphery of the pattern due to diffraction of light, and the boundary is not sharpened. However, in this embodiment, FIG.
The light 242 having a phase difference of 180 degrees transmitted through the transmission region 236 in FIG. 13 is disposed around the light 240 transmitted through the transmission region 232 in FIG. As a result, the degree of decrease in the light amplitude becomes significant. Therefore, the blur of the outline portion of the image projected on the wafer is reduced, the contrast of the projected image is greatly improved, and the resolution and the depth of focus are greatly improved (FIG. 16D). Since the light intensity is the square of the light amplitude, the waveform on the negative side of the light amplitude on the wafer is inverted to the positive side as shown in FIG.

As described above, according to the mask of this embodiment, when the desired pattern to be obtained is a pattern having a two-dimensional spread, the first pattern is replaced with the two-dimensional pattern (the desired pattern) at a relative position on the mask. 2), the second pattern is a strip-shaped transmission pattern having an outer periphery slightly larger than the outer periphery of the first pattern. It is possible to sharpen only a boundary portion of a desired pattern having a spread.

The mask 209 has alignment marks for aligning the first pattern 209a and the second pattern 209b. The driving of the alignment mechanism 207 is controlled by the alignment marks.

FIG. 20 shows an example of a mark for aligning two divided patterns. This mark pattern has exactly the same configuration, the same relative position and the same size in (a) and (b). The shape of the mark is not limited to a square as shown in the figure, and an L-shaped or cross-shaped figure can be used. However, it is better to provide a plurality of the same shapes for each direction in order to increase the accuracy. Also, in principle, these alignment marks are provided on the mask 209 only in dimensions required for alignment of the alignment mechanism 207. That is, if two-dimensional alignment of the XY axis is required, these marks are also required in the two-dimensional direction of the XY axis, but in the case of an apparatus as shown in FIG. Often sufficient.

When the transmitted light that has passed through the mark has a phase difference of 180 degrees and the positional relationship is correctly adjusted, the transmitted light is the same as the light that is completely shielded.
Therefore, the state of the light shielding may be monitored by a CRT or the like, and when the condition is satisfied, the positioning may be completed.

Conversely, if the light is not completely shielded at the time of initial setting, the alignment mechanism 207 is driven so that the positions (a) and (b) are aligned so that the light is shielded. It will be good.

Next, a method of manufacturing the mask 209 of this embodiment will be described with reference to FIG.

As the mask 209 of this embodiment shown in FIG. 12, a mask (reticle) used in a predetermined manufacturing process of a semiconductor integrated circuit device is used. In addition, the mask 2 of the present embodiment
In 09, for example, an original image of an integrated circuit pattern five times the actual size is formed, and is constituted by a light-shielding region A and a transmission region B.

In manufacturing, first, a surface of a transparent substrate 262 made of quartz glass or the like is polished and washed, and then a metal layer 263 made of Cr or the like having a thickness of, for example, about 500 to 3000 ° is formed on the surface by a sputtering method. And the like. Next, on the upper surface of the metal layer 263, for example, 0.4
.About.0.8 .mu.m of photoresist (hereinafter referred to as "resist") is applied. Subsequently, after pre-baking the resist, a predetermined portion of the resist is irradiated with an electron beam E by an electron beam exposure method or the like based on the integrated circuit pattern data of the semiconductor integrated circuit device which is pre-encoded on a magnetic tape or the like. In the integrated circuit pattern data, the position coordinates and the shape of the pattern are recorded.

Next, for example, the patterns (a) and (b) are transferred to the resist by an electron beam exposure method or the like based on the pattern data shown in FIGS.

The pattern data (a) and (b) are automatically created by enlarging or reducing the pattern width of the light-shielded area A or the transparent area B of the integrated circuit pattern data. For example, in the present embodiment, (a) increases the pattern width of the light shielding area by, for example, about 0.5 to 2.0 μm, and (b)
The pattern data can be automatically created by taking the logical product of this and the inverted data of the original data.

Thereafter, through processes such as development, etching of a predetermined portion, removal of the resist, cleaning, and inspection, the process shown in FIG.
A mask 209 having the pattern shown in FIGS.
Is manufactured.

In order to transfer the integrated circuit pattern on the mask 209 onto the irradiated sample 215 (hereinafter simply referred to as a wafer) to which a resist has been applied using the mask 209 manufactured as described above, for example, To do.

That is, the mask 209 and the wafer are arranged in the reduction projection exposure apparatus shown in FIG. 12, and the original image of the integrated circuit pattern on the mask 209 is optically reduced to 1/5 and projected onto the wafer. Each time the wafer is sequentially moved in steps on the sample stage 216, the integrated circuit pattern on the mask 209 is transferred to the entire surface of the wafer by repeating the projection exposure.

Next, another example of the mask according to this embodiment will be described.

FIGS. 14A and 14B are main part configuration diagrams of the mask according to the present invention, and FIGS. 14A and 14B show the first and second patterns of the mask 209 of FIG. 12, respectively. ,
It is the top view which divided | segmented the mask pattern keeping the relative positional relationship in consideration of the desired pattern. (C) is a plan view of the synthesized desired pattern. FIG.
15E is a diagram for explaining the amplitude and intensity of light transmitted through the transmission region of the mask shown in FIG. The exposure apparatus and the method used are the same as those in the above embodiment.

In the embodiment shown in FIG. 14, when the desired pattern 248 is a one-dimensional pattern in which the lines 244 to 247 are arranged in a line in the horizontal direction, the pattern on the mask for sharpening the boundary is used. 2 shows a configuration. In this case, the above-mentioned line 244 is placed on the relative arrangement of the mask.
247, the transmission regions 249 and 250 of the first pattern forming the lines 244 and 246 and the transmission regions 251 and 252 of the second pattern forming the lines 245 and 247 are alternately arranged. Then, an area weakened by interference comes to the intermediate area 255 of each line constituting the desired pattern 248, and each line becomes sharp.

The relationship will be described with reference to FIGS. 17A to 17E when only the lines 244 and 245 are extracted from the desired pattern. Also in this case, there is a 180-degree phase difference between the light 256 transmitted through the transmission region 249 of the first pattern and the light 257 transmitted through the transmission region 251 of the second pattern (FIG. ), (B)). Therefore, in the desired pattern on the wafer, these lights are reflected in an area 255 between the two lines 244 and 245 as shown in FIG.
The light components indicated by 259 and 260 in (d) cancel each other due to interference with each other, and the slope 261 of the light amplitude increases as shown in FIG. Therefore, a sharp boundary can be formed in a region between the lines 244 and 245 shown in FIG. FIG. 17D is a diagram schematically showing the amplitude of light on the wafer before interference.

As a result, the contrast of the projected image of the one-dimensional pattern can be greatly improved, and the resolution and the depth of focus can be greatly improved (FIG. 17).
(E)).

According to the present embodiment, when the desired pattern is a one-dimensional pattern in which the lines are arranged in a line in the horizontal direction, the first line forming the line at a relative position on the mask. The transmission area of the pattern and the transmission area of the second pattern are alternately arranged, and the interfering and weakening area is arranged in the middle of each line constituting the desired pattern, whereby the two-dimensional pattern is formed. In the case where a plurality of lines are arranged in an area that is too small to take the above method, the transfer accuracy can be greatly improved.

Next, other examples of the mask according to the present invention will be described.

FIGS. 15A and 15B are main part configuration diagrams of the mask according to the present invention, and FIGS. 15A and 15B show the first and second patterns of the mask 209 of FIG. 12, respectively. ,
It is the top view which divided | segmented the mask pattern keeping the relative positional relationship in consideration of the desired pattern. (C) is a plan view of the synthesized desired pattern. FIG.
17E is a diagram for explaining the amplitude and intensity of light transmitted through the transmission region of the mask shown in FIG. The exposure apparatus and the method used are the same as those in the above embodiment.

The desired pattern 269 of the present embodiment is obtained by forming a small sub pattern 2 around a square mask pattern 270.
72.

Although it has been difficult to transfer such a fine sub-pattern 272 around the two-dimensional pattern 270 with high accuracy by a conventional method of attaching a phase transparent film to a mask, the present invention provides a simple method. Desired pattern 26
9 can be made. That is, also in the mask of the present embodiment shown in FIG.
The pattern 274 having a transmission area of the same size as the two-dimensional pattern 270 in consideration of the reduction magnification
By setting the second pattern to the fine pattern 276, as shown in FIGS. 18A to 18E, the light 277 transmitted through the phase shift member and the phase A phase difference of 180 degrees occurs between the light 278 not passing through the shift member 205 and the light 278 (FIG. 18A,
(b)) Since these lights interfere with each other in the region 280 between the two-dimensional pattern and the minute pattern, it is possible to reduce the blur of the image projected on the wafer. As a result, the contrast of the projected image can be greatly improved, and the resolution and the depth of focus can be greatly improved (FIG. 18E).

According to the masks according to these embodiments,
The following effects can be obtained.

At the time of exposure, the light transmitted through the transmission area of the first pattern and the light transmitted through the transmission area of the second pattern interfere with each other and weaken each other at the boundary where the accuracy of the desired pattern is required. As described above, since the first pattern and the second pattern are configured, the blur of the outline portion of the image projected on the wafer is reduced, the contrast of the projected image is greatly improved, and the resolution and the depth of focus are improved. It can be greatly improved. As a result, even if the same wavelength is used with the same projection lens as before, the resolution limit can be greatly increased. Therefore, even if the pattern on the mask is as complicated as an integrated circuit pattern and fine, the transfer accuracy of the entire pattern formed on the mask is greatly reduced without partially reducing the pattern transfer accuracy. It can be improved.

Also, since two patterns are prepared and the phase shift effect is obtained by the synthesized pattern, the transparent film is not provided on the mask surface, and the conventional transparent film is provided on the mask. Such inspection inconvenience is eliminated.

Further, since there is no step of attaching a transparent film,
The mask manufacturing time can be greatly reduced as compared with a mask using a transparent film on a mask substrate as a phase shift means.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, according to the exposure method using the mask of the present invention, the structure of the apparatus is not limited to the specific one, and the light flux is not limited to two.
The present invention is not limited to the configuration of the above-described embodiment in which the light beam is divided and used. The light beam may be divided into a plurality of light beams, each having a phase difference, and a pattern of a plurality of masks may be synthesized and exposed.

In the above description, the invention made by the present inventor has been mainly described with respect to the manufacturing technology of the semiconductor device, which is the application field in which the invention is based. However, the present invention is not limited thereto. It is clear that the method can be widely applied to the technical field of exposure to which the image formation improving effect can be applied.

The effects obtained by typical ones of the inventions disclosed in this embodiment will be briefly described as follows.

That is, at the boundary where the accuracy of the desired pattern is required, the light transmitted through the transmission region of the first pattern and the light transmitted through the transmission region of the second pattern interfere and weaken each other. Irradiating the first pattern and the second pattern on the mask constituting the first pattern and the second pattern with at least partially coherent two lights having a phase difference, respectively, Since the desired pattern is created on the sample to be irradiated by synthesizing the transmission patterns, the transfer accuracy at the boundary where the accuracy of the desired pattern is required can be improved.

The two masks described in Embodiments 1 and 2 are combined with a normal main pattern and a main pattern or a fine shift pattern (accompanying pattern) to be given a phase shift of π or an equivalent phase shift. This method is referred to as a “multi-mask phase shift method” or a “multi-mask phase inversion shift method” in this specification.

(3) Third Embodiment FIG. 21 shows a phase shift mechanism 301 of an exposure apparatus (1: 5 reduction projection / step-and-repeat method) according to a third embodiment of the present invention.

In the figure, a phase shift mechanism 301
A beam expander 304, mirrors 305, 307, 308, and half mirrors 306, 31 provided between a light source 302 of an exposure apparatus and a sample to be irradiated 303 (wafer).
3. Optical axis shifter 309, corner mirror 310, variable optical path length mechanism 31 for reducing and driving this corner mirror
1. An optical system including a pair of relay lenses 312a and 312b, a reduction lens system 315, and the like. The mask 314 (or reticle) on which the original image of the pattern to be transferred to the irradiation sample 303 is formed is positioned in the alignment system of the optical system. The mask 314 is, for example, a mask (reticle) used in a manufacturing process of the semiconductor integrated circuit device, and the irradiation target 303 is, for example, a semiconductor wafer made of silicon single crystal.

The i-line (wavelength 365) generated from the light source 302
nm) is expanded by a beam expander 304 and then through a mirror 305 to a mask 314.
After being refracted into the main surface perpendicular direction and is divided into a light L ₂ traveling in the direction perpendicular to the optical L ₁ and which is straight through the half mirror 306 provided in the optical path. Light L ₂ is refracted through the mirror 307 and the corner mirror 310, passes through the light L ₁ and the different paths are irradiated elsewhere mask 314. The two lights L ₁ and L ₂ transmitted through different portions of the mask 314 pass through lenses 312 a and 312 b, are combined into one light L via a mirror 308 and a half mirror 313, and then are reduced by a reduction lens 315. The image is irradiated onto the sample 303 to be irradiated, which is reduced and positioned on the XY table 316.

In the phase shift mechanism 301, since the optical path lengths of the light L ₁ and L ₂ after passing through the half mirror 306 are different, the height from the main surface of the mask 314 to the corner mirror 310 (light L ₂ ), a desired phase difference can be generated between the lights L ₁ and L ₂ arriving at the wafer 303. The vertical movement of the corner mirror 310 is performed using, for example, an optical path length variable mechanism 311 using a piezoelectric control element.

FIG. 22 is an enlarged view of a cross section of the mask 314. The mask 314 is made of, for example, a transparent synthetic quartz glass 322 having a refractive index of about 1.47,
A metal layer 323 of Cr (chromium) or the like having a thickness of about 00 to 3000 ° is formed. At the time of exposure, the metal layer 323 becomes a light-shielding region A through which light does not pass, and the other region becomes a transmission region B through which light passes. The integrated circuit pattern is constituted by the light-shielding region B and has, for example, a size five times the actual size (dimension on the wafer).

FIGS. 23A and 23B show an example of an integrated circuit pattern formed on the mask 314. FIG. Circuit pattern P ₁ shown in the diagram (a) is part of a composite pattern after transfer (c), is obtained by extracting the low portion of the transferred sample surface steps. The circuit pattern P shown in FIG.
Reference numeral ₂ denotes a part of the composite pattern (c) after the transfer, which is obtained by extracting a high portion of the surface step of the sample to be transferred. The patterns P ₁ and P ₂ are arranged at predetermined positions of the mask 314 at predetermined intervals. In FIGS. 23 (a) to 23 (d),
331 is a Si single crystal substrate or an epitaxial layer (Si)
332 is a SiO ₂ film, 334a and b
Poly Si, polycide, silicide or Refractory gate electrode or wiring made of metal, coated positive resist film thereon 333, B _A and B _C opening pattern on the main mask 314a, B _B and B _D the opening pattern on the sub-mask 314b, the position of the resist film P _a and P _C corresponding to the low part pattern, the P _B and P _D is the position on the resist film corresponding to the higher portion pattern.

Next, a method of forming the masks 314a and 314b will be briefly described. First, polishing the surface of synthetic quartz glass,
After cleaning, the entire surface on the main surface is, for example, 500 to 500
A Cr film of about 3000 ° is deposited by a sputtering method, and subsequently, an electron beam resist is applied on the entire surface of the Cr film. Next, based on the integrated circuit pattern data previously encoded on a magnetic tape or the like, an integrated circuit pattern is drawn on the electron beam resist by an electron beam exposure method, and then the exposed portion of the electron beam resist is removed by development, and the exposure is performed. Cr
The film is removed by wet etching to create an integrated circuit pattern. The pattern data of the pair of circuit patterns P ₁ and P ₂ may be obtained by enlarging or reducing the data of the light shielding area A or the light transmitting area B of one of the circuit patterns, or inverting the data of one of the circuit patterns and the other of the circuit patterns. It can be automatically created by taking a logical product with the pattern data. Pattern data of, for example, the circuit pattern P ₂ is automatically created by taking the data obtained by enlarging the pattern of the through region B of the circuit pattern P _1, the logical product of the inverted data of the transmission region B of the circuit pattern P ₁ be able to.

In order to transfer the integrated circuit pattern formed on the mask 314 onto the wafer 303 (FIG. 21), first, the wafer 303 coated with a photoresist
Is positioned on the XY table 316 of the exposure apparatus shown in FIG.
The mask 314 (314a and 314b) is positioned in the alignment system. Mask 314, when the light L ₁ of one divided by the half mirror 306 is irradiated onto one of the circuit patterns P ₁ of the pair of the circuit patterns P _1, P _2, the other light L ₂ There is performed as accurately irradiated onto the other circuit pattern P _2. Next, the corner mirror 310 is moved vertically, and the phase difference is adjusted so that the phases of the _two lights L ₁ and L ₂ when recombining are opposite to each other. At this time, considering the coherence length of the light source, the difference between the two optical paths is kept as small as possible. In order to accurately position the mask 314 and adjust the phase difference between the two lights L ₁ and L ₂ , for example, the mask 314
A pair of alignment marks M ₁₁ , M ₁₂ , M ₂₁ , M ₂₂ (collectively Mln) as shown in FIGS. 25A and 25B are used. The mark Mln is formed of openings of the same shape and the same arrangement provided at equal intervals in the shaded area shown by oblique lines. In other words, a distance dimension M ₁₂ and M ₁₁ and M ₂₁ and M ₂₂ are all identical. The mask 314 (314a and 314)
If the positioning of b) and the adjustment of the phase difference between the lights L ₁ and L ₂ are performed properly, the light L ₁ transmitted through the mark M ₁ n and the light L ₂ transmitted through the mark M ₂ n are: Since they interfere with each other and completely disappear, the mark images M ₁ and M ₂ are not formed on the wafer 303. That is, the wafer 3
By identifying the presence or absence of the projection images M ₁ and M _{2 on} the mask 03, it is easy to determine whether or not the positioning of the mask 314 (314a and 314b) and the adjustment of the phase difference between the light L ₁ and L ₂ are accurate. Can be determined.

The alignment of the patterns P ₁ and P ₂ on the mask is performed using the alignment mechanism 309. Next, the phase difference is adjusted according to the surface step of the sample to be irradiated 303 (FIG. 23). This adjustment is performed by computer control (programming) of the piezoelectric control element of the optical path length variable mechanism 311. That is, as shown in FIG. 24, corresponding to the phase difference,
Since the focal position can be shifted, even when the irradiated sample has a surface step, it is possible to focus on both the upper and lower parts.

After the positioning of the mask 314 and the adjustment of the phase difference between the lights L ₁ and L ₂ are performed in this manner, the mask 31
The original image of the integrated circuit pattern formed in No. 4 is, for example, optically reduced to 1/5 and projected onto the wafer 303, and the above operation is repeated while sequentially moving the wafer 303 in a step-like manner.

The data shown in FIG.
By the mask phase shift method, the phase difference is 150
The transparent shifter layer on the mask was formed so as to be at 180 °, 180 °, and 210 °, and was exposed. The experimental conditions were a minimum pattern size of 0.35 μm and an exposure wavelength λ = 365 nm.
(I-line), NA = 0.42, partial coherency σ = 0.3, resist “RI7000P” (manufactured by Hitachi Chemical Co., Ltd.), exposure apparatus: 5: 1 i-line stepper “RA101”
(Manufactured by Hitachi, Ltd.).

The principle of the present invention is not only a pair mask phase shift method by combining two mask patterns as described above, but also an on-mask phase shift method for exposing one mask with a single light beam. It can also be realized by the shift method. In this case, it is necessary to form the thickness of the phase shift film 22 in FIG. 11 so that the phase difference φ becomes a desired value between 150 ° and 210 °.

As shown in the present embodiment, the method of projecting on a plurality of image planes by setting the shift amount to a value other than (2n + 1) π; (n is an integer) in the “phase shift method” The "multi-image plane phase shift method" will be referred to as "multi-mask multi-image plane phase shift method" especially when two masks are used.

The exposure method by simultaneous imaging on a plurality of planes having a step without phase shift shown in the following embodiments and the method of this embodiment are collectively referred to as “multi-image plane projection exposure method”. To

(4) Fourth Embodiment The fourth embodiment relates to a modification of the step-and-repeat type 5: 1 reduction projection exposure apparatus (stepper) applicable to the first to third embodiments and the embodiments described later. is there. This embodiment is effective when the coherence length is relatively short because, for example, exposure light with low coherency is used at the request of a process or the like.

FIG. 26 is a schematic front sectional view of the exposure optical system of the stepper of this embodiment. In the figure, reference numeral 402 denotes a mercury arc lamp, i-line of a mercury xenon arc lamp (365 nm), an excimer laser (249 nm or 3 nm).
08 nm), 403 is a wafer to be exposed, 40
Reference numeral 4 denotes an illumination optical system including a beam expander, a condenser lens, and the like; 405, a mirror such as a cold mirror; 406, a light splitting half mirror for splitting the light L almost equally into two; 407a and 407b, Mirrors for reflecting the split lights L ₁ and L ₂ , respectively, and 408 are light L ₁
408a is a front corner mirror, 408b is a rear corner mirror, 409 is a drive control means of the corner mirror block 408, and 410 is a corner mirror block for optical path length control and alignment with a mask. corner mirror block, 410a is a front portion thereof a mirror for optical path length control for light L _2, 410b rear corner mirror, 414a primarily masks, 414b are sub-masks, 412a and 412b, respectively the light L ₁ , L ₂
411 is a drive control system for the corner mirror 410, and 413 is a combination of L ₁ and L ₂ to make L
415 is a rear projection lens system for forming an image of the synthesized light L 1, and 416 is an XY stage and a wafer suction table for moving the wafer 403 in the XY directions.

Since the operation of the present apparatus is almost the same as that of each of the above-mentioned apparatuses, the description of the operation will not be repeated.

(5) Embodiment 5 In this embodiment, the optical distances from the main mask to the wafer and from the sub-mask to the wafer are substantially the same, and the distance from the main mask to the light source and from the sub-mask to the light source And a step-and-repeat type 5: 1 reduction projection exposure apparatus characterized in that the optical distances are substantially the same. However, it goes without saying that none of these features is necessarily an essential feature of the present invention.

FIGS. 27 and 28 are a sectional view of the i-line exposure apparatus according to the fifth embodiment and additional explanatory views of representative light beams.

In these figures, reference numeral 502 denotes a light source section, which is a filter for extracting only a substantially monochromatic i-line (365 nm) from an ultraviolet lamp such as an ultra-high pressure mercury arc lamp or a xenon mercury lamp and a spectrum issued by the lamp. It consists of groups and mirrors. Reference numeral 504 denotes a condenser lens or a lens system including a group of one or several lenses (synthetic quartz), and forms Koler illumination on the mask. 551 first for tension engaged optical path length matching with half-mirror surface of the prism (synthetic quartz), 506 splits the exposure light beam L, the main exposure light beam L ₁ and for the sub-exposure light beam L ₂ It is a half mirror surface. This half mirror is designed to have substantially the same reflectance and transmittance for the same polarization mode. 507a and 5
Mirror surface to 90 ° deflects the main luminous flux L ₁ is 80a,
507b is a mirror surface for 90 ° deflects the sub beam L _2, 552a and 552b are deflecting prism having a respective deposition mirror surfaces (synthetic quartz). Reference numerals 514a and 514b denote main masks (reticles) and sub-masks (reticles) having patterns to be exposed or transferred, and 561a and 561b denote holders of the respective masks and minute driving means in the Z axis (optical axis direction) and XY axis directions. is there. 540a
And 540b are phase difference setting means for setting the phase difference φ between the two light beams by adjusting the optical path lengths of L ₁ and L _2.
41 is a communication pipe for them. 562a and 562b denote respective front-stage projection lens groups, 554 denotes a second prism (synthetic quartz) for optical path length matching, and 553b denotes L2 by 90 °.
Deflecting prism (synthetic quartz) for deflecting, 549a,
549b and 508b are deflecting mirror surfaces, 51
Reference numeral 3 denotes a combining half mirror surface for combining the light beams L ₁ and L ₂ into L (combined light beam). This half mirror 51
No. 3 has the same characteristics as the half mirror 506 for division. 515, a rear projection lens group for exposure, 565, a rear projection lens group for reference, 566, a light detecting means provided on the image plane of the projection lens group for reference, 503, a wafer to be exposed, and 576, vacuum suction of the wafer. Chuck and a θ rotation (rotation axis around a vertical axis passing through the center of the wafer) stage to secure the flatness of the wafer
A moving stage in the axial (vertical axis) direction, 578 is a horizontality adjusting means composed of three Z-axis driving means, 579 is an X stage, and 580 is a Y stage.

FIG. 29 shows the phase difference setting means 54 of the stepper.
It is principal part sectional drawing of 0a. In the same figure, 542a and 543a are synthetic quartz glass plates, 541a is a distance adjusting means for them, 544a is a metal bellows, 544a is a pressure reservoir (Reservoir), 546a is a communicating pipe made of an austenitic stainless steel pipe, and 545a is a communicating pipe made of austenitic stainless steel pipe. An optical path length control chamber in which a single gas or a mixed gas having a refractive index different from that of the atmosphere gas of the chamber in which the stepper is disposed or the main atmosphere gas of the exposure light beam passage is maintained at a constant pressure by the action of the pressure reservoir 547a. . The optical path length control chamber 545a can be in a vacuum state by using 547a as a vacuum pump. In the case of a vacuum, it is not necessary to consider the temperature rise of the gas in the optical path length control chamber.

FIG. 30 is a top view of the wafer stage portion of the stepper. In the figure, reference numeral 503 denotes a wafer to be exposed, 576 denotes a wafer / chuck / θ stage, 577 denotes a Z stage, 578a to c denote respective Z-axis direction driving elements constituting elements of the horizontality adjusting means 578, 579 denotes an X table,
80 is a Y table.

Next, the exposure operation of the present stepper will be described.
First, the inclinations of the main mask 514a and the sub-mask 514b are adjusted so that the optical path length between the point on each mask corresponding to the exposure area and the light source is as equal as possible. Furthermore, the optical path length between each mask and each corresponding point on the wafer 503 is adjusted (tilt of the wafer) so as to be as identical as possible.
Next, as described in the third embodiment, using the alignment, the mark M, the focusing, the mask alignment in the XY plane, and the phase difference φ = π (after that, if necessary, π < φ <
The phase difference (a relative phase difference may be used as long as interference occurs) φ is readjusted in the range of π to correspond to the step. ), And then perform exposure at the same site.

The adjustment of the phase difference is performed by changing the thickness of the optical path length control chamber 540a or 540b as shown in FIG. That is, the distance between the quartz plates 542a and 542b is moved in parallel by one of the quartz plates.

Further, the inclination of each mask and wafer can be adjusted by:
Three inclination adjusting means 578a to 578c as shown in FIG. 30 (in the case of a wafer, the mask is also operated by substantially the same mechanism)
Is executed by moving in the Z-axis direction.

The rear projection lens group 515 (FIG. 27) itself is configured so as to be “telecentric” on both sides, that is, such that the chief ray is parallel to the optical axis on both sides of the same lens group. I have. Therefore, as in the case of an infinite cylinder length correction system in a microscope, a change in overall imaging characteristics when various optical elements are inserted between the front projection lens group 562a or 562b and the rear projection lens group 515 is minimized. be able to. Furthermore, since the front projection lens groups 562a and 562b are located near the masks 514a and 514, separately from the rear projection lens group 515, it is easy to secure an optimum object-side numerical aperture.

(6) Embodiment 6 In this embodiment, the main mask and the sub-mask are separately exposed, and they are combined with a phase difference of (2n + 1) π.
A mask pattern used in the invention for exposing a wafer with the combined light will be described. In the following description, the main pattern and the sub-pattern corresponding to the same pattern (on the wafer) on the sub-mask and the main mask are projected and shown on the same plane for convenience. The dimensions given to the pattern are shown in terms of dimensions on the wafer in the case of 5: 1 reduction projection. Regarding the sub-pattern, the boundary between the shielding area and the opening area is indicated by a broken line. Regarding the opening area of the sub-pattern, the corresponding portion is indicated by dispersed points.

FIG. 31 is applicable to the isolated Al line of the embodiment 6A (other metal wiring lines, insulating film strips, strip-shaped openings, poly-Si wirings or gate lines, polycide wirings or gate lines, etc. The description is limited to representative ones of them.) Is a pattern of a main mask and a sub-mask in the case of exposing by a negative process. (If a linear opening is to be formed, it is necessary to use a positive resist process with this mask pattern.) In the figure, reference numeral 601a denotes an opening on the main mask corresponding to the Al line, 604d and 605d is a light-shielding portion of the same main mask made of a chrome film, 602b and 603b.
Is a sub-pattern on the sub-mask (shifter pattern or compensation pattern, especially when the phase is reversed, referred to as phase reversal or simply reversed pattern or reversed slit), dimension A is 0.3 to 0.4 μm, dimension A B is about 0.2 μm, dimension E
Is about 0.1 μm.

FIG. 32 shows a main mask and a sub mask pattern of the embodiment B. This example corresponds to a contact hole or a through hole or other isolated holes, and a positive resist process is used. (On the other hand, in the case of an isolated film pattern, a negative resist process is used.)
In the figure, reference numeral 611a denotes a hole (opening) on the main mask.
612d is a light-shielding portion on the same main mask,
Reference numerals 613b, 614b, 615b, and 616b denote reverse slit groups on the sub-mask. Regarding the dimensions, the same symbols are substantially the same as those in the previous example.

FIG. 33 shows a mask pattern corresponding to the isolated openings of the main mask and the sub-mask of the embodiment 6C which is a modification of the embodiment 6B. In FIG.
Reference numerals C, 614C, 615C, and 616C denote auxiliary opening patterns (corner enhancement patterns or enhancers) on the main mask for preventing the openings from being rounded. is there. The dimensions of the enhancer are about 0.1 μm square. According to the embodiment 6B, this method is effective for preventing the corner portion from being abnormally rounded.

FIG. 34 shows a main mask and a sub-mask pattern when an "L" -shaped opening pattern whose width is equal to the minimum line width in the exposure process is processed by a positive resist process, as in the previous examples. It is. In the figure, reference numeral 621a denotes an opening on the main mask, and 622d denotes a shielding portion on the main mask (this portion also becomes a part of the shielding portion with respect to the sub-mask as before, that is, a broken line. Except for the reversing shifter portion indicated by, all correspond to the shielding portion or the shielding portion.), 623b, 624b, 625b, 62
Reference numerals 6b, 627b, and 628b denote shifter region openings on the sub-mask, respectively. The dimensions are indicated by the same symbols as in FIG. (These symbols indicate the same dimensions unless otherwise specified.) Note that when a negative resist process is used, this pattern is not changed to the “L” of Al as it is.
It becomes an isolated film pattern such as a character pattern.

FIG. 35 shows a modification 6E of the embodiment 6D. 34, reference numeral 621a denotes an opening pattern on the main mask corresponding to 621a in FIG. 34, and reference numeral 621d denotes an auxiliary light shielding pattern (FIG. 34) for preventing excessive expansion inside the corner of the "L" -shaped opening on the main mask. Corner reduction pattern or reducer), the size of which is the same as that of the enhancer. 623c, 624c, 6
Reference numerals 25c, 626c and 627c denote opening patterns corresponding to enhancers provided on the main mask in order to prevent excessive reduction of corners, and 622d denotes a shielding portion on the main mask, 623b, 624b, 625b, 626b, 627.
b and 628b are shifter patterns (inversion openings), respectively.

FIG. 36 shows a main mask and a sub-mask pattern corresponding to the negative resist process for the isolated and bent Al wiring pattern in the embodiment 6F. In the figure, 631a
Are openings on the main mask corresponding to the Al wiring, 638d and 639d are shielding portions on the main mask, 633b and 634
b, 635b, and 636b are shifters running along the Al wiring. Each dimension is basically the same as the others. When this pattern is applied to a positive resist process, it can be applied to the formation of a band-shaped opening.

FIG. 37 shows a main mask and a sub-mask pattern (corresponding to a negative process such as an isolated Al bending pattern) of the embodiment 6G. This example is a modification of the above 6F. In the figure, 631c is an opening pattern acting as an enhancer, 631d is a shielding pattern acting as a reducer, these are both provided on the main mask, and the dimensions are the same as the equivalent pattern in FIG. The other points are exactly the same as those in the embodiment 6F.

FIG. 38 shows a main mask and a sub mask pattern for the line and space pattern of the embodiment 6H. In this case, a negative resist process is used. In the figure, 641a, 642a and 643a
Is a band-shaped opening / pattern portion on the main mask corresponding to the Al line pattern; 641b, 642b and 643b are band-shaped shifter opening / pattern portions (or complementary line pattern) on the sub-mask corresponding to the Al line pattern portion. ), 645d, 646d, 647d, and 6
48d is a shielding part on the main mask. The dimensions are 0.3 μm for both lines and spaces.

[0149] In the case of positive, it is necessary to replace the shielding portion between the opening on the main mask and the opening on the sub-mask and the opening adjacent thereto in the figure. . That is, it is necessary to make the opening of the main or sub mask at a portion corresponding to the space. This is the same when a well-known band-shaped opening is formed.

Embodiment 6 The mask patterns 6A to 6H are as follows:
The multi-mask method as described above (Examples 1 to
5) Not only the on-mask phase shift (shifter having an inverted transparent film with relative position φ = π on one mask)
(Phase shift exposure method using one mask having both a pattern and a main pattern of φ = ο). In this case, the pattern shown in FIGS.
What is necessary is just to make a mask as what is on one mask.

(7) Embodiment 7 Here, a wafer processing and an exposure process used for carrying out the present invention will be described.

FIG. 39 is a top view of the wafer showing the flow of exposure in 5: 1 reduction step-and-repeat projection exposure.
In the figure, reference numeral 703 denotes a wafer to be exposed (for example, 8
Inch single crystal Si wafer), 702 is an orientation flat of the wafer, and 731 and 732 are exposure areas which have already been exposed (areas irradiated with light by one exposure operation, also called unit exposure areas), 73, respectively.
Reference numerals 3 to 736 denote each unit exposure area to be exposed, and this area covers almost the entire area of the upper surface of the wafer 703. Exposure is performed in the numerical order shown here.

FIG. 40 shows a unit exposure area 7 in the case of a memory IC.
33, each chip area 721, 722 and inter-chip area 7
FIG. 23 is a plan view showing the relationship with 23.

FIGS. 41-E and 44-H are schematic sectional views for explaining the flow of the exposure process and the wafer process using the positive and negative resists of the present invention, respectively.
In FIGS. 41 and F, for the sake of simplicity, the ray diagram and the mask are on-mask phase shift (phase shift method using one mask. However, only the main pattern is shown in the mask, and the shifter is omitted. In the case of a multi-mask, only two light paths are provided in the middle and only one light path is combined on the wafer surface.
It is exactly the same as shown here.

In FIGS. 41 to 41E, reference numeral 714 denotes a positive mask, 745 denotes an opening of the mask 714, 714 denotes a reduction projection lens system shown in another embodiment, and 703 denotes a stepper on a wafer stage of a stepper. The wafer to be processed vacuum-sucked on the semiconductor wafer 741 is the first oxide film on the main surface of the semiconductor wafer.
42 is an Al wiring pattern formed thereon, 743 is a second oxide film formed on the entire surface thereof, and 744 is a positive resist film (resist applied on the entire surface thereof by a spinner (0.6 μm)). About Example 16).

In FIG. 42, reference numeral 746 denotes a resist film 744.
Is an opening formed in a predetermined portion.

In FIG. 43, reference numeral 747 denotes a resist film 744.
Is a through hole of the second oxide film formed using the mask as a mask.

44 to H, reference numeral 714 denotes a negative mask, reference numeral 755 denotes an opening or a light-transmitting pattern, reference numeral 715 denotes the same reduction projection lens system as above, and reference numeral 703 denotes a stepper as in the previous case. Semiconductor wafer, 74
1 is an oxide film formed on the main surface, 742 is an Al film deposited on the entire surface by sputtering, 75
Reference numeral 4 denotes a negative photoresist film having a thickness of about 0.6 μm formed (coated) thereon.

In FIG. 45, reference numeral 754x denotes a patterned resist film.

In FIG. 46, reference numeral 742x denotes a resist film 75.
This is an Al wiring pattern patterned using 4x as a mask.

FIGS. 48 to 54 are cross-sectional views showing a manufacturing process flow of a CMOS-static RAM (SRAM) using a twin well system, and FIG. 55 is a layout diagram on a chip thereof. Hereinafter, description will be made sequentially.

FIG. 48 shows n by the twin well process.
And a p-well formation process. In FIG.
Reference numeral 3 denotes an n ⁻ -type Si single crystal wafer (substrate), 760 n denotes an n-type well region, and 760 p denotes a p-type well region.

FIG. 49 shows a subsequent gate forming process and a process of forming the source / drain of each FET by ion implantation with a self-aligned line using the formed gate as a mask. In the figure, reference numerals 761a to 761c denote LOs.
COS oxide film, 762 p and n are gate oxide films, 763
p and n are polysilicon gate electrodes (or polycides), respectively, and 764 p and n are p-type and n-type high-concentration source / drain regions, respectively.

FIG. 50 shows an interlayer PSG film forming process and a second process.
4 shows a layer poly-Si wiring and a high resistance forming process. In the figure, reference numeral 765 denotes an interlayer PSG film, 766 denotes a second-layer poly-Si wiring, and 766r denotes a poly-Si high resistance serving as a load resistance of the SRAM memory cell.

FIG. 51 shows a SOG planarization process and a contact hole or through hole formation process. In the same figure, 767 is an SOG film, 768a, b,
d and e are contact holes with the Si substrate, 768
c is a through hole between the second layer poly-Si wiring and the upper layer.

FIG. 52 shows a first layer Al wiring forming process. In FIG. 7, reference numerals 769a to 769 denote first layer Al wirings.

FIG. 53 shows a process of forming an interlayer insulating film on a first layer Al wiring and a process of forming a second layer Al wiring. In the figure, reference numeral 770 denotes an interlayer insulating film on the first-layer Al wiring;
Reference numerals 71a and 71b denote second layer Al wirings connected to lower Al wirings and the like via through holes.

FIG. 54 shows a process of forming a final passivation film on the second layer Al wiring. In the figure,
772 is a final passivation film.

FIG. 55 is a top view showing a layout of the SRAM in a chip unit. In the figure, 721 is a chip, 722 is a memory cell mat, and 723 is an I / O.
It is a peripheral circuit including a circuit, an address decoder, a read / write circuit, and the like.

FIG. 47 shows a process related to photolithography in the above-mentioned SRAM manufacturing process, that is, an exposure process extracted and shown as a flow.
It is a flowchart. In the figure, an n-well photo process 7P1 is a process of forming a resist pattern on a Si ₃ N ₄ film (on a substrate) so as to cover a portion other than a portion to be an n-well, and a field photo process 7P2 is Si ₃ so as to cover the active region of the channel and the N channel.
In this step, a resist film is deposited on the N ₄ film and patterned to pattern the N ₄ film. p-well
The photo step 7P3 is a step of patterning a resist film covering the n-well to form a p-well channel stopper region, and the gate photo step 7P4 is deposited on the entire surface to pattern the gate electrodes 763p and n. This is a step of patterning a resist film on the poly-Si or polycide layer. The details of the process up to this point will be described in more detail with reference to FIGS. The n-channel photo step 7P5 is a step of patterning a resist film on the p-channel side for ion-implanting n-type impurities using the gate 763n as a mask on the n-channel side, and the p-channel photo step 7P6 is reversed on the p-channel side. A step of patterning a resist film on the n-channel side in order to implant a p-type impurity by using the gate 763p as a mask; a poly-Si photo step 7P7 includes a second layer wiring 766 or a high resistance 766r
The step of forming a resist pattern on the poly-Si film deposited on the entire surface to pattern the second-layer poly-Si film to be (FIG. 50), the R photo step 7P8 is a poly-Si high resistance 766r (FIG. 50) A step of patterning a resist film serving as a mask by a negative process in order to implant impurity ions into other portions while the upper part is covered with a resist film, and a contact photo step 7P9 includes a substrate, a source / drain region, and a first layer. Positive process of forming a resist pattern for forming contact holes 768a to 768e (FIG. 51) for making contact between a poly-Si layer, a second-layer poly-Si layer, etc. and a first-layer Al wiring (Al-I). Patterning process according to the above, Al-I photo process 7P10
(FIG. 52) is a resist patterning process for patterning Al-I, and a through-hole photo step 7P11 is for opening a through-hole for making a connection between Al-I and the second-layer Al wiring. Step of forming a resist pattern, Al-II photo step 7P12 (FIG. 5)
3) resist patterning step for Al-II patterning, bonding pad photo step 7P
Reference numeral 13 denotes a step of forming a resist film on the final passivation film other than the pads in order to form an opening of about 100 μm square corresponding to the bonding pad in the final passivation film 772.

Of these exposure processes, the n-well photo 7P1, the n-channel photo 7P5, the p-channel photo 7P6, and the bonding pad photo 7P13 have relatively large minimum dimensions. Therefore, it is generally not necessary to use the phase shift method. Absent.

On the other hand, with respect to the other exposure processes in FIG. 47, the “phase inversion shift method” of each embodiment of the present invention is used.
It is effective to apply “Phase inversion shift method” is a concern that includes both “multi-mask phase shift method” and “on-mask phase shift method”.

When there is a considerable step between the memory mat 722 and each plane of the peripheral circuit portion in FIG. 55, it is effective to use any one of the “multi-image plane projection exposure method” of the present invention. It is.

(8) Eighth Embodiment FIGS. 56 to 70 show a process flow of a 16 MDRAM according to the present invention. The basic design rule is 0.6 μm, stack type memory cell, LOCOS oxide film isolation, and the basic features are twin-well CMOS configuration, WSi ₂ polycide bit line, and two-layer Al wiring using WSi ₂ / TiN tangent. It is. In the following processes, a photoresist removing step, a pre-processing (such as cleaning) and a post-processing step, an inspection step, a back surface processing step, and the like are omitted.

FIG. 56 shows n by ion implantation of phosphorus (P).
^- it is a sectional view showing a well forming process. In the figure, reference numeral 803 denotes a P-type Si single crystal wafer having a resistivity of 10 Ω · cm (boron is a dopant) and a main surface of a mirror surface (100). 860 is a thin thermal oxide film, 861 is an Si ₃ N ₄ film as an oxygen-resistant mask, and 862 is a patterned resist layer which acts as a mask for ion implantation. 863 is an n-well region formed by P (phosphorus) introduced by implantation.

FIG. 57 is a graph showing p by ion implantation of boron (B).
^- it is a sectional view showing a well forming process. In the figure, 865 is a thick silicon oxide film (SiO ₂ ) formed by thermal oxidation, 864a is a p-well region of a peripheral circuit, 8
64b is a p-well region of the memory array section.

FIG. 58 is a view showing B of the p ⁺ type channel stopper region.
It is sectional drawing which shows the formation process which implants (boron).
In the same figure, 866a to 866d are p ⁺ channel stopper regions, 867a to 867c are Si ₃ N ₄ films as an oxygen-resistant and ion implantation mask, 868 is a photoresist film as an ion implantation mask, and 869a and b are gates. It is an oxide film.

FIG. 59 is a sectional view showing a state in which a LOCOS oxide film has been formed. Referring to FIG.
This is a COS oxide film.

FIG. 60 is a cross-sectional view showing a process of forming a phosphorus-attached Si gate and an n-channel source / drain. In the figure, reference numerals 871a, 871c and 871d denote gate electrodes (P-doped poly S) of an n-channel FET.
i) and 871b are p-channel FET gate electrodes (P-doped polysilicon); 872a to 872e are P (phosphorus) ion implantation regions corresponding to n-channel sources or drains; It is a resist film.

FIG. 61 shows a process of forming a high-concentration n-channel source / drain region performed after formation of a side wall. In the figure, 872x and y are p-channel source / drain regions, 874 is a photoresist film as an ion implantation resistant mask, and 875a to 875d are side electrodes.
This is a wall insulating film (SiO ₂ ).

FIG. 62 is a cross-sectional view showing an interlayer SiO 2 deposition process and a polycide bit line forming process. In the figure, 877a is a poly-Si film (addition of phosphorus), and 877b is a silicide (WSi ₂ ) film, which forms a bit line. 877c is SiO by CVD
₂ and 876 are CVD SiO ₂ films formed (deposited) after As (arsenic) implantation.

FIG. 63 is a cross-sectional view showing a process for forming a poly-Si electrode to be an individual electrode of a capacitor of a memory cell. In the figure, reference numeral 878 denotes SiO ₂ films 876 and 87.
SiO2 film formed integrally with 7c, 879
“a” and “b” are poly-Si deposited films that become individual electrodes of the capacitor of the memory cell.

FIG. 64 is a cross-sectional view showing a process for forming a capacitor plate serving as the other common electrode of the capacitor of the memory cell. In the figure, reference numeral 880 denotes an Si ₃ N ₄ deposited film serving as a dielectric of the capacitor, and 881 denotes an additional poly-Si deposited film serving as a plate electrode.

FIG. 65 is a sectional view showing a process for forming a high concentration source / drain of a p-channel FET by implanting B ⁺ (boron). In the figure, 882a and 882b are resist films as ion implantation resistant masks.

FIG. 66 is a sectional view showing a reflow process of the interlayer insulating film. In the same figure, 883a-f are BP
Reflow films made of SG (Boro-Phospho Silicate Glass) films, and reference numerals 884a to 884 denote contact holes formed there.

FIG. 67 is a sectional view showing a silicide (WSi ₂ / TiN) wiring forming process. In FIG.
Reference numerals 85a to 85c denote silicide wiring layers composed of both deposited films of a lower TiN film and an upper tungsten silicide (WSi ₂ ).

FIG. 68 shows an interlayer PSG (Phospho-Silicate-Gla).
ss) Sectional view showing the deposition and through-hole formation process. In the figure, 886a-c are PSG / SOG
/ PSG is an interlayer insulating film composed of three deposited films.

FIG. 69 is a cross-sectional view showing a forming process of the first layer Al wiring. In the figure, reference numerals 887a to 887d denote a lower TiN buffer layer and an upper Al (Al 99%, Sil).
%) Wiring layer (Al-I).

FIG. 70 shows an upper interlayer PSG film and a second layer Al
FIG. 4 is a cross-sectional view illustrating a wiring (Al-II) forming process. In the figure, 888 is the same PSG as 886a to 886c.
This is an interlayer PSG film composed of three deposited films of / SOG / PSG. 889a and 889b are second layer Al (Al-II) wiring layers.

FIG. 71 is a circuit layout diagram of the DRAM chip. In the figure, 821 is a chip area,
Reference numerals 822a and 822b denote a memory array or a memory cell mat unit, and 823 denotes a peripheral circuit unit (including a bonding pad).

FIG. 72 is a top view showing the cell plane structure of the memory array of the DRAM substantially for one period of the translation symmetry. However, the upper wiring structure is omitted for simplicity. In the figure, 871c is a word line, 872
d is an n-type source or drain region, 877a and b are bit lines, 879a is a storage node (capacitance), 88
1 is a plate.

Next, the DRAM will be described with reference to FIGS.
The process flow of the preceding step (wafer process) will be described.

As described above, the thickness of about 0.7 mm to 1.0 mm
A type Si single crystal wafer is prepared, and a thin thermal oxide film for a buffer is formed on the entire surface of the (100) plane. A Si ₃ N ₄ film is deposited on the entire surface by CVD with a sufficient thickness as an oxygen-resistant mask. Thereafter, spin coating is performed on the entire main surface of the wafer, and the resist is patterned and the underlying Si ₃ N _{4 is formed} by the exposure process (exposure process 1) of the present invention.
The film is etched. Next, as shown in FIG. 56, using the resist film 862 or the like as a mask, phosphorus is implanted into a portion to be an n-well region. Next, a resist film 862
Is removed, and a thermal oxide film is selectively formed on the n-well 863 using the Si ₃ N ₄ film 861 as an oxygen-resistant mask. Next, the entire surface of the Si ₃ N ₄ film 861 is removed, and as shown in FIG.
Using the oxide film 865 on the well as a mask for ion implantation, p
Drill boron (B ⁺ ) into the wells. Next, extension and diffusion (N ₂ annealing) and activation of each well are performed. Further, after the oxide films 860 and 865 on the substrate are entirely removed, thin thermal oxide films 869a and 869a and S
An i ₃ N ₄ film is formed on the entire surface. Next, as shown in FIG. 58,
Patterning is performed by the exposure process (exposure process 2) of the present invention so that the Si3N4 film remains only in the active region, thereby obtaining oxygen-resistant masks 867a to 867c. After that, the resist is removed. Further, a resist film is applied on the entire surface and exposed by any of the methods of the present invention (exposure process 3).
Then, the entire upper surface of the n-well is covered with a resist 868. In this state, boron (B ⁺ ) is ion-implanted into regions 866a to 866d to be channel stoppers. Next, the resist film 86
8 is entirely removed, and using the Si ₃ N ₄ films 867a to 867c as masks, a field oxide film 870a is selectively formed as shown in FIG.
~ E are formed by thermal oxidation. Next, the Si ₃ N ₄ film 867a
To c is entirely removed, and a thin oxide film 869 on the active region is further removed.
After removing a and b, new gate oxide films 869 a and 869 b are formed again by thermal oxidation (FIG. 59).

Further, a phosphorus-added poly-Si film is formed on the entire surface by low-pressure CVD, a resist is applied, and the resist film is patterned (exposure process 4) by any of the methods of the present invention. As a mask,
The gate electrodes 871a-87d are patterned (FIG. 60).
Next, the n-well is covered with a resist film 873 (exposure process 5), and self-aligned with each of the gate electrodes, a region 873 to be a source / drain of an n-channel FET.
Phosphorus (P) ions are implanted into a to e by ion implantation. After that, the resist 871b is removed. Further, the p-well region is similarly covered with a resist film (exposure process
6) Then, similarly to the above, boron (B) is ion-implanted into the regions 872x and y to be the source or the drain of the p-channel FET (FIG. 61). Further, side walls 875a to 875d are formed in a self-aligned manner around the gates 871a to 871d by a known side wall process. Further, as shown in FIG.
(Exposure process 7), and arsenic (As) is ion-implanted using them as a mask to form an LDD (Lightly
An n-type region forming a high-concentration region of Doped Drain is formed. After that, the resist 874 is removed.

Further, as shown in FIG. 62, an SiO ₂ film 876 is deposited on the entire surface by low pressure CVD. Next, a resist pattern with a wide opening (exposure process
8) A contact hole to be a contact between the bit line of the memory cell and the substrate is formed in a semi-self-aligned manner. Further, poly Si and WSi ₂ low pressure CVD SiO ₂ are sequentially deposited on the entire surface, a photoresist is applied (exposure process 9), and the bit lines 877a and 877b are patterned. After forming a bit line and removing the resist, an SiO ₂ film is deposited on the entire surface by low pressure CVD, and the side surface of the bit line is covered with an insulating film 878 (FIG. 63). Next, a contact hole between the storage node electrode of the memory cell and the substrate is formed by applying a photoresist (exposure process 10) and etching the SiO ₂ film 878 and the underlying oxide film. Next, a poly-Si film to be a storage node electrode is deposited on the entire surface by low pressure CVD. Further, phosphorus (P) is ion-implanted into the entire surface of the poly-Si film, activation annealing (N ₂ annealing) is performed, and a photoresist is applied (exposure process 11), and the storage node 879a is formed as shown in FIG. And b are patterned. After that, the resist is removed.

Further, as shown in FIG. 64, a Si ₃ N ₄ film to be a capacitor insulating film is deposited by low pressure CVD.
Next, the Si ₃ N ₄ is oxidized to a partial thickness. Further, a phosphorus-added poly-Si film serving as a capacitor plate is deposited thereon. Next, a resist film is applied on these films, and unnecessary poly-Si and Si ₃ N ₄ films are removed by using a patterned (exposure process · 12) mask, and the capacitor insulating film 880 and the plate 881 are removed.
To form After that, the resist is removed.

Further, as shown in FIG.
The channel portion is covered (exposure process 13), and the SiO ₂ film 878 in the p-channel portion is removed. Next, after removing the previous resist, a resist film 882 is again formed on the n-channel portion.
A and b are deposited (exposure process 14), and using the mask as a mask, boron (B ⁺ ) is ion-implanted into a region to be a high-concentration source / drain region of the LDD structure of the p-channel FET. Thereafter, the resist film is entirely removed, and N ₂ annealing for activation is performed.

Further, as shown in FIG.
_Two films and a BPSG film are deposited and flattened by reflow. Next, contact holes 884a to 884e are formed by applying a photoresist and performing patterning (exposure process 15). Next, the upper surface of the p-channel portion is covered with a photoresist (exposure process 16), and an n ⁺ -type n ⁺ contact region is formed below the n-type source / drain contacts by ion implantation (phosphorus). . After removing the resist, the n-channel portion is covered with a photoresist (exposure process 17).
A p ⁺ -type p ⁺ contact region is formed below the p-type source / drain contact by ion implantation (B). After removing the resist film, the ion implantation layer is activated and B
Performing N ₂ anneal for reflow of the PSG film 883A～f.

Further, as shown in FIG. 67, an underlying TiN buffer layer and a wiring layer WSi ₂ (tungsten silicide) are formed on the entire surface.
Is applied by CVD, and a photoresist film is applied thereon and patterned into a desired shape (exposure process 1).
8) Then, using the mask as a mask, the silicide wiring 885a
To c are formed by dry etching. After that, the unnecessary resist film is removed. Perform N ₂ annealing.

Further, as shown in FIG. 68, PSG / SOG / PS
An interlayer PSG film having a structure of G is deposited and formed, and dry etching is performed by a positive resist process (exposure process 19) in a state where a portion other than a portion to be a through hole is covered with a resist by dry etching. . After that, the resist film is removed.

Further, as shown in FIG. 69, an underlying TiN film and an Al wiring layer (Al 99% by weight, Sil
% By weight), and a negative process (exposure process 20) is performed to leave the resist only on the portion to become the Al wiring, and the Al-I wirings 887a to 887d are pattern-formed by dry etching. After that, the resist film is removed.

Further, as shown in FIG. 80, plasma SiO ₂ /
An interlayer insulating film 888 composed of three layers of SOG (Spin-On-Glass) / plasma SiO ₂ is deposited, and a portion other than a portion to be a through-hole thereon is subjected to a positive process (exposure process.
21) A through hole is formed by dry etching in a state covered with the resist. After that, the resist is removed. Next, an Al wiring layer (A
199% Sil%) is applied on the entire surface, and a resist film is applied on only the portions to be wiring thereon by a negative process (exposure process 22). By performing dry etching using this resist film as a mask,
The Al-II wirings 889a and 889b are formed.

Furthermore, a normal pressure PSG film (final passivation) is deposited, and a positive process (exposure process
23) a resist film is applied. Using this resist film as a mask, an opening for a bonding pad is formed by chemical etching.

Of the above exposure processes, the exposure processes requiring strictly dimensional conditions.
For 1, 15, and 18 to 22, the phase shift method of each embodiment of the present invention is effective. Among them, as shown in FIG. 71, the memory array units 822a and 822b and the peripheral circuit 8
When there is a large step between the planes to which 23 belongs, it is effective to utilize the multi-image plane projection exposure method shown in each embodiment of the present invention. In the process including a large number of periodic wirings such as the exposure processes 9, 18, 20, and 22, masks for the mutual opening (FIG. 38 of the sixth embodiment and FIGS. 84 to 89 of the fifteenth embodiment) are used. The phase shift method (phase inversion shift method) used is effective.

(9) Embodiment 9 The concept of creating a mask layout and the theoretical background of the present invention will be described.

FIG. 73 shows the amplitude intensity u (broken line) and the same energy intensity I in the case of light from two apertures separated by ε (equivalent distance on the wafer) on a mask without a normal phase shift.
(Solid line) is plotted with respect to the coordinate X on the main surface on the wafer. (Numerical calculation value) Thus, for example, when 5: 1 reduction projection is performed, the phase difference φ ₂ −
When φ ₁ = Δφ is equal to or equal to 0, constructive interference occurs, as indicated by the solid line I, and the peaks u ₁ and u ₂ are not resolved.

The problem of the resolution of such a minute proximity object by the projection system is given by Rayleigh as follows. That is, assuming that the distance between two adjacent points (on the wafer) is δ:

[0208]

(Equation 3)

Here, λ is the exposure wavelength, and NA ₁ is the NA (numerical aperture) of the image-side projection system.

For example, considering the case of the i-line, λ = 0.
365 μm, for example, NA = 0.4, and the resolution limit δ is about 0.56 μm. Therefore, as shown in FIG. 73, when trying to project a pattern having the same size as the wavelength (for example, 200% to 50% of λ), a problem occurs in that two lines cannot be separated because they are united.

On the other hand, when a phase difference π (or its equivalent) is given to a light beam between two adjacent openings as shown in FIG. 74 (phase inversion shift method), a sharp dent appears in the energy intensity I near the origin, As a result, the peak is resolved into two.

FIG. 75 is a schematic diagram for explaining the principle of the multi-image plane phase shift method for setting the phase difference Δφ between the main aperture and the sub aperture to a value other than π or an equivalent value as in the third embodiment. is there. This greatly simplifies the optical action of the reduction projection system. 23, reference numeral 991 denotes an exposure light beam (wavelength λ), reference numeral 914 denotes a mask, and reference numeral 921a denotes a main opening (for example, FIG. 23).
B _A ) and 921b are sub-openings (for example, FIG. 23B).
B _B ), d is the distance between the apertures (converted on the wafer),
1 is the distance between the mask and the image plane, and l ₁ and l ₂ are the optical path lengths from each opening to the screen 903 (image plane or wafer).
The light intensity I (x) on the screen is determined as follows.

Assuming that the electric field strengths u ₁ and u ₂ by the openings are wave number k and phases φ ₁ and φ ₂ ,

[0214]

U ₁ = A _exp [−i (kl ₁ −φ ₂ )] (9.2)

[0215]

U ₂ = B _exp [−i (kl ₂ −φ ₂ )] (9.3) For synthetic light,

[0216]

(Equation 6)

As a result, the change of l is Δl, Δφ = φ
₂ −φ ₁

[0218]

(Equation 7)

It can be seen that changing Δφ changes the image plane. However, this model is a rough model, and needs to be corrected and confirmed by numerical calculations and experiments.

(10) Embodiment 10 This embodiment describes an ultraviolet light source for projection exposure applied to each exposure process of the present invention and its periphery.

FIG. 76 is a table summarizing various characteristics of the available exposure illumination system. In the diagram, Partial Coherence is generally denoted by the Greek letter “σ”, and its definition is

[0222]

(Equation 8)

Is as follows. Here, NAc is the numerical aperture on the mask side of the illumination system condenser lens, and NAo is the numerical aperture on the mask side of the exposure projection lens system. Here, NAo = 0.4. The ultraviolet light source used in the exposure of the present invention may be a deep UV spectrum (far ultraviolet) between 0.2 and 0.3 μm of an Xe-Hg light source, excimer laser emission around 0.2 μm, There are Hg arc emission other than those shown in the figure.

The lighting used in the present invention has a so-called Kohler structure. However, illumination with other configurations is also possible.

FIG. 19A shows a specific example of the exposure illumination system.
Will be described separately.

(11) Embodiment 11 Here, a modified example (corresponding to Embodiment 5) of the 5: 1 reduction projection exposure apparatus used for exposure according to the present invention will be described. In this example, in the illumination system and the exposure projection system, the lens operation for operating the two divided light beams is performed only by the same lens system. Therefore, a pair of lens systems is used for each of the left and right light beams. There is an advantage that it is not necessary to consider a difference in aberration of the lens system which may be a problem in such a case. This exposure system is a double-sided telecentric system configured to be telecentric on the mask side (object side) and the wafer side (image side).

FIG. 77 is a simplified schematic sectional view of the illumination system and the exposure projection system of the stepper of this embodiment. In the figure, reference numeral 1102 denotes a light source that emits i-rays of mercury, L denotes an initial luminous flux, and 1104 denotes a condenser that constitutes Koehler illumination.
An illumination optical lens system such as a lens, L ₁ and L ₂ are a main beam and a sub beam separated by a half mirror with the same uniform intensity, 1114 a is a main mask, 1114 b is a sub mask, 1
140a is an optical path length control room (for the main light beam), 11
Reference numeral 40b denotes an optical path length control chamber for the sub light beam, L denotes a combined light beam, 1115 denotes a projection lens system, and 1103 denotes a wafer to be exposed.

In this method, since a lens system in which various aberrations are likely to be different is common to both light beams L ₁ and L ₂ ,
The area that can be simultaneously exposed can be increased. Also, 1
The phase shift can be adjusted to a desired value over the entire field that can be exposed at one time, so that a high resolution can be obtained.

Note that the present embodiment is not limited to the one shown in FIG. 77. For example, two independent light source systems can be used. Also in this case, the main lens system 11 for the main and sub-beams in the lower half (after the mask) of the optical system.
Since 15 is common, it is possible to minimize the adverse effect on the transfer characteristics of the pattern on each pair of masks due to the difference in aberration between the two optical systems.

Further, the present apparatus is applicable to all exposure methods for simultaneously transferring patterns on two masks onto one wafer.

The optical structure simplified in FIG. 77 is almost the same as in FIGS. 27 and 28. The different parts correspond to the front-stage lens groups 562a and 562b, but are not present in the present embodiment, but only in the presence of a double-sided telecentric projection lens system 1115 provided at a position equivalent to 515 in FIG.

(12) Embodiment 12 Here, a mask defect inspection apparatus for inspecting a mask according to the present invention will be described.

FIG. 78 is a simplified schematic sectional view of a mask inspection apparatus. In the same figure, reference numeral 1252 denotes an e-line (546n
monochromatic light sources m), L initial inspection light beam, L ₁ and L ₂ each main beam and sub beam split inspection light flux uniformly divided with equal intensity similarly to the above exposure apparatus, M ₁ and M ₂ Inspection masks, 1240a and 1240b are optical path length control chambers, 1265
Denotes a 1: 1 projection lens system, L denotes a synthetic inspection light beam, and 1266 denotes a photodetector.

The projection lens 1265 may have a magnification greater than 1 or may have a reduced magnification if necessary. However, in the case of reduction, the projection lens system must be able to resolve the accompanying pattern.

Next, the operation of the present apparatus will be described. The mask for the inspected mask M ₁ is turned on mask phase inversion shift to the first, the reference mask M ₂ has the identical opening patterns, the phase shift processing to the shifter pattern (associated pattern and the complementary pattern) portion is The case in which no phase shift film is formed, that is, the case in which the phase shift film is not formed will be described. In this case, by adjusting the optical path control means 1240a and b, and to equalize the optical path L ₁ and L ₂ (or a phase difference of 2n [pi]), in the composite image, - at all normal case shifter
The pattern will not be visible. On the other hand, when the thickness of the phase shift film is abnormal, that portion becomes a bright portion and the detector 1
266. In this case, since the corresponding main pattern is imaged as a bright portion, the mutual relationship between the defective portion and the main pattern can be clearly grasped.

Second, a description will be given of a case where the masks M ₁ and M ₂ to be inspected are a main mask and a sub-mask, respectively, in a mask inspection for multi-mask phase inversion shift. In this case, if the optical path length control means 1240a and 1240b are adjusted so that the phase difference between the _two optical paths L ₁ and L ₂ is zero or equivalent, the main surface and the sub-pattern (association) are formed on the image plane. Pattern) are imaged. Therefore, the defect can be comprehensively determined by electrically comparing the combined pattern and the mask design pattern information.

Third, in a mask inspection for a multi-mask phase inversion shift (including a phase difference other than π),
The design is performed in a case where the inspected masks M ₁ and M ₂ are both masks that should be the same pattern having associated patterns that cannot be resolved by the exposure projection system. In this case, if the light dew length adjusting means 1240a and b are adjusted to set the phase difference to π or an equivalent value, the composite image of the normal accompanying pattern disappears or is weaker than the general case. Becomes On the other hand, if there is an abnormal pattern, only that portion becomes a clear bright portion.

(13) Embodiment 13 This embodiment relates to a technique which is effective when applied to reduced projection exposure of a wafer having a chip region having a height difference on the surface, such as a memory IC such as a DRAM.

FIG. 79 is a simplified front sectional view (optical system) of the step-and-repeat type 5: 1 reduction projection exposure apparatus of the embodiment. In the figure, 1302a, monochromatic light source (e.g., i-line) of b are each independently identical wavelengths, L _1, L ₂ each main beam and sub beam, 1304a, b, respectively main and auxiliary exposure illumination lens system (Koehler illumination ), 1314
a is a main mask for exposing a basin (peripheral circuit in the case of a memory IC), 1314b is a sub-mask for exposing a plateau (a memory cell or a memory mat portion in the case of a memory), and 1334i and 1334j are chips The shield part corresponding to the upper plateau part, 1334k is the main pattern part corresponding to the peripheral circuit pattern on the chip, 1344k is the shield part corresponding to the basin part on the chip, 1344i and j correspond to the memory mat on the chip L is a combined light beam by a half mirror, 1315 is a reduction projection lens system in which the object side and the image side are telecentric, 1
Reference numeral 303 denotes a wafer to be exposed, 1313i and 1313 denote plateaus (memory mat portions), and 1313k or 1324 denote basins (peripheral circuit portions).

FIG. 80 is a top view showing the arrangement of regions on the wafer corresponding to unit steps of exposure. In FIG.
The area surrounded by the broken line 313 and the entire area exposed by the unit step, that is, the unit exposure area, 1321 and 13
22 is a first and second chip area, respectively, 1323
And 1324 are peripheral circuit portions of each chip area, 1
Reference numeral 313k denotes a main exposure portion (a long rectangular portion separated by broken lines) corresponding to a basin or a valley, and 1313i and 1313i denote sub-exposure portions corresponding to a plateau or a plateau (both sides separated by broken lines).

Next, the operation of the reduction projection exposure apparatus of the present invention will be described. In this method, the exposure area 1313 is divided into two masks 1314a and 1314b. This corresponds to, for example, the memory mat regions 1313i and j and the peripheral circuit unit 1313k. These areas often have a step as shown in the figure (FIG. 79). In such a case, each area is formed as a pattern on a different mask, and those masks are separately set on the Z axis (same as the optical axis).
The exposure is performed simultaneously while adjusting in such a manner that the images in the respective regions are formed on the corresponding planes of the resist film on the wafer.

In this case, a plurality of light source lamps having the same wavelength are used as the light source. If there is a difference between both wavelengths, the chromatic aberration of the projection lens system 1315 will be affected. As in the twelfth embodiment, a light beam from a single light source may be split.

In this stepper, the projection lens system 131 is used.
5 is common to the light beams L ₁ and L ₂ , and has a telecentric configuration on both sides (object side and image side). Therefore, a slight movement of each mask in the Z-axis direction does not change the magnification. The imaging position can be changed.

(14) Embodiment 14 This embodiment is directed to a phase shift exposure method (hereinafter, referred to as “on-mask phase shift”) performed by forming a transparent film for inverting the phase on a predetermined portion on the same mask. The law is called ").

FIG. 81 is a simplified front sectional view (optical system) of the step-and-repeat type 5: 1 reduction projection exposure apparatus of the embodiment. In the figure, 1402a and b monochromatic exposure light source such as independent i-line with one another, L ₁ and L ₂ are the main beam and the sub-luminous flux, 1404a and b illumination lens system constituting the Koehler illumination, 1414a and b, A main mask for exposing a predetermined pattern in a lowland (on the wafer) portion;
1414b is a sub-mask for exposing a predetermined pattern in a highland portion on the wafer, 1414x and y are synthetic quartz mask substrates, 1414m and n are chrome light shielding portions, 1414b.
p and q are main openings corresponding to the pattern, 1414 s and t are transparent films for phase inversion provided on the opening corresponding to the phase shifter, L is a synthetic light beam by a half mirror, 1
Reference numeral 415 denotes a 5: 1 reduction projection lens system in which both the object side and the image side are telecentric, 1413k denotes a lowland portion on the wafer (wafer 1403), and 1413i denotes a highland portion on the wafer.

FIG. 82 shows a unit exposure area on a wafer 1403, and is a top view for explaining the exposure method of the present invention. In FIG. 14, reference numeral 1413 denotes a unit exposure area;
Reference numerals 1422 and 1422 denote chip regions corresponding to chips such as memories, 1423 and 1424 denote peripheral circuit portions corresponding to lowlands on the respective chips, 1451a denotes a portion provided with an opening 1414p as shown in FIG. Similarly, this is a portion where the opening 1414q is provided.

FIG. 83 is a plan view of a mask showing a specific example of a mask in the case where the predetermined pattern portions 1451a and 1451b in the lowland portion and the highland portion are long and thin patterns such as isolated Al wirings. This mask corresponds to a negative resist process. In the figure, 1414p and 1414q are:
Opening pattern corresponding to Al wiring, 1414 g
And h are slit opening patterns corresponding to the shifters, respectively, and 1414 s and t are phase inversion films formed thereon.

The operation and the like of the stepper of this embodiment are exactly the same as those of the embodiment 13 and their explanation is omitted. In this embodiment, two regions having steps can be simultaneously exposed by the on-mask phase shift method. This is effective when applied to an exposure step that cannot be performed. The method is valid for any type of on-mask phase shift method.

(15) Embodiment 15 This embodiment is directed to a cycle or an approximate cycle A to which the multi-mask phase shift method or the on-mask phase shift method of the present invention is applied.
1 relates to a method for forming a wiring pattern and the like.

FIGS. 84-C are wafer top views schematically showing the Al periodic patterns (on the wafer) which are the targets of Examples 15A-C. In FIG. 84, 1503 is the upper surface of the wafer, 1
553 is a peculiar pattern, 1559 and 1560 are adjacent patterns, and 1551 and 1552 are remaining periodic patterns. In FIG. 85, 1556 is a unique pattern, 156
1 and 1562 are adjacent patterns, 1554 and 15
55 is the remaining periodic pattern, and 1503 is the upper surface of the wafer. In FIG. 86, 1558 is a peculiar pattern corresponding to the end of the periodic Al wiring pattern, 1557 is the remaining periodic pattern, and 1503 is the upper surface of the wafer.

FIG. 87 is a layout or superimposed layout diagram on a mask corresponding to FIG. 84 described above. A solid line indicates the boundary of the opening pattern of the main mask, and a broken line indicates the boundary of the opening pattern of the sub-mask. In the case of the on-mask phase shift mask, a solid line indicates an aperture pattern having a phase shift amount “0”,
The broken line corresponds to the aperture pattern with the phase shift amount “π”.
87 to 89, the Al line width is 0.3 to 0.4.
μm, each figure is drawn at the same magnification.

In FIG. 87, 1514 (hereinafter, mainly the case of the multi-mask phase inversion shift method) will be described.
Is a quartz mask substrate, and 1559a is an Al line 1 on the main mask.
559, a shifter pattern on the sub-mask associated with it, 1553b is a main opening pattern on the sub-mask corresponding to Al line 1553, and 1560a is a main opening pattern on the main mask corresponding to Al line 1560. The aperture pattern, 1560b, is the associated shifter pattern on the sub-mask, and 1559c is the auxiliary aperture pattern to counteract ghosts that may result from being equidistant from apertures 1559a, 1560a corresponding to the Al lines on both sides. is there.

FIG. 88 is a mask layout diagram corresponding to FIG. 85 similar to FIG. 87 described above. In FIG.
Is a mask substrate, 1556a is a main opening (on the main mask) corresponding to the Al line 1556 in FIG. 85, and 1556b and b
Is the associated shifter pattern on the sub-mask, 15
61b and 1562b are 1561 and 1562, respectively.
Is an opening pattern on the sub-mask corresponding to.

FIG. 89 is a mask layout diagram corresponding to FIG. 86 similar to FIGS. 87 and 88 described above. In the figure, 1
558a is the main opening on the main mask corresponding to the end Al wiring 1558 of FIG. 86, 1558b is the corresponding shifter pattern on the sub-mask, and 1557b is the inner Al line 1
Main opening on sub-mask corresponding to one of 557, 151
4 is a mask substrate.

Next, how to use these masks will be described. First, FIG. 86 and FIG. 89 will be described. In such a dense periodic pattern, a mask of the type shown in FIG.
A layout is used. In this case, at the end of the periodic pattern, as can be inferred from the amplitude distribution in FIG.
The outer half of the line 1558 has a broad line width because there is no adjacent shifter pattern (complementary main pattern). Therefore, an additional accompanying opening pattern (shifter) 15 is provided so as to cancel the unnecessary spread.
58b are provided.

Next, the cases of FIGS. 85 and 88 will be described. In such a periodic pattern, as shown in FIG.
Alternatively, a mask layout having a phase shift equivalent to that is used, but in the case of protruding one by one as shown in FIG. 85 or in the case of protruding every few (or one), the protruding portion 1556 undesirably becomes thicker for the same reason as before. To avoid this, shifter patterns 1556b and 1556b are provided.

Next, the cases of FIGS. 84 and 87 will be described. Even in such a periodic pattern, “π” is alternately shown in FIG.
A mask layout having a phase shift of (or equivalent thereto) is used. However, when only one line is short as shown in FIG. A first problem arises in that the inside of each of the elements 1559 and 1560 becomes undesirably thick. Further figure
When the valleys of the amplitude shown in FIG. 74 are overlapped with each other, a second problem occurs in that a ghost appears between them. To solve the first problem, the associated shift patterns 1559b and 1560b are provided. In order to solve the second problem, an auxiliary pattern 1559c
(Assistant accompanying pattern).

The techniques described above are particularly effective when applied to a dense pattern portion in the following process. That is, processes 7P2, 7P4, 7P in FIG.
7, 7P10, and 7p12, and exposure processes 2, 4, 9, 11, 18, 20, 20, and 22 in the eighth embodiment. The mask and exposure method may be either on-mask phase shift or multi-mask phase shift.

(16) Embodiment 16 This embodiment is an explanation of a photoresist used for exposing a wafer of the present invention. The resist can be selected from FIG. 90 according to the wavelength of the monochromatic ultraviolet light source used for exposure.

The resist is applied uniformly over the entire upper main surface of the wafer to a thickness of, for example, 0.6 μm by a spin coater.

(17) Embodiment 17 This embodiment relates to improvement of a mask used for a pair mask or a multi-mask phase shift method.

FIG. 91 is a schematic sectional view of a main part of an optical system of a step-and-repeat type 5: 1 reduction projection exposure apparatus according to the same method. In the figure, 1702 is Hg lamp i rays ultraviolet monochromatic light source of, 1704 illumination optical lens system for forming a Koehler illumination, L is the illumination light, L ₁ and L ₂ are split illumination light, 1714a and b are primarily A main mask and a sub-mask corresponding to the divided light and the sub-divided light, 1751a are a first main opening pattern corresponding to the first isolated pattern, and 1754.
b is a second main opening pattern corresponding to the second isolated pattern, 1752a and 1753a are second sub opening patterns (ie, shifters) associated with the second main opening pattern, and 1755b and 1756b are the first main opening patterns. The first sub-aperture patterns 1740a and 1740b associated with the main aperture pattern are optical path length adjusting means or the same adjustment chamber as shown in FIG. 29, L is synthetic light, 1715 is a 5: 1 reduction projection lens system, Reference numeral 1703 denotes a wafer to be exposed, and reference numeral 1709 denotes a photoresist film uniformly coated on the wafer 1703.

FIG. 92 is a layout plan of a superposed mask showing how the main opening patterns corresponding to a large number of isolated patterns are distributed on the main mask and the sub-mask. In the same drawing, a mask substrate when 1714a is superimposed on 1714b, a pattern portion (one shot) to be simultaneously exposed, a solid circle in a dashed square is a main opening pattern on the main mask 1714a, The circles indicated by broken lines are the main opening patterns on the sub mask 1714b.

As described above, by uniformly distributing the main opening patterns on both masks, the heating by the exposure light of both masks can be made almost identical and uniform.

(18) Embodiment-18 FIG. 93 shows a step-and-repeat method 5: 1 for implementing a multi-mask phase shift method (pair mask phase shift method) according to an embodiment of the present invention. FIG. 2 is a schematic front sectional view of an exposure optical system of a reduction projection exposure apparatus (stepper). In the figure, 1802 is Hg lamp i-line exposure light source (details Example-10) such as a, L is the original exposure light beam, L ₁ is the main exposure light beams split, L ₂ is also divided subsidiary exposure A light beam, 1851 is a prism for accommodating the light splitting half mirror 1806, 1840 is a phase adjustment or optical path length adjustment means or shifter as shown in 205, 29, or the following example in FIG. 12, and 1808a and 1807b are main light beams, respectively. Mirrors 1804a and 1804b for storing the condenser 6 forming Kohler illumination (Kohler), and 1840 for phase adjustment or optical path length adjustment as shown in 205, 29 in FIG. 12, or the following example. Means or shifters, 1808a and 1807b are mirrors for the main light beam and sub light beam, respectively, and 1804a and 1804b are each for Koehler illumination. (Kohler) condenser lens to form a, 1814a and b, respectively main and auxiliary mask, the composite prism for accommodating the synthesizing half mirror 1813 1854, L is luminous flux synthesis, 1815 5: 1
The reduction projection lens system is telecentric on both the object side and the image side. 1803 is a wafer to be exposed,
Reference numeral 1881 denotes a wafer stage as shown in FIGS. 27 and 19A.

In this embodiment, since the main exposure optical axis penetrating the wafer and the main illumination optical axis penetrating the light source are orthogonal to each other, it is comparatively possible to configure the optical paths of the main and sub-divided beams almost symmetrically. Easy to do.

Note that the present apparatus is not limited to the phase shift method,
It goes without saying that the present invention can be widely applied to the exposure method using two masks described in the other embodiments of the present application.

(19) Embodiment 19 In this embodiment, a specific example of an exposure illumination system for performing the pair mask phase shift method (multi-mask phase shift method) of the present invention and another example of the exposure optical system will be described. One example will be described.

FIG. 19A shows the step-and-step of this embodiment.
FIG. 2 is a schematic front sectional view of an exposure optical system of a repeat type 5: 1 reduction projection exposure apparatus. In the same figure, 1902 is an ultra-high pressure mercury lamp, 1982 is an ellipsoidal mirror, L is the original exposure illumination light flux, 1
983, a first reflecting mirror (for example, an Al mirror), 1985, a shutter, 1986, a fly-eye lens, 1987, an aperture, 1988, a filter (for example, a short cut filter), and 1984, a second reflecting mirror (for example, a cold mirror). ), condenser lens 1904 constituting the Koehler illumination, a half mirror for splitting the original exposure light beam L on the primary and secondary exposure light beam L _1, L ₂ is 1906, 19
Numeral 40 denotes an optical path length adjusting means or a phase shift plate (205 in FIG. 12, 540a, b or the like in FIG. 27) shown in another embodiment, 19
07b deflection mirror for sub beam L _2, mask equipped with the main pattern and the auxiliary pattern 1914, 1961 mask holder further XYZ and θ directions while holding the mask as well as other examples of adjusting the inclination, Reference numeral 1961c denotes a central opening, 1964a and b reference object-side projection lens systems for main and sub-beams, and 1949a denotes a main beam L.
Deflecting mirror for _1, synthesizing a half mirror for the combined light L by combining the main luminous flux L ₁ and sub beam L ₂ is 1913, 1
Reference numeral 954 denotes a combining prism for accommodating a half mirror, and 1915 denotes an object-side lens system 1964a and 196.
4b, an image-side lens system which is a part of a 5: 1 reduction projection lens system configured to be telecentric on both the object side and the image side (similar to Embodiment 11), 1903 is a wafer to be exposed,
Reference numeral 1976 denotes a wafer suction table which also serves as a θ drive table.
77 is a vertical direction, that is, a Z-axis moving table, 1979 is a horizontal direction, that is, an X-axis moving table, and 1980 is another horizontal direction, that is, a Y-axis moving table.

In this embodiment, since there is only one mask substrate,
No alignment between the main and sub masks is required.

(20) Twentieth Embodiment This embodiment describes a two-dimensional locally variable shifter plate which can be used as an optical path length adjusting means or a shifter plate shown in other embodiments.

FIG. 95 is a simplified front sectional view of the stepper when the variable shifter of this embodiment is replaced with or added to the shift plate 1940 of FIG. 19A. In FIG.
Reference numeral 2 denotes an ultraviolet or far-ultraviolet light source as shown in FIGS. 76 and 19A, L denotes an original exposure light beam, and 2091 denotes a phase detector or scanner for measuring the phase of coordinates (x, y) on the field of the original exposure light beam. a half mirror for 2006 to divide the original exposure light beam L to main luminous flux L ₁ and sub beam L _2, 204
0 sets the difference Δφ (x, y) between the phase of the coordinates (x, y) of the main light beam L ₁ and the phase of the same coordinates of the sub light beam L ₂ to a desired value locally (for each minute portion). 2D variable phase shift plate or shifter for, L ₁ (x, y) and L ₂ (x, y)
Indicates the coordinate (x, y) portion of each light flux L ₁ and L ₂ . 2
Reference numeral 014 denotes a mask on which a main pattern and a sub-pattern are mounted in isolated places on a single mask. In the figure, the thickness of each part of the mask is different, and the phase shift when passing through the mask is represented by coordinates (x, y). ) Is exaggerated. 2049
a is a deflecting mirror for the main light beam L ₁ , 2013 is a combining half mirror for combining the main light beam L ₁ and the sub light beam L ₂ to obtain L ₁ , φ ₁ (x, y) and φ ₂ (x, y) are L ₁ (x, y) and L on the reference plane immediately before the synthesis, respectively.
₂ (x, y) phase 2015 is a projection lens system that constitutes a 5: 1 reduction projection system by itself or together with other lens groups, and is telecentric on both the object side and the image side. Reference numeral 2003 denotes a semiconductor wafer to be exposed;
Reference numeral 2 denotes a phase difference Δφ over the entire exposure field (unit shot) based on the phase difference Δφ (x, y) data between the divided lights at the coordinates (x, y) detected by the scanner 2091.
Is a variable shifter control circuit for controlling the variable shifter 2040 to a constant uniform value.

FIG. 96 is an enlarged view of one main surface of the variable shifter 2040 shown in FIG. 95. In the figure, 2040a is a large number of square transparent electrodes, and 2041 is a gap without electrodes. When the width of the gap is set to be equal to or smaller than the size corresponding to the minimum resolution dimension on the wafer, it is effective to reduce noise due to the gap. One side of the square electrode is, for example, about 20 μm to 200 μm. Further, it is desirable that the position of the variable shifter 2014 on the optical path is near the optical axis of the optical member whose phase variation is to be compensated. That is, when the largest cause of the phase variation in a single shot is the mask substrate, it is effective to dispose it on the optical axis near the mask.

FIG. 97 is a sectional view taken along line XX of the variable shifter shown in FIG. In the figure, reference numeral 2042 denotes Pockels (Pockels)
els) An electro-optic crystal having the effect shown in FIG. 98, 2040a and 2040a are opposing square transparent electrodes (segments), and 2043 is a transparent insulating film. In the insulating film 2043, a transparent wiring having a width equal to or smaller than a minimum resolution (on a wafer) is formed so that a desired voltage can be independently applied to each segment. The variable shifter control circuit 2092 controls the voltage of a large number of segments via these wirings,
The variation of the phase difference Δφ within a single shot, that is, a single step exposure area is compensated.

(21) Documents Supplementing the Description of the Present Application Logical explanations on the on-mask phase shift exposure method, mask creation methods, pattern calculation methods, experimental data, and the like are described below. , And the description of the embodiment of the present invention will be given. In other words, Japanese Patent Application No. 63-20
No. 5350 (filed on November 22, 1988) and Japanese Patent Application No. 1-257226 (filed on October 2, 1999), and corresponding US patent applications 07/437, 26.
8 (filed on November 16, 1989), Japanese Patent Publication No. 62-
No. 50811, "Nikkei Microdevices", May 1990, pp. 74-75, "Improving Resolution in Photolithography with a Phase Shifting Mask" by E.I.E.E. E-Transaction on Electron Devices ED-29, vol. 12, no. 1982, p. 1828-1836 ('Improving Resolution in
Photolithograph with a Phase-Shifting Mask ', Leve
nson et al, IEEE Transaction on Electron Devices,
vol.ED-29, No.12 December 1982, P.1828-1836), Ito et al., "Correcting Projection Image Distortion of Photomask Patterns for 1 μm Processes," Transactions of the Institute of Electronics, Information and Communication Engineers, May 1985, vol.
J68-C No. 5, pages 325-332.

Japanese Patent Application Laid-Open No. Sho 62-171123 discloses an exposure illumination system using a high-pressure mercury lamp or the like.

Japanese Patent Application Laid-Open No. 61-22626 discloses a configuration of a projection lens system having a double-sided telecentric structure, which is incorporated in the description of the embodiments of the present invention.

Japanese Patent Application Laid-Open (JP-A) No. 61-43420 discloses a technique for producing a mask using an electron beam, and this is incorporated in the description of the present embodiment.

[0279]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

An appropriate resist process can be selected in accordance with the shape of the pattern to be formed. Therefore, the phase of the light transmitted through the light transmitting portion adjacent to the light transmitting portion via the light shielding portion is inverted so that the contrast of the projected image can be improved. When a semiconductor device is formed using a phase shift method that improves the above, the design of a mask including the arrangement of the phase shift regions becomes relatively easy, so that a semiconductor device with high pattern accuracy can be manufactured.

[Brief description of the drawings]

FIG. 1 is an overall view of a phase shift mechanism provided in an exposure apparatus which is I of Embodiment 1 of the present invention.

FIG. 2 is an enlarged sectional view of the mask according to the embodiment of the present invention.

3A and 3B are plan views of a pair of circuit patterns formed on the mask. (C) is a plan view of a circuit pattern obtained by synthesizing the pair of circuit patterns.

FIGS. 4A to 4G are explanatory diagrams respectively showing amplitude and intensity of light transmitted through a transmission region of the circuit pattern shown in FIGS. 3A and 3B;

FIGS. 5A and 5B are plan views of a pair of alignment marks formed on the mask. (C) is a plan view of a circuit pattern obtained by combining the pair of alignment marks.

FIGS. 6A and 6B are plan views showing another example of a pair of circuit patterns formed on the mask of II of Embodiment 1 of the present invention. (C) is a plan view of a circuit pattern obtained by synthesizing the pair of circuit patterns.

FIGS. 7A to 7G are explanatory diagrams respectively showing amplitude and intensity of light transmitted through a transmission region of the circuit pattern shown in FIGS. 6A and 6B.

8 (a) and (b) show III of Example 1 of the present invention.
FIG. 9 is a plan view showing another example of the pair of circuit patterns formed on the mask of FIG. (C) is a plan view of a circuit pattern obtained by synthesizing the pair of circuit patterns.

FIGS. 9A to 9E are explanatory diagrams showing the amplitude and intensity of light transmitted through the transmission region of the circuit pattern shown in FIGS. 8A and 8B, respectively.

FIGS. 10A to 10D are explanatory diagrams respectively showing the amplitude and intensity of light transmitted through a transmission region of a conventional mask.

FIGS. 11A to 11D are explanatory diagrams respectively showing the amplitude and intensity of light transmitted through a transmission region of a conventional mask provided with a transparent film.

FIG. 12 is a main part configuration diagram of an exposure optical system that is Embodiment 2 of the present invention.

13 (a) and 13 (b) are each a plan view of an essential part showing an example of a pattern configuration of the mask of FIG. 12; (C) is a plan view of a desired pattern formed by the patterns.

14 (a) and (b) are plan views of relevant parts showing an example of a pattern configuration of the mask of FIG. 12, respectively. (C) is a plan view of a desired pattern formed by the patterns.

FIGS. 15A and 15B are plan views of relevant parts showing an example of the pattern configuration of the mask of FIG. 12; (C) is a plan view of a desired pattern formed by the patterns.

16 (a) to 16 (g) are explanatory diagrams showing the amplitude and intensity of light transmitted through a transmission region of the mask of FIG.

17 (a) to (h) are explanatory diagrams showing the amplitude and intensity of light transmitted through a transmission region of the mask in FIG.

FIGS. 18A to 18G are explanatory diagrams showing the amplitude and intensity of light transmitted through the transmission region of the mask shown in FIG.

FIG. 19 is a sectional view of a mask.

FIGS. 20A to 20E are explanatory diagrams of a pattern alignment method used in the apparatus of the present invention.

FIG. 21 is a schematic front sectional view showing an outline of an exposure optical system of a step-and-repeat type 5: 1 reduction projection exposure apparatus according to Embodiment 3 of the present invention.

FIG. 22 is a sectional view of a mask corresponding to a periodic or quasi-periodic line and space pattern according to the embodiment of the present invention.

FIG. 23A is a main mask pattern (positive mask) corresponding to the periodic pattern having steps in the above embodiment, and FIG. 23B is a sub-mask pattern,
FIG. 3C is a plan view of the synthetic aperture pattern, and FIG.
FIG. 3 is a cross-sectional view of a periodic step portion of a semiconductor integrated circuit device being manufactured on a wafer to be exposed.

FIG. 24 shows a case where the phase difference φ between L1 and L2 in the above embodiment is (2n
+1) A diagram showing a state of a shift of the image plane corresponding to the main and sub-patterns when the image plane is shifted back and forth from π.

FIG. 25A is a plan view showing a phase shift alignment mark formed on a main pattern portion in the embodiment.
(B) is a top view of the opening pattern for phase matching formed in the sub pattern part. (C) is a projection pattern at the time of combining these.

FIG. 26 is a schematic sectional view of a stepper device according to a fourth embodiment of the present invention.

FIG. 27 is a schematic front sectional view of an exposure projection optical system of a step-and-repeat type 5: 1 reduction projection exposure apparatus according to a fifth embodiment of the present invention.

FIG. 28 is a schematic front sectional view of an exposure light source and an illumination (exposure) optical system of the apparatus.

FIG. 29 is an enlarged sectional view of a phase difference setting unit of the same device.

FIG. 30 is a top view of a wafer holding unit of the apparatus.

FIG. 31 is a plan view of a mask pattern corresponding to an isolated band-shaped pattern according to Embodiment 6 of the present invention.

FIG. 32 is a plan view of a mask pattern corresponding to an isolated square pattern according to Embodiment 6 of the present invention.

FIG. 33 is a plan view of a mask pattern corresponding to the isolated square pattern according to the modification of FIG. 32;

FIG. 34 is a plan view of a mask pattern corresponding to an “L” -shaped pattern according to Embodiment 6 of the present invention.

FIG. 35 is a mask pattern plan view corresponding to the “L” -shaped pattern according to the modification of FIG. 34;

FIG. 36 is a plan view of a mask pattern corresponding to a bent isolated belt-shaped pattern according to Embodiment 6 of the present invention.

FIG. 37 is a plan view of a mask pattern corresponding to the bent and isolated strip-shaped pattern according to the modification of FIG. 36;

FIG. 38 is a plan view of a mask pattern corresponding to a uniform periodic strip pattern according to Embodiment 6 of the present invention.

FIG. 39 is a top view of a wafer showing an exposure step according to Embodiment 7 of the present invention.

FIG. 40 is a plan view showing a unit exposure area in an exposure method according to Embodiment 7 of the present invention.

FIG. 41 is a flow sectional view showing a positive process according to Embodiment 7 of the present invention.

FIG. 42 is a flow sectional view showing a positive process according to Embodiment 7 of the present invention.

FIG. 43 is a flow sectional view showing a positive process according to Embodiment 7 of the present invention.

FIG. 44 is a flow sectional view showing a negative process according to Embodiment 7 of the present invention.

FIG. 45 is a flow sectional view showing a negative process according to Example 7 of the present invention.

FIG. 46 is a flow sectional view showing a negative process according to Example 7 of the present invention.

FIG. 47 shows a twin well S according to Embodiment 7 of the present invention.
FIG. 4 is an overall flowchart showing a photolithography step in a RAM process.

FIG. 48 is a flow sectional view of an SRAM wafer process corresponding to FIG. 47 of the present invention;

FIG. 49 is a flow sectional view of an SRAM wafer process corresponding to FIG. 47 of the present invention;

FIG. 50 is a flow sectional view of a wafer process of the SRAM corresponding to FIG. 47 of the present invention;

FIG. 51 is a flow sectional view of a wafer process of the SRAM corresponding to FIG. 47 of the present invention;

FIG. 52 is a flow sectional view of a wafer process of the SRAM corresponding to FIG. 47 of the present invention;

FIG. 53 is a flow sectional view of a wafer process of the SRAM corresponding to FIG. 47 of the present invention;

FIG. 54 is a flow sectional view of an SRAM wafer process corresponding to FIG. 47 of the present invention;

FIG. 55 is a plan layout view of a chip area of the SRAM.

FIG. 56 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention.

FIG. 57 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 58 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 59 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 60 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention.

FIG. 61 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 62 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 63 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 64 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 65 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 66 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 67 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 68 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 69 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 70 is a flow sectional view showing a wafer step of the DRAM according to Embodiment 8 of the present invention;

FIG. 71 is a plan layout view of a chip area of the DRAM;

FIG. 72 is a plan layout view of a unit translation cycle of a memory cell region of the DRAM.

FIG. 73 is a graph for explaining the distribution of the amplitude intensity and energy intensity of light when the phases of adjacent patterns are the same.

74 is the same distribution graph when the phases are different by 180 ° (relatively) as in FIG. 73.

FIG. 75 is a schematic sectional view of an optical system for explaining the principle of reduced projection according to the present invention.

FIG. 76 is a table showing conditions of a monochromatic light source for exposure used in the exposure method of the present invention.

FIG. 77-5 of the eleventh embodiment of the present invention in which all the projection lens systems are made common using the object side telecentric configuration:
1 is a simplified front sectional view of a reduced projection exposure apparatus.

FIG. 78A is a simplified front sectional view of a mask inspection apparatus according to a twelfth embodiment of the present invention;

FIG. 79 is a simplified front sectional view of a step-and-repeat 5: 1 reduction projection exposure apparatus according to Embodiment 13 of the present invention using two light sources that are not coherent with each other.

FIG. 80 is a mask or wafer plan view showing a layout of a unit exposure area exposed by the exposure method shown in FIG. 79;

FIG. 81 is a simplified cross-sectional view of a step-and-repeat type reduced projection exposure apparatus (using mutually non-coherent light sources) for explaining an exposure method according to Embodiment 14 of the present invention;

FIG. 82 is a plan layout view of a single-position light area (mask or wafer) in the method of FIG. 81;

FIG. 83 is a plane pattern diagram of a mask used in the method of FIG. 81;

FIG. 84 is a plan view of a pattern on a wafer corresponding to the quasi-periodic pattern according to Example 15 of the present invention.

FIG. 85 is a plan view of a pattern on a wafer corresponding to another quasi-periodic pattern of the embodiment.

FIG. 86 is a plan view of a pattern on a wafer corresponding to still another quasi-periodic pattern of the embodiment.

87 is a plan layout diagram or a superimposed plan layout diagram of a mask in the on-mask or multi-mask phase shift method corresponding to the pattern on the wafer in FIG. 84 described above.

FIG. 88 is a similar plan layout view corresponding to FIG. 85;

FIG. 89 is a similar plan layout view corresponding to FIG. 86;

FIG. 90 is a list of photoresists used in the practice of the invention.

FIG. 91 is a simplified front sectional view of a step-and-repeat type 5: 1 reduction projection exposure apparatus showing an exposure method for mutually mounting an associated pattern on two masks according to Embodiment 17 of the present invention;

FIG. 92 is a superposition mask pattern diagram for explaining the same method.

FIG. 93 is a simplified multi-unit according to the eighteenth embodiment of the present invention.
FIG. 3 is a front sectional view of a mask / stepper.

FIG. 94 is a front sectional view of a pair mask (pattern) exposure apparatus (stepper) using a single mask substrate according to the nineteenth embodiment for explaining the configuration of the individual illumination light source of the exposure apparatus of each embodiment of the present invention.

FIG. 95 is an overall configuration diagram of a two-dimensional phase matching device according to Embodiment 20 of the present invention.

FIG. 96 is a top view of the same two-dimensional phase shift plate.

FIG. 97 is a sectional view of the same two-dimensional phase shift plate;

FIG. 98 is a table of crystals having an electro-optical effect used for the phase shift plate.

Claims (13)

[Claims] A positive mask formed on a semiconductor wafer by transmitting light by irradiating light to a first mask in which a first region and a second region surrounded by the first region are formed. Exposing a pattern to the photosensitive film of the step of: developing the positive photosensitive film to remove a pattern formed on the positive photosensitive film by the second region of the mask; Processing the semiconductor wafer using the positive photosensitive film, a third region and a fourth region surrounded by the third region are formed, and a part of the light transmitting region of the mask; The second mask having a phase shift region where the phase is inverted with respect to the light transmitted through the other light transmitting region of the mask is irradiated with light, and formed on the semiconductor wafer by the transmitted light. Exposing a pattern to a negative photosensitive film; Developing the photosensitive film, leaving a pattern imaged by the fourth region of the mask, removing the surrounding negative photosensitive film, using the developed negative photosensitive film And processing the semiconductor wafer. A method for manufacturing a semiconductor device, comprising: 2. The third region is a light-shielding region, the fourth region is a light transmitting region, and the other light transmitting region of the second mask passes through the first region. The method according to claim 1, wherein the method is provided near the second region. 3. A phase shift region in which a phase of light transmitted through another light transmitting region of the mask is inverted in a part of a light transmitting region of the first mask. 3. The method of manufacturing a semiconductor device according to claim 2, wherein 4. The first area is a light-shielding area, the second area is a light-transmitting area, and the other light-transmitting area of the first mask passes through the first area. 4. The method according to claim 3, wherein the semiconductor device is provided near the second region. 5. The apparatus according to claim 1, wherein the second area is a light transmitting area, and the other light transmitting area of the first mask is provided so as to be in contact with the second area. Item 3
The manufacturing method of the semiconductor device described in the above. 6. A plurality of light transmitting patterns extending in one direction for forming a wiring layer on a first substrate are formed close to each other via a light shielding portion and transmit adjacent patterns. The step of exposing a pattern to a negative resist layer provided on a conductive film on the first substrate by transmitting light to a second substrate such that the phases of the light are opposite to each other, Developing the negative resist layer, processing the conductive film using the developed negative resist layer, and forming a wiring pattern on the first substrate; A step of transmitting light to a third substrate on which a light transmission pattern for forming an opening is formed, and exposing the pattern to a positive resist layer provided on the insulating film, Developing process, before developed Using the positive resist layer, forming an opening pattern on the first substrate, a pattern forming method characterized by having a city. 7. A plurality of light transmitting patterns for forming said openings are provided in close proximity to each other, and the phases of light passing through adjacent patterns via a light shielding portion are opposite to each other. 7. The pattern forming method according to claim 6, wherein the pattern is formed. 8. An auxiliary light transmitting region for transmitting light in an auxiliary manner is provided around a light transmitting pattern for forming the opening, and the light transmitted through the auxiliary light transmitting region is
7. The pattern forming method according to claim 6, wherein the opening pattern is exposed on the first substrate by interfering with and weakening light transmitted through the light transmitting pattern for forming the opening. 9. The third substrate has a boundary with a light transmission pattern for forming the opening, and a light transmitted through the light transmission pattern for forming the opening and a phase of the transmitted light. 7. The pattern forming method according to claim 6, wherein another light transmission pattern is provided so that the light transmission pattern is reversed. 10. The pattern forming method according to claim 6, wherein the opening is a hole. 11. A light-transmitting pattern and a light-shielding portion for forming a line-and-space pattern on a semiconductor wafer are formed close to each other, and phases of light passing through adjacent light-transmitting patterns are opposite to each other. Exposing a pattern to a negative resist layer provided on the semiconductor wafer by transmitting light through a first photomask that is in phase, developing the negative resist layer, developing the developed negative Using a resist layer, forming a line and space pattern on the semiconductor wafer, transmitting light to a second photomask on which a light transmission pattern for forming a hole pattern on the first substrate is formed; Exposing a pattern to a positive resist layer provided on the semiconductor wafer, developing the positive resist layer, By using the positive resist layer that is the image, forming a hole pattern on the semiconductor wafer, a pattern forming method characterized by having a city. 12. A first photomask in which a group of patterns for forming a plurality of gate lines of a field effect transistor is formed on the semiconductor wafer, the method comprising: forming a negative resist film on a semiconductor wafer; The group is formed such that a plurality of light transmitting regions corresponding to gate lines formed on the semiconductor wafer are formed via light shielding regions, and the phases of light transmitted through adjacent light transmitting regions are inverted from each other. Forming a pattern on the negative resist film using the first photomask, forming a gate line of a field effect transistor on the semiconductor wafer using the negative resist film on which the pattern is formed, Forming an insulating film on the semiconductor wafer on which the gate line is formed, forming a positive resist film on the insulating film Forming a second photomask in which an opening pattern for forming an opening to be a through hole in the insulating film is formed, wherein the phase of transmitted light around the opening pattern is the opening pattern. Forming a pattern on the positive resist film by using the second photomask provided with a transmission region whose phase is inverted with light transmitted therethrough, using the positive resist film on which the pattern is formed. Forming a through hole in the insulating film. 13. After the step of forming the through hole,
A step of forming a final passivation film on the semiconductor wafer; a step of forming a positive resist film on the final passivation film; an opening pattern for forming an opening for a bonding pad in the final passivation film; Using a third photomask that does not have a light transmission region whose phase is inverted with light transmitted through the opening pattern,
13. The method according to claim 12, further comprising: forming an opening in the positive resist film.