JPH1083757A - Cold electron emitting element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cold electron emitting element of field emission type and its method of manufacturing, thereby it is practicable to suppress a large current flowing locally without raising the operating voltage and use a glass base board capable of being easily produced at a low cost and embodies with a large area. SOLUTION: A p-type semiconductor thin film 3a and an n-type semiconductor thin film 3b are laminated on an emitter wiring layer 2 in this order and thereover an emitter 4 is formed, which is itself equipped with a current controlling function by providing pn joint, and thus it is possible to suppress a large current flowing locally without raising the working voltage and also minimize current variation through control of individual elements. Further a hydrogenated amorphous silicon thin film is used as semiconductor thin film to form the pn joint, which makes possible the use of a glass base board 1 capable of being easily produced at a low cost and embodies with a large area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type cold electron-emitting device that emits electrons by a strong electric field and a method of manufacturing the same. More specifically, as an electron generating source or an electron gun of an optical printer, an electron microscope, an electron beam exposure device, or the like, or as a micro illumination source of an illumination lamp, particularly, an array-like FEA (FEA) constituting a flat display
The present invention relates to a cold electron-emitting device useful as an electron source used in "Field Emitter Array" and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a cathode ray tube has been widely used as an electronic display device. However, the cathode ray tube consumes a large amount of energy to emit thermoelectrons from a cathode of an electron gun, and is structurally large. There were problems such as requiring a volume.

[0003] For this reason, there has been a demand for a flat display in which cold electrons can be used instead of thermoelectrons, thereby reducing the energy consumption as a whole and further reducing the size of the device itself. There is also a strong demand for such a flat display to realize high-speed response and high resolution.

As a structure of such a flat display utilizing cold electrons, a structure in which minute cold electron-emitting devices are arranged in an array in a flat plate cell in a high vacuum is considered to be promising. As a cold electron-emitting device used therefor, a field-emission cold electron-emitting device utilizing a field emission phenomenon has been receiving attention. In this field emission type cold electron-emitting device, when the intensity of an electric field applied to a substance is increased, the width of an energy barrier on the surface of the substance is gradually reduced according to the intensity,
When the electric field intensity becomes a strong electric field of 10 ⁷ V / cm or more, electrons in a substance can break through the energy barrier by a tunnel effect, and the phenomenon that electrons are emitted from the substance is used. In this case, since the electric field complies with Poisson's equation, if a portion where the electric field is concentrated is formed on a member (emitter) that emits electrons, cold electrons can be efficiently emitted with a relatively low extraction voltage.

A common example of such a field emission type cold electron emitting device is a cold electron emitting device having a conical shape with a sharp tip as shown in FIG. In this element, a conductive layer 62, an insulating layer 63 and a gate electrode 64 are sequentially laminated on an insulating substrate 61, and an opening A reaching the conductive layer 62 is formed in the insulating layer 63 and the gate electrode 64. Have been. A conical emitter 65 is formed on the conductive layer 62 in the opening A so as not to contact at least the gate electrode 64.

Among such conical emitters, Spindt-type emitters are widely known.

An example of manufacturing a cold electron emitting device having a Spindt-type emitter will be described with reference to FIGS.

First, as shown in FIG. 7A, an insulating layer 73 and a gate electrode 74 are sequentially formed on a glass substrate 71 on which an emitter wiring 72 is formed in advance by a sputtering method or a vacuum evaporation method. Subsequently, the insulating layer 73 and a part of the gate electrode 74 are removed by using the photolithography method and the reactive ion etching method (RIE).
Etching is performed so that a circular hole (gate hole) is opened until 2 is exposed.

Next, as shown in FIG. 7B, a lift-off material 75 is formed only on the gate electrode 74 by oblique evaporation. The material of the lift-off material 75 is Al, MgO
And so on.

Subsequently, as shown in FIG.
1, on the perpendicular direction by ordinary anisotropic deposition
A metal material for the emitter 76 is deposited. At this time, as the deposition proceeds, the opening diameter of the gate hole is reduced, and at the same time, a conical emitter 76 is formed on the emitter wiring 72 in a self-aligned manner. The vapor deposition is performed until the gate hole is finally closed. As a material of the emitter, Mo, Ni, or the like is used.

Finally, as shown in FIG. 7D, the lift-off material 75 is peeled off by etching, and the gate electrode 74 is patterned if necessary. Thus, a cold electron emitting device having a Spindt-type emitter is obtained.

In such a Spindt-type cold electron-emitting device, a conical emitter can be formed relatively easily in a self-aligned manner by anisotropic vapor deposition, so that a wide range of emitter materials can be selected. As long as the material is a material that can be vapor-deposited, there is an advantage that any type of substrate, in particular, a glass substrate capable of increasing the area can be used.

When a cold electron emitting device utilizing a fine processing technique represented by a Spindt-type emitter is applied to a flat display or the like in particular, a small fluctuation of the emission current from the emitter is required to obtain a high quality image. Is essential.

The fluctuation of the emission current can be reduced to some extent by integrating the emitter.
This is because the effect of variations in emission characteristics of individual emitters is reduced by integration. However, in this method, the emission current from each emitter is merely averaged, so that it is impossible to suppress an abnormally large emission current that appears locally.

As means for reducing such a variation in emission current, US Pat. No. 3,789,471 discloses a technique in which a resistance layer is provided between an emitter wiring layer and an emitter in a Spindt-type cold electron emission element. It is shown.

An example of the configuration of a cold electron emission device having such a resistance layer will be described with reference to FIG.

A conductive layer 82 and a resistance layer 8 are formed on an insulating substrate 81.
3, an insulating layer 84 and a gate electrode 85 are sequentially laminated, and the insulating layer 84 and the gate electrode 85 are provided with a resistance layer 8
An opening A reaching 3 is formed. Then, at least the gate electrode 8 is formed on the resistance layer 83 in the opening A.
A conical emitter 86 is formed so as not to come into contact with 5.

In this case, the resistance layer 83 is electrically inserted between the conductive layer 82 and the emitter 86 in series. By the resistance layer 83, an action of equalizing the current between the elements is obtained. Further, a large current leading to element destruction is reduced, and the fluctuation of the emission current is reduced in proportion to the resistance value of the resistance layer 83. It is possible. The specific resistance of the resistance layer 83 is appropriately set to 10 ² to 10 ⁶ Ω · cm.

[0019]

However, in the cold electron emitting device provided with such a resistance layer, in order to obtain a sufficient current reduction characteristic with respect to a local large current,
In addition to the necessity of providing a larger resistance, there has been a problem that the current fluctuation can be reduced only relative to the characteristics of the individual elements, and that an increase in operating voltage is in principle unavoidable.

The present invention is intended to solve the above-mentioned problems of the prior art. In a field emission type cold electron emitting device, a local large current can be suppressed without increasing an operating voltage, and furthermore. It is an object of the present invention to be able to use a glass substrate which is easy to increase in area at low cost.

[0021]

In order to solve the above-mentioned problems, the present invention is directed to a lamination of a p-type semiconductor thin film and an n-type semiconductor thin film between an emitter wiring layer and an emitter of a field emission type cold electron emission element. A film is arranged, that is, p is used instead of the conventional resistance layer.
By forming an n-junction, adding a current control function to the emitter itself suppresses a local large current without increasing the operating voltage, and minimizes current fluctuations by controlling individual elements. By using a hydrogenated amorphous silicon thin film as a semiconductor thin film for forming such a pn junction, it is possible to use a glass substrate which is easy to increase in area at a low cost. .

That is, according to the present invention, first, an emitter wiring layer, an insulating layer, and a gate electrode are sequentially stacked on an insulating substrate, and the gate electrode and the insulating layer include the emitter wiring layer. An opening reaching the wiring layer is provided, and an emitter is formed on the emitter wiring layer in the opening so as not to contact the gate electrode. And at least a p-type semiconductor thin film and an n-type semiconductor thin film are laminated in this order, and the emitter is formed on the n-type semiconductor thin film. .

More preferably, as set forth in claim 2, the p-type semiconductor thin film is a p-type hydrogenated amorphous silicon thin film, and the n-type semiconductor thin film is an n-type hydrogenated amorphous silicon thin film. It is a cold electron emission element of a statement.

More preferably, in the p-type hydrogenated amorphous silicon thin film, boron is a dopant and the boron doping amount is 100 ppm to 1 ppm.
A hydrogenated amorphous silicon thin film in the range of 0%, and an n-type hydrogenated amorphous silicon thin film,
Phosphor is a dopant, and the phosphorus doping amount is 10 ppm or more.
3. The cold electron-emitting device according to claim 1, wherein the hydrogenated amorphous silicon thin film is in a range of 10%.

Further, the thickness of the p-type semiconductor thin film is in the range of 0.05 μm to 1 μm, and the thickness of the n-type semiconductor thin film is in the range of 0.05 μm to 1 μm. Item 7. A cold electron-emitting device according to item 1.

The cold electron emission element according to claim 1, wherein the p-type semiconductor thin film and the n-type semiconductor thin film are formed with an intrinsic semiconductor thin film interposed therebetween.

According to a sixth aspect of the present invention, in the cold electron emission device according to the fifth aspect, the intrinsic semiconductor thin film is a non-doped hydrogenated amorphous silicon thin film.

According to a seventh aspect of the present invention, the emitter wiring layer and the p-type semiconductor thin film are formed with an n-type semiconductor thin film as an ohmic layer interposed therebetween.
5. The cold electron-emitting device according to item 1.

Further, as in claim 8, the cold electron emitting device according to claim 7, wherein the n-type semiconductor thin film as the ohmic layer is an n-type hydrogenated amorphous silicon thin film.

According to a ninth aspect of the present invention, there is provided the cold electron emitting device according to the first aspect, wherein the insulating layer is made of an amorphous silicon nitride film.

According to a tenth aspect of the present invention, there is provided the cold electron emitting element according to the first aspect, wherein the shape of the emitter is any one of a cone, a cylinder, a truncated cone, and a truncated polygon.

[0032] According to a eleventh aspect of the present invention, there is provided the cold electron-emitting device according to the first aspect, wherein the emitter is made of n-type hydrogenated amorphous silicon.

According to a twelfth aspect of the present invention, there is provided the cold electron emitting device according to the first aspect, wherein a glass substrate is used as the insulating substrate.

Alternatively, an emitter wiring layer, an insulating layer and a gate electrode are sequentially laminated on an insulating substrate, and an opening reaching the emitter wiring layer is formed in the gate electrode and the insulating layer. Is provided on the emitter wiring layer in the opening so that the emitter is not in contact with the gate electrode, wherein the field emission type cold electron emitting element is provided between the emitter wiring layer and the emitter. Is a method for manufacturing a cold electron emission element, characterized in that at least a p-type semiconductor thin film and an n-type semiconductor thin film are laminated in this order, and an emitter is formed on the n-type semiconductor thin film. a) forming a metal thin film for forming an emitter wiring on an insulating substrate and patterning to form an emitter wiring layer; and (b) forming a p-type semiconductor thin film on the emitter wiring layer. And a step of forming an n-type semiconductor thin film on the p-type semiconductor thin film; (c) forming a layer of an insulating material on the n-type semiconductor thin film, and further forming a layer of a gate electrode material thereon (D) applying a photoresist on the surface, and forming the photoresist on an etching mask layer having a hole having a shape and a size corresponding to the opening of the gate by using a photolithography method; (E) etching the layer of the gate electrode material and the insulating material by reactive ion etching to form a gate hole in which the n-type semiconductor thin film is exposed and to form a gate electrode and an insulating layer; A) forming a lift-off layer by depositing a lift-off material only on the top and side surfaces of the gate electrode using an oblique deposition method; By using anisotropic deposition method having more deposition anisotropy deposited amount to the vertical direction, forming the emitter material inside the pores of the gate hole,
(G) a step of forming an emitter in a self-aligned manner; and (g) a step of lifting off an emitter material on an upper side or a side of the gate electrode; Is the way.

Further, in the step (c), in the step (c), the insulating material layer is made of amorphous silicon nitride, and this is reacted with a mixed gas containing either silane or disilane and ammonia. 14. The manufacturing method according to claim 13, which is formed by a PECVD method using a gas.

Alternatively, an emitter wiring layer, an insulating layer and a gate electrode are sequentially laminated on an insulating substrate, and an opening reaching the emitter wiring layer is formed in the gate electrode and the insulating layer. Is provided on the emitter wiring layer in the opening so that the emitter is not in contact with the gate electrode, wherein the field emission type cold electron emitting element is provided between the emitter wiring layer and the emitter. Is a method for manufacturing a cold electron emission element, characterized in that at least a p-type semiconductor thin film and an n-type semiconductor thin film are laminated in this order, and an emitter is formed on the n-type semiconductor thin film. h) forming a metal thin film for forming an emitter wiring on an insulating substrate and forming an emitter wiring layer by patterning; (i) forming a p-type semiconductor thin film on the emitter wiring layer Forming an n-type semiconductor thin film on the p-type semiconductor thin film; and (j) forming an etching mask material on the n-type semiconductor thin film, and forming the gate of the etching mask material film by photolithography. Forming an etching mask layer in which a portion having a shape and a size corresponding to the opening is left; (k) etching the n-type semiconductor thin film using a reactive ion etching method until the n-type semiconductor thin film remains; (L) laminating a layer made of an insulating material and a layer made of a gate electrode material in this order on the surface side of the n-type semiconductor thin film of the insulating substrate, thereby forming an insulating material on the n-type semiconductor thin film. Forming a layer and a gate electrode material layer; and (m) removing the etching mask layer,
Step of Lifting Off the Insulating Material Layer and Gate Electrode Material Layer Overlying It is a manufacturing method characterized by including any of the above (h) to (m).

Further, as set forth in claim 16, in any one of step (b) of claim 13 and (i) of claim 15, the p-type semiconductor thin film is a hydrogenated amorphous silicon thin film. Is formed by a PECVD method using a mixed gas of either silane or disilane and diborane as a reaction gas, and the n-type semiconductor thin film is a hydrogenated amorphous silicon thin film, which is formed using either silane or disilane and phosphine. 16. The method according to claim 13, wherein the film is formed by a PECVD method using a mixed gas consisting of:

Further, the gas flow ratio of diborane to either silane or disilane is in the range of 100 ppm to 10%, and the gas flow ratio of phosphine to either silane or disilane. The ratio is in the range of 10 ppm to 10%.
6. The method according to item 6.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional perspective view of one example of the cold electron emitting device of the present invention. As shown in the figure, this cold electron emission element has a structure in which an insulating substrate 1, an emitter wiring layer 2, an insulating layer 5, and a gate electrode 6 are sequentially laminated. An opening A reaching the emitter wiring layer 2 is provided in the gate electrode 6 and the insulating layer 5, and a p-type semiconductor thin film 3a and an n-type semiconductor are formed on the emitter wiring layer 2 in the opening A. A pn junction layer composed of a laminated film of the thin films 3b is provided, and a conical or truncated conical emitter 4 is formed on the n-type semiconductor thin film 3b so as not to contact the gate electrode 6.

In the present invention, the insulating substrate 1 is used as a support substrate for a cold electron emission element, and an insulating substrate whose area can be particularly easily increased can be preferably used.
As such an insulating substrate, a glass substrate, a ceramic substrate, a quartz substrate, or the like can be used.

The emitter wiring layer 2 is formed from a material having low wiring resistance and good adhesion to the insulating substrate 1. As such a material, particularly preferably, Cr or Al, Cr
A laminated film can be given.

The thickness of the emitter wiring layer 2 is not particularly limited as long as sufficient wiring resistance and adhesion can be obtained, but is usually 0.05 to 0.5 μm, and has both good wiring resistance and adhesion. In consideration of ease of film formation and saving of material cost, the thickness is more preferably 0.1 to 0.3 μm.

The p-type semiconductor thin film 3a and the n-type semiconductor thin film 3
b is a laminated film that functions to limit the current emitted from the emitter. As a p-type semiconductor thin film, for example, a boron-doped hydrogenated amorphous silicon thin film, and further, an n-type semiconductor As the thin film, for example, a laminated film of a phosphorus-doped hydrogenated amorphous silicon thin film is used. Here, a pn junction is formed in the base layer of the emitter 4 and has a current control function for driving the element. By generating a depletion layer on the pn junction surface, the emission current is limited, and current control becomes possible. Further, by using a semiconductor thin film that can be formed at a low temperature such as a hydrogenated amorphous silicon thin film as a semiconductor, it is possible to use a glass substrate that is inexpensive and advantageous for increasing the area.

Here, the hydrogenated amorphous silicon used in the present invention is silicon which does not show a peak showing crystallinity when analyzed by a thin film X-ray diffraction method.
It means silicon for which hydrogen bonded to silicon is observed by T-IR analysis. Therefore, hydrogenated amorphous silicon includes partially microcrystalline silicon.

The impurity control of hydrogenated amorphous silicon exhibiting p-type conductivity can be easily attained by controlling the reaction gas used for film formation by PECVD, for example, the mixing ratio of silane and diborane. The doping amount is preferably such that a thin film having p-type conductivity and a relatively low resistance can be obtained, and in that sense, 100 ppm to 10% can be particularly preferably used. If the doping amount is 100p
If it is lower than pm, the resistance tends to be high and the p-type conductivity is not sufficiently exhibited.
When the ratio exceeds 1, the proportion of boron atoms that function (activate) as acceptors is extremely reduced, and good p-type conductivity tends not to be obtained. In addition, PECVD described in this specification is "Plasma Enhanced Chemical
VaporDeposition ".

Control of impurities of hydrogenated amorphous silicon having n-type conductivity can be easily performed by controlling a reaction gas used in film formation by PECVD, for example, a mixture ratio of silane and phosphine. The doping amount is n
It is preferable that a thin film having mold conductivity and a relatively low resistance is obtained, and 10 ppm to 10% can be particularly preferably used. If the doping amount is less than 10 ppm, the resistance tends to be high, and sufficient n-type conductivity is not exhibited. If the doping amount exceeds 10%, the proportion of phosphorus atoms functioning as donors is reduced. It tends to be extremely reduced and no good n-type conductivity can be obtained.

The p-type semiconductor thin film 3a and the n-type semiconductor thin film 3
The thickness of b can be appropriately determined as necessary, but is preferably 0.05 μm to 1 μm. The thickness ratio between the p-type semiconductor thin film and the n-type semiconductor thin film is not particularly limited, but is preferably about 1: 1. If the thickness is less than 0.05 μm, there is a tendency that sufficient pn junction characteristics cannot be obtained. If the thickness exceeds 1 μm, the substantial resistance increases,
Emission characteristics tend to deteriorate.

The emitter 4 is a member that emits electrons directly from its surface. In the present invention, various materials such as a metal and a semiconductor can be used.

The thickness (height) of the entire emitter 4 can be appropriately determined as required, and is usually 0.3 to 2 μm.
m is preferable.

The shape of the emitter is preferably a cone, a cylinder, a truncated cone, or a truncated polygon.

The insulating layer 5 is a layer for electrically insulating the emitter wiring layer 2 from the gate electrode 6. Such an insulating layer 5 can be formed from a known material used as an insulating layer of a cold electron-emitting device. However, the insulating layer 5 has good insulating properties and can be formed by anisotropic vapor deposition. Can be mentioned. When an insulating material is continuously formed from a p-type semiconductor thin film material and an n-type semiconductor thin film material, amorphous silicon nitride by PECVD using a mixed gas of silane or disilane and ammonia as a reaction gas is used. Can be used.

The thickness of the insulating layer 5 depends on the emitter wiring 2
Since sufficient insulation between the gate electrode 5 and the gate electrode 5 may be maintained, for example, about 0.2 to 2 μm, preferably 0.3 to 0.
7 μm.

The gate electrode 6 is an electrode for concentrating a strong electric field on the emitter 4. As a material for the gate electrode 6, a material having a high melting point from the viewpoint of current resistance and having resistance to an etching solution used for forming an emitter can be used. Preferably, Cr, W, Ta or Nb is used. Can be mentioned. Above all, it is preferable to use Nb from the viewpoint of adhesion to the base.

The thickness of the gate electrode 6 can be appropriately determined as needed, and is set to 0.1 to 0.5 μm.

Further, as shown in FIG.
Between the n-type semiconductor thin film 3a and the n-type semiconductor thin film 3b, ie, p
By interposing a non-doped intrinsic semiconductor layer 3c, particularly a non-doped hydrogenated amorphous silicon thin film layer, on the n-junction surface, the pn-junction characteristics can be further stabilized, and thus better emission characteristics can be obtained.

The non-doped hydrogenated amorphous silicon thin film 3c can be easily obtained by using silane or disilane as a reaction gas when forming a film by PECVD. Here, it is known that a non-doped hydrogenated amorphous silicon thin film usually shows weak n-type conductivity, and the intrinsic semiconductor used in the present invention includes such a non-doped film.

Further, as shown in FIG. 2B, an n-type semiconductor thin film 3d functioning as an ohmic layer is provided at the interface between the emitter wiring layer 2 and the emitter 3 in order to maintain good electrical connection between the two layers. In particular, better emission characteristics can be obtained by interposing an n-type hydrogenated amorphous silicon thin film.

N-type semiconductor thin film 3d as ohmic layer
The thickness (height) of can be appropriately determined as needed, but is preferably 0.01 to 0.2 μm.

<Example 1 of Manufacturing Method> Next, a method of manufacturing a cold electron-emitting device in which a stacked film of a p-type semiconductor thin film and an n-type semiconductor thin film is disposed between an emitter wiring layer and an emitter will be described in detail with reference to FIG. Will be described.

Step (a) First, a metal thin film for an emitter wiring is formed on the insulating substrate 1 and then patterned into a predetermined shape by photolithography to form an emitter wiring layer 2 (see FIG. 3A). ]. In this case, as the emitter wiring layer 2, a Cr film or an Al / Cr laminated film formed by a sputtering method can be preferably used.

Step (b) Next, a p-type semiconductor thin film 3a, for example, a p-type hydrogenated amorphous silicon thin film, is formed on the emitter wiring layer 2, and then an n-type semiconductor thin film 3b is formed on the p-type semiconductor thin film 3a. 3
(See (b)). In this case, the p-type hydrogenated amorphous silicon thin film is formed by PECVD using a mixed gas of silane and diborane as a reactive gas and hydrogen as a diluent gas. As an example of the film forming conditions of such a PECVD method, a total gas flow rate of 540 sccm, a gas pressure of 1 Torr, a substrate temperature of 320 to 340 ° C., and an RF power of 60 W can be shown. The n-type hydrogenated amorphous silicon thin film is formed by PECVD using a mixed gas of silane and phosphine as a reactive gas and hydrogen as a diluent gas. Such a PE
As an example of the film forming conditions of the CVD method, a total gas flow rate of 540 s
ccm, gas pressure 1 Torr, substrate temperature 320 ° C-340
° C, RF power 60W. Furthermore, p
In order to keep the n interface clean, the p-type hydrogenated amorphous silicon layer and the n-type hydrogenated amorphous silicon layer can be formed continuously in separate reaction chambers and by installing a transfer system in a vacuum. preferable.

Step (c) Next, S is deposited on the n-type hydrogenated amorphous silicon thin film layer.
The insulating layer 5 and the gate electrode 6 are formed on the n-type hydrogenated amorphous silicon thin film layer by laminating an insulating material such as iO ₂ and a gate electrode material such as Nb by vapor deposition or the like [FIG. c)]. Here, when the insulating layer 5 is formed by a vapor deposition method, an oxygen gas containing about 10% of ozone is introduced as a reactive gas, and a film is formed using a chimney resistance heating method in which SiO is filled as a vapor deposition material. Is preferred. The insulating layer 5 formed by such a method shows good insulating properties. Further, in the case of this manufacturing method, the same PECVD as the semiconductor thin film is used as the insulating layer 5.
It is possible to use amorphous silicon nitride by the method. In this case, the amorphous silicon nitride is formed by using a mixed gas of silane and ammonia as a reaction gas and hydrogen as a diluting gas. As an example of the film forming conditions of such a PECVD method, a total gas flow rate of 540 sccm, a gas pressure of 1 Torr, a substrate temperature of 320 ° C. to 400 ° C., and an RF power of 60 W can be shown. The insulating layer 5 formed by such a method exhibits particularly good insulating properties.

Step (d) Next, after applying a resist on the insulating layer 5, a resist layer 7 having a circular pattern or a polygonal pattern corresponding to the gate hole is formed by photolithography.

Subsequently, the gate electrode 6 and the insulating layer 5 are etched by RIE with high anisotropy until the n-type semiconductor thin film 3b is exposed (see FIG. 3D). As an example of such RIE conditions, the introduced gas SF6 30 to 70
sccm, RF power of 100 W, and gas pressure of 4.5 Pa.

Step (e) Next, a lift-off material 8 is formed only on the side and upper surfaces of the gate electrode 6 by oblique deposition (see FIG. 3E). As the lift-off material 8, A
1, MgO and the like are preferable.

Step (f) Subsequently, by anisotropic vapor deposition from a direction perpendicular to the substrate,
Film formation is performed until the gate opening is closed. At this time, the emitter 4 is self-aligned at the same time that the gate opening is closed.
Is formed [see FIG. 3 (f)].

Step (g) Further, the lift-off material 8 is removed by wet etching, and at the same time, the emitter material on the gate electrode 6 is removed (see FIG. 3G). Further, if necessary, the gate electrode 6 is patterned into a predetermined shape by using a photolithography method, whereby a cold electron-emitting device can be obtained.

<Example 2 of Manufacturing Method> Next, another method of manufacturing a cold electron-emitting device in which a laminated film of a p-type semiconductor thin film and an n-type semiconductor thin film is arranged between an emitter wiring layer and an emitter is shown in FIG.
Will be described in detail.

Step (h) First, a metal thin film for an emitter wiring is formed on the insulating substrate 1 and then patterned into a predetermined shape by photolithography to form an emitter wiring layer 2 (see FIG. 4 (h)). ]. In this case, as the emitter wiring layer 2, a Cr film or an Al / Cr laminated film formed by a sputtering method can be preferably used.

Step (i) Next, a p-type semiconductor thin film 3a, for example, a p-type hydrogenated amorphous silicon thin film, is formed on the emitter wiring layer 2, and then an n-type semiconductor thin film 3b is formed on the p-type semiconductor thin film 3a. 4
(See (i)). In this case, the p-type hydrogenated amorphous silicon thin film is formed by PECVD using a mixed gas of silane and diborane as a reactive gas and hydrogen as a diluent gas. As an example of such PECVD film forming conditions, a total gas flow rate of 540 sccm and a gas pressure of 1
Torr, substrate temperature 320 ° C to 340 ° C, RF power 6
0W can be indicated. The n-type hydrogenated amorphous silicon thin film is formed by PECVD using a mixed gas of silane and phosphine as a reactive gas and hydrogen as a diluent gas. Such PECV
As an example of the D film formation conditions, the total gas flow rate is 540 sccm,
Gas pressure 1 Torr, substrate temperature 320 ° C to 340 ° C, RF
A power of 60 W can be indicated. Furthermore, in order to keep the pn interface clean, the p-type hydrogenated amorphous silicon layer and the n-type hydrogenated amorphous silicon layer should be formed continuously in separate reaction chambers and in a vacuum in a transfer system. Is more preferred.

Step (j) Next, an etching mask material is formed on the n-type hydrogenated amorphous silicon thin film by a vapor deposition method, a sputtering method, or the like, and is etched by patterning into a circle using a photolithography method. A mask layer 9 is formed (see FIG. 4 (j)).

The etching mask layer 9 is formed from a material having resistance to RIE described later. As such a material, SiO ₂ can be preferably mentioned.

The diameter of the circular pattern is about 1.0 to 3.0 μm in consideration of the characteristics of the cold electron emitting element, the difficulty of operation according to the design rule of the photolithography method, the yield of the etching step, and the like. Is preferred.

Step (k) Next, n is performed by RIE under the condition of a high side etch rate.
The hydrogenated amorphous silicon thin film layer is etched leaving an appropriate thickness. At this time, it is possible to control the shape of the emitter by increasing or decreasing the etching time. For example, when the etching time is shortened, the emitter shape becomes a conical shape, and when the etching time is lengthened, the emitter shape becomes a truncated cone shape. When the shape of the etching mask is not a circle but a polygon, the shape can be a pyramid or a truncated polygon, respectively. Here, it has been confirmed from experiments by the inventor that, for example, a trapezoidal conical shape can obtain more uniform emission characteristics over a large area than a conical shape. Thereby, for example, the emitter 4 having a sharpened tip is formed (see FIG. 4 (k)). As one example of such RIE conditions, O ₂ is added to SF ₆ as an introduced gas.
Can be shown at a flow rate of 30 to 70 sccm, an RF power of 100 W, and a gas pressure of 4.5 Pa.

Step (l) Next, on the surface of the insulating substrate 1 on the emitter wiring layer 2 side,
By laminating an insulating material such as SiO ₂ and a gate electrode material such as Nb by a vapor deposition method or the like, the insulating layer 5 and the gate electrode 6 are formed on the emitter wiring layer 2 and the etching mask pattern layer 9 is formed. Insulating material layer 5a
And a gate electrode material layer 6a (see FIG. 4 (l)). Here, when the insulating layer 5 is formed by a vapor deposition method, an oxygen gas containing about 10% of ozone is introduced as a reactive gas, and a film is formed using a chimney resistance heating method in which SiO is filled as a vapor deposition material. Is preferred. The insulating layer 5 formed by such a method shows good insulating properties.

Step (m) Subsequently, the etching mask layer 9 as a lift-off material is removed by etching using a buffered hydrofluoric acid solution. As a result, the stacked body composed of the insulating material layer 5a and the gate electrode material layer 6a stacked thereon is peeled off. Thus, the emitter 4 is exposed (see FIG. 4 (m)).

Further, if necessary, the gate electrode 5 is patterned into a predetermined shape by using a photolithography method to obtain a cold electron emission element.

As described above, in the cold electron-emitting device of the present invention, the p-electrode is provided between the emitter wiring layer and the emitter.
A stacked film of a type semiconductor thin film and an n-type semiconductor thin film is provided. In other words, the cold electron emission device of the present invention provides a current control function to the emitter itself by forming a pn junction in place of the conventional resistance layer, thereby increasing the local large current without increasing the operating voltage. Current fluctuations can be reduced to a minimum by controlling each element, and the use of a hydrogenated amorphous silicon thin film as a semiconductor thin film for forming such a pn junction provides a low cost and large area. A glass substrate which can be easily formed can be used.

[0080]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a cold electron emitting device according to the present invention will be specifically described below with reference to the drawings.

<Example 1> Step (a) First, Cr as a material of the emitter wiring layer 2 was sputtered to a thickness of about 0.1 μm on a glass substrate 1. continue,
The emitter wiring layer 2 was patterned into a matrix wiring shape by photolithography (FIG. 3A).

Step (b) Next, p-type hydrogenation is performed on the emitter wiring layer 2 by PECVD using a mixed gas of silane, diborane, and hydrogen (addition amount of diborane to silane of 1%) as a reaction gas. After forming an amorphous silicon thin film of 0.3 μm to form a p-type semiconductor thin film 3a, the amorphous silicon thin film is moved to another reaction chamber without being exposed to the atmosphere, and a mixed gas of silane, phosphine, and hydrogen (phosphine to silane) is formed by the same PECVD method. Is added as a reaction gas to form an n-type hydrogenated amorphous silicon thin film layer having a thickness of 0.3 μm.
The semiconductor thin film 3b is shown in FIG. 3 (b).

Step (c) Next, an amorphous silicon nitride film having a thickness of 0.8 μm is formed as the insulating layer 5 by PECVD, and then Nb is formed thereon as a gate electrode material 6 with a thickness of 0.2 μm.
Thickness was sputtered [FIG. 3 (c)].

Step (d) Next, after applying a resist, by photolithography, patterning into a circular mask shape having a diameter of 1.0 μm for a gate hole to form a resist layer 7, and then RIE (introduced gas SF ₆ / The gate electrode material and the insulating layer material were etched at a flow rate of 60 sccm / power of 100 W / gas pressure of 4.5 Pa) for about 5 minutes (FIG. 3D).

Step (e) Next, Al was deposited as a lift-off material 8 to a thickness of 0.3 μm (FIG. 3E).

Step (f) Subsequently, Mo was deposited as a material for the emitter 4 by an anisotropic vapor deposition method from a direction perpendicular to the substrate until the gate hole was closed (FIG. 3F).

Step (g) Next, the lift-off material 8 was wet-etched using an acid-based etchant and peeled off together with the upper layer emitter material to obtain a cold electron-emitting device (FIG. 3 (g)).

An array in which 100 of the above-described cold electron-emitting devices were integrated was prototyped, tested and evaluated as follows. That is,
The distance between the emitter electrode and the gate electrode of each element is about 0.5
A glass plate member having a transparent electrode (anode) coated with a phosphor is opposed at a distance of 30 mm to an element having a structure of μm, and an extraction voltage is applied between the emitter electrode and the gate electrode with a polarity where the gate electrode side is positive. As a result, electrons were successfully and stably emitted.

<Embodiment 2> Another manufacturing example of the cold electron emitting device of the present invention will be specifically described in the following embodiment with reference to FIG.

Step (h) First, Cr was formed as a material for the emitter wiring layer 2 on the glass substrate 1 by sputtering to a thickness of about 0.1 μm. continue,
The emitter wiring layer 2 was patterned into a matrix wiring shape by photolithography [FIG. 4 (h)].

Step (i) Next, p-type hydrogenation is performed on the emitter wiring layer 2 by PECVD using a mixed gas of silane, diborane, and hydrogen (addition amount of diborane to silane of 1%) as a reaction gas. After forming an amorphous silicon thin film of 0.3 μm to form a p-type semiconductor thin film 3a, the amorphous silicon thin film is moved to another reaction chamber without being exposed to the atmosphere, and a mixed gas of silane, phosphine, and hydrogen (phosphine to silane) is formed by the same PECVD method. Is added as a reaction gas, an n-type hydrogenated amorphous silicon thin film is formed to a thickness of 1.1 μm,
An n-type semiconductor thin film 3b and an emitter material were formed [FIG.
(I)].

Step (j) Next, SiO ₂ was applied to a thickness of 0.2 μm by a reactive vacuum deposition method.
Thick film, and then by photolithography,
An etching mask layer 9 was formed by patterning into a circular mask shape having a diameter of 1.2 μm for forming an emitter [FIG. 4 (j)].

Step (k) Next, the n-type hydrogenated amorphous silicon thin film layer 3b was etched by RIE (introduced gas SF ₆ / flow rate ₆₀ sccm / power: 100 W / gas pressure: 4.5 Pa) for 5 minutes [FIG. k)].

Step (l) Next, a silicon oxide film having a thickness of 0.6 μm as the insulating layer 5 (evaporation source: SiO, reactive gas: oxygen and about 10% ozone, evaporation degree of vacuum: 5 × 10 ^-6 Torr) Then, Nb as a gate electrode material was deposited thereon to a thickness of 0.2 μm. Thereby, the insulating layer 4 and the gate electrode 5 located around the emitter 4 could be formed in a self-aligned manner with a small gap from the emitter 4 without contacting the emitter 4 [FIG. (L)].

Step (m) The etching mask layer 9 is lifted off by immersing the material obtained in the step (l) in a buffered hydrofluoric acid solution at room temperature for 2 minutes, and the insulating material layer 5a And the laminated body of the gate electrode material layer 6a peeled off. Thus, the emitter shown in FIG. 4 (m) was obtained. Further, a cold electron-emitting device was obtained by patterning the Nb film of the gate electrode 6 into a matrix wiring shape by photolithography.

An array in which 100 cold electron emitting elements described above were integrated was prototyped, and tested and evaluated as follows. That is,
The distance between the emitter electrode and the gate electrode of each element is about 0.7
A glass plate member having a transparent electrode (anode) coated with a phosphor was placed at a distance of 30 mm from an element having a structure of μm.
When an extraction voltage was applied between the emitter electrode and the gate electrode with a polarity where the gate electrode side was positive, electrons could be emitted satisfactorily and stably.

In the obtained emission characteristics, a current saturation region was obtained in a high electric field region. This is due to the function of the depletion layer generated at the pn junction interface of the semiconductor thin film provided between the emitter wiring layer and the emitter.

Next, the interpretation of the mechanism of emission from a metal emitter, which is an example of the cold electron emitting device of the present invention, will be described. [See Fig. 5]

When the p-type semiconductor P and the n-type semiconductor N are joined, if a strong electric field E is applied to the tip of the metal emitter M in contact with the n-type semiconductor N, the p-type semiconductor P and the n-type semiconductor N The energy state of the junction surface changes, and a depletion layer L is generated. The electrons emitted into the vacuum V are generated by the generation of the electron e-hole h pair in the depletion layer L. Therefore, the emitted electrons are limited by the generation of the electron e-hole h pair, that is, the emission current can be limited.

[0100]

According to the present invention, in the cold electron emission element, a laminated film of a p-type semiconductor thin film and an n-type semiconductor thin film is arranged in this order between the emitter wiring layer and the emitter. That is,
According to the present invention, a current control function is added to the emitter itself by forming a pn junction instead of the conventional resistance layer, and as a result, a large local current can be supplied without increasing the operating voltage. In addition to the suppression, the current fluctuation can be reduced to a minimum by controlling each element.

Further, according to the present invention, such p
By using a hydrogenated amorphous silicon thin film as a semiconductor thin film forming an n-junction, it is possible to use a glass substrate that is easy to increase in area at low cost. That is, when the FEA is applied to a flat display, it can contribute to cost reduction and large area of the flat display.

As described above, according to the present invention, it is possible to obtain a cold electron-emitting device which can operate at a low voltage and has high current stability. At high cost, high quality images on large screens,
It can be obtained with low power consumption.

[Brief description of the drawings]

FIG. 1 is a schematic sectional perspective view of an example of a cold electron emission element according to the present invention.

FIGS. 2A and 2B are schematic cross-sectional perspective views of another example of the cold electron emitting device according to the present invention.

3 (a) to 3 (g) are schematic manufacturing process diagrams of an example of a cold electron emitting device according to the present invention.

4 (h) to (m) are schematic manufacturing process diagrams of another example of the cold electron emitting device according to the present invention.

FIG. 5 is an energy diagram of an emitter of one example of the cold electron emitting device according to the present invention.

FIG. 6 is a schematic sectional perspective view of an example of a conventional cold electron emission element.

FIGS. 7A to 7D are schematic manufacturing process diagrams of an example of a conventional cold electron-emitting device.

FIG. 8 is a schematic manufacturing process diagram of another example of a conventional cold electron-emitting device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Emitter wiring layer 3a ... P-type semiconductor thin film 3b ... N-type semiconductor thin film 3c ... Intrinsic semiconductor layer 3d ... Ohmic layer 4 ... Emitter 5 ... Insulating layer 5a ... Insulating layer material layer 6 ... Gate electrode 6a ... Gate electrode material layer 7 ... Resist layer 8 ... Lift-off material 9 ... Etching Mask layer 61 Insulating substrate 62 Conductive layer 63 Insulating layer 64 Gate electrode 65 Emitter 71 Insulating substrate 72 Conductive layer 73 Insulated Layer 74 Gate electrode 75 Lift-off material 76 Emitter 81 Insulating substrate 82 Conductive layer 83 Resistive layer 84 Insulating layer 85 Gate electrode 86 ... Emitter A ... Opening P ... p Semiconductor N · · · · n-type semiconductor M · · · · metal emitter V · · · · vacuum e · · · · electron h · · · · hole L · · · · depletion

Claims (17)

[Claims] An emitter wiring layer, an insulating layer, and a gate electrode are sequentially stacked on an insulating substrate, and an opening reaching the emitter wiring layer is provided between the gate electrode and the insulating layer. A field emission type cold electron emission element formed such that an emitter does not come into contact with the gate electrode on the emitter wiring layer, wherein at least p is provided between the emitter wiring layer and the emitter.
A cold electron emission element, wherein a type semiconductor thin film and an n-type semiconductor thin film are stacked in this order, and the emitter is formed on the n-type semiconductor thin film. 2. The cold electron-emitting device according to claim 1, wherein the p-type semiconductor thin film is a p-type hydrogenated amorphous silicon thin film, and the n-type semiconductor thin film is an n-type hydrogenated amorphous silicon thin film. 3. The p-type hydrogenated amorphous silicon thin film comprises:
Boron is a dopant, and the boron doping amount is 100 p
a hydrogenated amorphous silicon thin film in the range of pm to 10%, and the n-type hydrogenated amorphous silicon thin film has phosphorus as a dopant and a phosphorus doping amount of 10 ppm to 10%.
3. The cold electron-emitting device according to claim 1, wherein the cold electron-emitting device is a hydrogenated amorphous silicon thin film in the range of: 4. The p-type semiconductor thin film has a thickness of 0.05 μm to 1 μm.
2. The cold electron emission device according to claim 1, wherein the thickness of the n-type semiconductor thin film is in a range of 0.05 μm to 1 μm. 5. The cold electron-emitting device according to claim 1, wherein the p-type semiconductor thin film and the n-type semiconductor thin film are formed with an intrinsic semiconductor thin film interposed therebetween. 6. The cold electron-emitting device according to claim 5, wherein the intrinsic semiconductor thin film is a non-doped hydrogenated amorphous silicon thin film. 7. The cold electron emitting element according to claim 1, wherein the emitter wiring layer and the p-type semiconductor thin film are formed with an n-type semiconductor thin film as an ohmic layer interposed therebetween. 8. An n-type semiconductor thin film as an ohmic layer,
The cold electron emitting device according to claim 7, wherein the cold electron emitting device is an n-type hydrogenated amorphous silicon thin film. 9. The cold electron-emitting device according to claim 1, wherein the insulating layer comprises an amorphous silicon nitride film. 10. The cold electron emitting device according to claim 1, wherein the shape of the emitter is one of a cone, a cylinder, a truncated cone, and a truncated polygon. 11. The cold electron-emitting device according to claim 1, wherein the emitter is made of n-type hydrogenated amorphous silicon. 12. The cold electron-emitting device according to claim 1, wherein a glass substrate is used as the insulating substrate. 13. An emitter wiring layer, an insulating layer and a gate electrode are sequentially laminated on an insulating substrate, and the gate electrode and the insulating layer are provided with an opening reaching the emitter wiring layer.
A field emission type cold electron emitting element in which an emitter is formed on the emitter wiring layer in the opening so as not to contact the gate electrode, wherein at least p is provided between the emitter wiring layer and the emitter. A method of manufacturing a cold electron-emitting device, characterized in that a type semiconductor thin film and an n-type semiconductor thin film are stacked in this order, and an emitter is formed on the n-type semiconductor thin film. Forming a metal thin film for forming an emitter wiring on a substrate and forming an emitter wiring layer by patterning; (b) forming a p-type semiconductor thin film on the emitter wiring layer, and further forming a p-type semiconductor thin film on the p-type semiconductor thin film (C) forming a layer made of an insulating material on the n-type semiconductor thin film and further forming a layer made of a gate electrode material thereon; (d) That side A photoresist is applied to the substrate, and a photoresist is formed on the etching mask layer having a hole having a shape and a size corresponding to the opening of the gate by using a photolithography method, and thereafter, the gate electrode is formed by reactive ion etching. Forming a gate electrode and an insulating layer by exposing the layer of the material and the insulating material to form the gate hole where the n-type semiconductor thin film is exposed; (e) forming the gate electrode using an oblique deposition method; Forming a lift-off layer by vapor-depositing a lift-off material only on the upper surface and side surfaces of the substrate; (f) anisotropic vapor deposition having a large amount of vapor-deposited anisotropy in the vertical direction from the direction perpendicular to the substrate By depositing an emitter material in the gate hole using a method,
(G) a step of forming an emitter in a self-aligned manner; and (g) a step of lifting off an emitter material on an upper side or a side of the gate electrode; Method. 14. In the step (c), the insulating material layer is made of amorphous silicon nitride, and the insulating material layer is made of PE using a mixed gas of either silane or disilane and ammonia as a reaction gas.
14. The manufacturing method according to claim 13, wherein the manufacturing method is performed by a CVD method. 15. An emitter wiring layer, an insulating layer and a gate electrode are sequentially laminated on an insulating substrate, and the gate electrode and the insulating layer are provided with an opening reaching the emitter wiring layer,
A field emission type cold electron emitting element in which an emitter is formed on the emitter wiring layer in the opening so as not to contact the gate electrode, wherein at least p is provided between the emitter wiring layer and the emitter. A method of manufacturing a cold electron-emitting device, characterized in that a semiconductor thin film and an n-type semiconductor thin film are stacked in this order, and an emitter is formed on the n-type semiconductor thin film. Forming a metal thin film for forming an emitter wiring on a substrate and forming an emitter wiring layer by patterning; (i) forming a p-type semiconductor thin film on the emitter wiring layer; (J) forming an etching mask material on the n-type semiconductor thin film and opening the gate of the etching mask material film by photolithography. Forming an etching mask layer in which a portion having the shape and size corresponding to the portion remains; (k) etching the n-type semiconductor thin film using reactive ion etching until the n-type semiconductor thin film remains. (L) stacking a layer made of an insulating material and a layer made of a gate electrode material in this order on the surface side of the n-type semiconductor thin film of the insulating substrate, thereby forming an insulating material layer on the n-type semiconductor thin film; Forming a gate electrode material layer; and (m) removing the etching mask layer;
A step of lifting off the insulating material layer and the gate electrode material layer thereover. A manufacturing method comprising any of the above (h) to (m). 16. The method according to claim 13, wherein the p-type semiconductor thin film is a hydrogenated amorphous silicon thin film, which is formed by combining either silane or disilane with diborane. Using a mixed gas consisting of nitrogen as a reaction gas
The n-type semiconductor thin film is a hydrogenated amorphous silicon thin film, which is formed by a PECVD method using a mixed gas of either silane or disilane and phosphine as a reaction gas. Claim 1
16. The production method according to any one of items 3 and 15. 17. The gas flow ratio of diborane to either silane or disilane is in the range of 100 ppm to 10%, and the gas flow ratio of phosphine to either silane or disilane is in the range of 10 ppm to 10%. The method according to claim 16.