JPH1083508A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make clock signals to be supplied one system. SOLUTION: Reproduced RF signals are subjected to frequency conversions by multipliers 13, 14 after passing a prefilter consisting of a low-pass filter 11 of 900kHz and a high-pass filter 12 of 420kHz. Here, since a component of 465kHz is multiplied by a clock signal of 421.875kHz to be produced by frequency-dividing an external clock of 13.5MHz with a 1/2 frequency divider 22 and a 1/16 frequency divider 21, the component is converted into a component of 43.1kHz being the difference between the two signals. Similarly, a component of 697.5kHz is converted into a component of 146.3kHz by being multiplied by a clock of 843.75kHz to be produced by frequency-dividing the external clock with the 1/16 frequency divider 21. Moreover, these frequency components are pulled out in band-pass filters 15, 16 of a next stage and are detected in detectors 17, 18 to be taken out as a detected output after being added in an adder 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus suitable for detecting, for example, a reproduced ATF signal of a VTR.

[0002]

2. Description of the Related Art In the case of detecting a weak signal in a narrow band, such as the detection of a reproduced ATF signal in a VTR, the following two techniques are generally used. Using a switched capacitor filter (SCF) to reduce the variation in the center frequency of the filter. Using a frequency conversion circuit, the target frequency component is low-frequency converted. As a result, the Q of the band limiting filter can be reduced, the number of circuit elements can be reduced, and the stability of the circuit can be improved.

[0003]

However, in this device, the SCF and the frequency conversion circuit need to supply different clock signals, respectively, and this has caused the following problems. Since two different clocks are required, the system becomes complicated, for example, having two crystal oscillators. It has been difficult to cope with a case where a "shift" occurs in the target frequency, such as during variable speed reproduction of a VTR.

The present invention has been made in view of the above points, and the problem to be solved is that in the conventional apparatus, it is necessary to supply different clock signals to the SCF and the frequency conversion circuit. Therefore, there are problems that the system becomes complicated and it is difficult to cope with the "shift" of the frequency.

[0005]

According to the present invention, a signal obtained by arbitrarily dividing a clock signal supplied to a switched capacitor filter is supplied to a multiplier of a frequency conversion circuit. According to this, a single clock signal can be supplied, the system can be simplified, and it is possible to easily cope with a frequency shift.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS That is, in the present invention, a band limiting filter using a switched capacitor filter,
In a signal processing device having a detector and a frequency conversion circuit by multiplication, a signal obtained by arbitrarily dividing a clock signal supplied to a switched capacitor filter is supplied to a multiplier of the frequency conversion circuit.

FIG. 1 is a block diagram of a VTR to which a signal processing apparatus according to the present invention is applied.
FIG. 3 is a block diagram showing an example of the configuration. In FIG. 1, a tape 1 is run by a capstan motor 2 and a drum 3 is rotated by a drum motor 4. Then, the reproduced RF signal picked up by the rotating head on the drum 3 is amplified through a reproducing amplifier 5 and supplied to a reproduced signal processing circuit 6 and a detection circuit 7 including a signal processing circuit according to the present invention.

On the other hand, the clock generation circuit 8 forms various clocks on the basis of the reproduction signal from the reproduction signal processing circuit 6, for example, and supplies the generated clock to necessary parts. Further, the control circuit 9 performs a tracking operation by servo-controlling the capstan motor 2 and the drum motor 4 and controlling the phase of the capstan motor 2 according to the output of the detection circuit 7. Then, the reproduction signal processing circuit 6 demodulates the reproduction signal to obtain a video signal, an audio signal, and the like, and outputs the signal to the outside.

FIG. 2 shows details of the detection circuit 7 including the above-described signal processing circuit according to the present invention. Although specific numerical values are shown in FIG. 2 for ease of explanation, the present invention is not limited to these numerical values.

In FIG. 2, in this example, the frequency components (pilot signals) to be extracted are two of 465 kHz and 697.5 kHz in the reproduced RF signal. Therefore, these signals pass through a pre-filter including a low-pass filter (LPF) 11 of 900 kHz and a high-pass filter (HPF) 12 of 420 kHz, and are frequency-converted by multipliers 13 and 14.

As shown in FIG. 3, the 465 kHz component reduces 13.5 MHz supplied from outside by 1/16
Divided by the divider 21 and the 1/2 divider 22, 4
Multiplied by a 21.875 kHz clock signal, 43.1 kHz which is the difference between the two frequencies
Converted to components.

Similarly, the 697.5 kHz component is 1/1
The signal is multiplied by a 843.75 kHz clock signal generated by dividing the frequency by the 6 frequency divider 21 to obtain 146.3 kHz.
Converted to z component. Further, these frequency components are extracted by band-pass filters (BPF) 15 and 16 at the next stage, detected by detectors 17 and 18, added by an adder 19, and extracted as a detection output.

In this circuit, a low-pass filter (LPF) 11 and a high-pass filter (HPF) 12
And bandpass filters (BPF) 15 and 16 are formed using switched capacitor filters (SCF), respectively, and these filters each have 13.5 MHz.
Clock signal is supplied.

In the above-mentioned circuit, an arbitrary value can be generally selected for the frequency of the clock for frequency conversion as long as the following conditions are satisfied. Condition 1: next bandpass filter (BPF) 15, 1
6. The difference from the frequency component is small so that 6 can be easily designed.

Therefore, the clock frequency of the switched capacitor filter is not an integer ratio, and for simplicity it is 2 times.
It is relatively easy to find a frequency that satisfies the above condition 1 from frequencies divided by a power of ratio. That is, in the present invention, the present invention is not limited to the above-described example, but holds in a more general case.

Further, the frequency conversion shown in FIG. 3 satisfies another important condition described below. Condition 2: The conversion frequency is outside the frequency to be extracted.

That is, in general, in frequency conversion by multiplication, as shown in FIG. 4, for example, not only a frequency component to be extracted but also a component at a position symmetrical with respect to the conversion frequency is converted into the same frequency as "return". This is called an image frequency and degrades S / N after frequency conversion. Note that, in the example of FIG.
The 0 kHz component corresponds to this.

If the frequency relationship satisfies the above condition 2, the image frequency component can be easily removed by the pre-filter constituted by the low-pass filter (LPF) 11 and the high-pass filter (HPF) 12. , S / N can be converted without deteriorating the S / N ratio.

Therefore, in this device, the clock signal supplied to the switched capacitor filter is arbitrarily divided and supplied to the multiplier of the frequency conversion circuit, whereby the supplied clock signal can be made into one system. , The system can be simplified.

Further, in the above-mentioned apparatus, the relative speed between the drum and the tape changes during variable speed reproduction, so that the pilot signal also changes.

Therefore, this change is set to + 1%. When the clock is supplied from the crystal. When only the clock of the switched capacitor filter is a clock synchronized with the reproduced signal, the clock of the switched capacitor filter and the clock of the frequency conversion are synchronized with the reproduced signal. (In the present invention), each band-pass filter (BPF) 1
The characteristics of No. 6 are as shown in FIG.

Therefore, when the present invention is applied, the characteristics of the filter follow the frequency of the pilot component, and a desired output is obtained.

The above-described apparatus can be applied to, for example, systems having different rotation speeds.

That is, the above-described systems shown in FIGS. 1 and 2 are based on the assumption that the rotation speed of the drum is 9000 rpm. On the other hand, for example, a system in which the number of heads is increased and two tracks are simultaneously read to reduce the number of rotations of the drum to half (4500 rpm) is considered. In such a system, the frequency of the pilot component is halved, so that the center frequency of the filter and the like are different, and another circuit must be prepared in the conventional configuration.

In this case, according to the present invention described above, all frequency relations are reduced to ２ by simply dividing the supplied clock by 周, so that it is possible to cope easily. That is, as shown in FIG. 6, for example, by adding a 分 frequency divider 31 at a stage prior to the clock input of the IC 30 constituting the detection circuit 7, the rotation speed of the drum is reduced to half (4500
rpm) can be implemented using the same IC 30.

Alternatively, as shown in FIG. 7, a 1/2 frequency divider 32 and a selector 33 are provided inside an IC 30 and
The selector 33 may be switched by the select terminal SEL. This also makes the circuit common and IC
It is possible to realize a device that can form a circuit that is advantageous in terms of integration and that can more easily cope with a plurality of systems.

According to the above-described signal processing device, in the signal processing device having the band-limiting filter using the switched capacitor filter, the detector, and the frequency conversion circuit based on the multiplication, the clock signal supplied to the switched capacitor filter is arbitrarily divided. By supplying the multiplied signal to the multiplier of the frequency conversion circuit, the supplied clock signal can be made into one system, which simplifies the system and easily copes with the frequency shift. Can be done.

[0028]

According to the present invention, the clock signal supplied to the switched capacitor filter is arbitrarily divided and supplied to the multiplier of the frequency conversion circuit so that the supplied clock signal becomes one system. And the system can be simplified.

According to this apparatus, for example, at the time of variable speed reproduction, even when the relative speed between the drum and the tape changes and the pilot signal also changes, the characteristics of the filter follow the frequency of the pilot component. And a desired output can be obtained.

Further, according to this apparatus, the circuit can be shared and the circuit can be advantageously integrated into a system in which the number of heads is increased and two tracks are read at the same time to reduce the number of rotations of the drum to half (4500 rpm). A circuit can be formed, and an apparatus which can more easily cope with a plurality of systems can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an example of a VTR to which the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of an example of a signal processing device according to the present invention.

FIG. 3 is a diagram for explaining the operation.

FIG. 4 is a diagram for explaining the operation.

FIG. 5 is a diagram for explaining the operation.

FIG. 6 is a block diagram showing a configuration of another example of the signal processing device according to the present invention.

FIG. 7 is a block diagram showing a configuration of another example of the signal processing device according to the present invention.

[Explanation of symbols]

11 Low-pass filter (LPF), 12 High-pass filter (HPF), 13, 14 Multiplier, 15, 16
Bandpass filter (BPF), 17, 18 detector, 1
9 adder, 21 1/16 frequency divider, 22 1/2 frequency divider

Claims (1)

[Claims] 1. A signal processing apparatus having a band-limiting filter using a switched capacitor filter, a detector, and a frequency conversion circuit based on multiplication, wherein a signal obtained by arbitrarily dividing a clock signal supplied to the switched capacitor filter is subjected to the frequency conversion. A signal processing device for supplying a signal to a multiplier of a circuit.