JPH1079332A - Method and apparatus for producing pattern layout for integrated circuit and method for forming circuit pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method wherein a cell library with proximity effects evaluated can be produced before determining a manufacturing process and one cell of the cell library can be used in a general-purpose semiconductor integrated circuit under general-purpose manufacturing process conditions. SOLUTION: A proximity effect influence amount evaluating part 12 evaluates an influence amount of proximity effects under virtual process conditions, while a proximity effect influence amount converting part 16 evaluates an influence amount of proximity effects under actual process conditions, and obtains correlation between the influence amount of proximity effects under the virtual process conditions and the influence amount of proximity effects under the actual process conditions before converting virtual proximity effect information based on the correlation, so that it is applicable to the actual process conditions. A pattern size correcting part 17 corrects a pattern size with actual proximity effect information converted to be fitted to the actual process conditions reflected on design data. A cell library placing part 18 produces a layout of a corrected circuit pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for generating a pattern layout of circuit elements in a cell which is a component of a semiconductor integrated circuit such as an LSI and a method for forming a circuit pattern.

[0002]

2. Description of the Related Art In recent years, miniaturization of semiconductor integrated circuits represented by LSIs has been further advanced, and the miniaturization is approaching a processing limit. Accordingly, in the lithography process, which is one of the LSI manufacturing processes, the difference between the design dimension and the processing dimension due to the proximity effect cannot be ignored, so when designing each cell that is an individual unit of the pattern layout,
It is necessary to perform a pattern design in which a dimensional variation due to the proximity effect is corrected to a target pattern size.

Conventionally, a pattern dimension has been adjusted at the time of designing each cell in accordance with a specific manufacturing process, thereby correcting a dimension variation. However, the increase in the scale of the LSI increases the period from the design of each cell to the manufacture of the LSI. During that period, it is necessary to frequently change the manufacturing process due to various factors. In order to obtain an economical effect by reusing the same as a library for various LSIs, it has become necessary to use a common cell for a plurality of manufacturing processes.

Accordingly, in the fine pattern forming method for performing pattern design by performing correction in accordance with a specific manufacturing process, the performance in design can be realized, and economical effects can be obtained by reusing general-purpose cells. It's also getting harder to get.

Hereinafter, a conventional method and apparatus for generating a pattern layout for an LSI circuit will be described with reference to the drawings.

FIG. 14 is a block diagram showing a conventional pattern layout generator for LSI circuits. In FIG. 14, the generation apparatus inputs a pattern input unit 101 for inputting design data including circuit elements constituting a cell, and converts the input design data of the cell into a library in a cell library 105 as cell library data. A cell library generation unit 102; a proximity effect evaluation unit 103 that evaluates the influence amount of the proximity effect due to miniaturization before generating the cell library; and a pattern size in which the influence amount of the proximity effect is reflected in the design data. Dimension correction unit 104 that corrects
And a cell library copy creation unit 106 for extracting and copying desired cell library data from the cell library 105, and a cell for arranging the extracted and copied cell library data to generate LSI layout data 108. A library arrangement unit 107.

The operation of the pattern layout generating apparatus for an LSI circuit configured as described above will be described.

First, from the pattern input unit 101, a pattern of the transistor unit and a pattern layout corresponding to the connection information of the transistor unit are input according to a predetermined design rule from the circuit diagram, and the cell library generation unit 102 receives the input pattern. Layout to Cell Library 10
5 is generated. At this time, the pattern of each layer composed of the gate layer and the active layer has a mixture of dense and sparse patterns in the arrangement state. For example, if a normal exposure process using light is used in a lithography process, Due to the effect, a dense pattern becomes thinner than a design pattern, and a sparse pattern becomes thicker than a design pattern.

As a result, for example, in the gate layer, there is a difference between the design dimension of the gate width and the gate length and the processing dimension, and the dimensional difference may exceed the allowable range for defining the performance in design. Therefore, the proximity effect evaluation unit 103 evaluates in advance the difference between the design size and the processing size due to the proximity effect of the process conditions used in the manufacturing process, and the pattern size correction unit 104 applies the size difference to each pattern. Is corrected. The pattern layout corrected and generated by the influence of the proximity effect is registered as the cell library 105. As a method of evaluating the proximity effect, a method of performing prediction using a high-performance simulator adapted to the conditions of the experiment and the like are employed.

Next, the cell library copy creation section 106
After extracting and copying the cell library data necessary to create an LSI from the cell library 105, the cell library arranging unit 107 generates LSI layout data in accordance with the cell library data.

A fine pattern of an LSI is formed by using a mask device created based on the LSI layout data created as described above.

[0012]

However, the conventional method for generating a pattern layout for an LSI circuit has a problem that the proximity effect cannot be corrected for process conditions other than those assumed at the time of design. Have. For example, under the process conditions of normal exposure using light, a sparse pattern becomes thicker and a dense pattern becomes thinner,
Even with exposure using the same light, the exposure method using a ring filter called super-resolution may make sparse patterns thin and dense patterns thick, and the correction will have the opposite effect. There is also.

Further, since the conventional pattern layout generating method is designed in accordance with a specific manufacturing process condition, the generated cell library cannot be used for other process conditions. Therefore, there is a problem that the effect of reducing the design cost of the LSI cannot be obtained by reusing it for a plurality of LSIs by corresponding to a plurality of manufacturing conditions.

As shown in FIG. 15, as a simple improvement, a proximity effect evaluation section 103 and a pattern size correction section 104 are provided.
May be changed between the process of the cell library copy creation unit 106 and the process of the cell library arrangement unit 107.

However, in a normal LSI design, the period for preparing the cell library 105 is several months to several tens of months, but the period for preparing the LSI layout data 108 from the cell library 105 is several weeks. From dozens of weeks. Since the cell library 105 is versatile, development can be performed without specifying an LSI to be actually created.
To create the SI layout data 108, the LSI must be specified. This is because the shorter the period from when the LSI to be developed to when the actual LSI is manufactured, the higher the development efficiency.

Therefore, from the viewpoint of LSI development efficiency,
LSI layout data 1 as shown in the above improvement example
Immediately before the creation of the 08, it is not possible to provide the proximity effect evaluation unit 103 for evaluating the influence amount of the proximity effect by the simulator which requires an enormous processing time.

Further, even if the same cell library is used, if the conditions of the manufacturing process are different, there is also a problem that a simulator which requires a long processing time for the cell library data must be executed again.

In view of the above problems, the present invention can create a cell library in which the proximity effect has been evaluated before the manufacturing process is determined, and can prepare one cell of the cell library for general-purpose manufacturing. It is intended to be usable for general-purpose semiconductor integrated circuits under process conditions.

[0019]

In order to achieve the above object, the present invention seeks a correlation between the amount of influence of the proximity effect of virtual process conditions and the amount of influence of the proximity effect of actual process conditions. Here, the dimensions of the circuit pattern are corrected based on the correlation.

Specifically, a solution taken by the invention of claim 1 is an integrated circuit pattern layout generating method for generating a layout of a circuit pattern in which circuit elements are arranged in a cell which is a component of the integrated circuit. A virtual proximity effect evaluation step of setting a virtual process condition in a circuit pattern generation step as a target, and evaluating an influence amount of a virtual proximity effect which is a proximity effect of the circuit pattern in the virtual process condition; A real proximity effect evaluation step of evaluating the amount of influence of the real proximity effect, which is the proximity effect of the circuit pattern when the process conditions described above are applied; and a correlation between the amount of influence of the virtual proximity effect and the amount of influence of the real proximity effect. A correlation creation step of obtaining a relationship; and a pattern dimension correction for correcting a pattern dimension of the circuit pattern based on the correlation to generate a layout of the circuit pattern. It is an arrangement and a degree.

According to the first aspect of the present invention, the influence of the virtual proximity effect, which is the proximity effect of the circuit pattern under virtual process conditions, is evaluated, and the influence of the actual proximity effect, which is the proximity effect of the circuit pattern under actual process conditions, is evaluated. In order to generate the layout of the circuit pattern by correcting the amount of the virtual proximity effect and calculating the correlation between the amount of influence of the virtual proximity effect and the amount of influence of the real proximity effect, and correcting the dimensions of the circuit pattern based on the correlation, The influence amount of the proximity effect can be simulated without being limited to a specific process condition.

According to a second aspect of the present invention, there is provided an integrated circuit pattern layout generating method for generating a layout of a circuit pattern in which circuit elements are arranged in a cell which is a component of an integrated circuit. A virtual proximity effect evaluation step of setting a virtual process condition in the circuit pattern generation step and evaluating an influence amount of a virtual proximity effect that is a proximity effect of the circuit pattern in the virtual process condition; A cell library generation step of generating a cell library by adding virtual proximity effect information reflecting the influence amount of the virtual proximity effect, and real proximity which is a proximity effect of the circuit pattern when an actual process condition is applied. A real proximity effect evaluation step of evaluating the amount of influence of the effect; and a phase for determining a correlation between the amount of influence of the virtual proximity effect and the amount of influence of the real proximity effect. A relationship creation step, a proximity effect information conversion step of converting the virtual proximity effect information in the cell library into real proximity effect information of the actual process condition based on the correlation, and based on the real proximity effect information. A pattern dimension correcting step of generating a layout of the circuit pattern by correcting the pattern dimension of the circuit pattern.

According to the second aspect of the present invention, the influence of the virtual proximity effect, which is the proximity effect of the circuit pattern under virtual process conditions, is evaluated, and the influence of the virtual proximity effect is reflected on the circuit pattern. Since a cell library to which information is added is generated, the cell library is not limited to a specific process condition, so that the cell library can be generalized.

Further, a correlation between the amount of influence of the virtual proximity effect and the amount of influence of the real proximity effect is obtained, and based on the correlation, the virtual proximity effect information in the cell library is obtained based on the actual proximity effect of the actual process condition. Since the layout is generated by correcting the pattern size of the circuit pattern by converting the information into information, it is not necessary to evaluate the influence of the proximity effect of the actual process condition after determining the actual process condition.

According to a third aspect of the present invention, in the invention of the second aspect, the virtual proximity effect evaluation step and the real proximity effect evaluation step use the light intensity of the circuit pattern by light intensity simulation based on optical theory. This is to add a configuration including a step of evaluating the amount of influence of the proximity effect.

According to a fourth aspect of the present invention, there is provided a pattern layout generating apparatus for an integrated circuit for generating a layout of a circuit pattern in which circuit elements are arranged in a cell which is a component of the integrated circuit. Virtual proximity effect evaluation means for setting a virtual process condition in a circuit pattern generation step, and evaluating an influence amount of a virtual proximity effect which is a proximity effect of the circuit pattern in the virtual process condition; A cell library generating means for generating a cell library by adding virtual proximity effect information reflecting the influence amount of the virtual proximity effect, and real proximity which is a proximity effect of the circuit pattern when an actual process condition is applied. A real proximity effect evaluation means for evaluating the influence amount of the effect; and a phase for obtaining a correlation between the influence amount of the virtual proximity effect and the influence amount of the real proximity effect. A relationship creating unit, a proximity effect information converting unit that converts the virtual proximity effect information in the cell library into real proximity effect information of the actual process condition based on the correlation, and based on the real proximity effect information. And a pattern dimension correcting means for correcting a pattern dimension of the circuit pattern to generate a layout of the circuit pattern.

According to the fourth aspect of the present invention, the influence of the virtual proximity effect, which is the proximity effect of the circuit pattern under virtual process conditions, is evaluated, and the effect of the virtual proximity effect is reflected in the circuit pattern. Since a cell library to which information is added is generated, the cell library is not limited to a specific process condition, so that the cell library can be generalized.

Further, a correlation between the influence amount of the virtual proximity effect and the influence amount of the real proximity effect is obtained in advance, and based on the correlation, the virtual proximity effect information in the cell library is converted into the real proximity effect of the actual process condition. Since the layout is generated by correcting the pattern size of the circuit pattern by converting the information into information, it is not necessary to evaluate the influence of the proximity effect of the actual process condition after the actual process condition is determined.

According to a fifth aspect of the present invention, in the invention of the fourth aspect, the virtual proximity effect evaluation means and the real proximity effect evaluation means use the light intensity of the circuit pattern obtained by light intensity simulation based on optical theory. A configuration for evaluating the influence amount of the proximity effect is added.

In a sixth aspect of the present invention, there is provided a circuit pattern forming method, wherein a virtual process condition is set in a circuit pattern generation step, and a proximity effect of the circuit pattern under the virtual process condition is used. A virtual proximity effect evaluation step of evaluating an influence amount of a certain virtual proximity effect, and a cell library generation step of adding a virtual proximity effect information reflecting the influence amount of the virtual proximity effect to the circuit pattern to generate a cell library And an actual proximity effect evaluation step of evaluating an influence amount of a real proximity effect which is a proximity effect of the circuit pattern when an actual process condition is applied; and an influence amount of the virtual proximity effect and an influence amount of the real proximity effect. A correlation creating step of determining a correlation with the virtual proximity effect information in the cell library based on the correlation. Generating a pattern layout for an integrated circuit, comprising: a proximity effect information conversion step of converting the information into effect information; and a pattern dimension correction step of generating a circuit pattern layout by correcting a pattern dimension of the circuit pattern based on the actual proximity effect information. A mask device manufacturing step of manufacturing a mask device having a mask pattern formed using the pattern layout data created by the method, and transferring the pattern layout to a substrate by exposing the substrate to exposure light transmitted through the mask device. And a pattern layout transfer step.

In a seventh aspect of the present invention, a circuit pattern forming apparatus sets a virtual process condition in a circuit pattern generation step, and uses a proximity effect of the circuit pattern under the virtual process condition. Virtual proximity effect evaluation means for evaluating the influence amount of a certain virtual proximity effect, and cell library generation means for generating a cell library by adding virtual proximity effect information reflecting the influence amount of the virtual proximity effect to the circuit pattern Real proximity effect evaluation means for evaluating the influence amount of the real proximity effect, which is the proximity effect of the circuit pattern when an actual process condition is applied, and the influence amount of the virtual proximity effect and the influence amount of the real proximity effect Correlation creation means for determining a correlation with the virtual proximity effect information in the cell library based on the correlation. Pattern layout generation for an integrated circuit, comprising: proximity effect information conversion means for converting to effect information; and pattern dimension correction means for generating a circuit pattern layout by correcting the pattern size of the circuit pattern based on the actual proximity effect information. A mask device manufacturing step of manufacturing a mask device having a mask pattern formed using pattern layout data created by the device, and transferring the pattern layout to a substrate by exposing the substrate to exposure light transmitted through the mask device. And a pattern layout transfer step.

[0032]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a pattern layout generating apparatus for an integrated circuit according to an embodiment of the present invention. In FIG. 1, the present generation device includes a pattern input unit 11
A proximity effect influence amount evaluation unit 12, a cell library generation unit 13, a cell library copy creation unit 15, a proximity effect influence amount conversion unit 16, a pattern size correction unit 17, and a cell library placement unit 18 And

The pattern input section 11 inputs design data including circuit elements constituting a cell. The proximity effect influence amount evaluation unit 12 has virtual proximity effect evaluation means for setting virtual process conditions and evaluating the influence amount of the proximity effect due to miniaturization of the virtual process conditions. The cell library generating unit 13 converts the input design data of the cell into a cell layout including the pattern layout reflecting the influence of the proximity effect and cell library data including the virtual proximity effect information in the cell library 14. It has generating means. The cell library copy creation unit 15 extracts and copies desired cell library data from the cell library 14. Proximity effect influence amount conversion unit 16
Calculates the actual proximity effect evaluation means for evaluating the influence amount of the proximity effect of the actual process condition and the correlation between the influence amount of the proximity effect of the virtual process condition and the influence amount of the proximity effect of the actual process condition There is provided a correlation creating means, and proximity information converting means for converting the virtual proximity effect information copied based on the correlation so as to conform to actual process conditions. The pattern dimension correcting section 17 has a pattern dimension correcting means for correcting the pattern dimension by reflecting the actual proximity effect information converted so as to conform to the actual process conditions in the design data. The cell library arranging unit 18 arranges the corrected cell library data to generate LSI layout data 19.

Hereinafter, the operation of the pattern layout generating apparatus for an integrated circuit configured as described above will be described with reference to the drawings.

FIG. 2 is a flowchart showing the operation procedure of the integrated circuit pattern layout generating apparatus according to one embodiment of the present invention.

First, in a pattern input step S1 shown in FIG. 2, the pattern input section 11 represents an electronic circuit based on a predetermined dimensional rule, and inputs a pattern of a cell which is a basic element of an LSI pattern layout out. Thus, the pattern layout shown in FIG. FIG. 3A is a plan view of a transistor portion of the electronic circuit,
2, 23, and 24 are gate portions of transistors, 25A and 2
5B is the active region of the transistor and 26A, 26B, 2
6C represents an electrode of the transistor. Hereinafter, in the present embodiment, as shown in FIG. 3B, the description will be limited to the gate portions 21, 22, 23, and 24 of the pattern layout.

Next, the virtual proximity effect evaluation step S shown in FIG.
In 2, the proximity effect influence amount evaluation unit 12 sets a certain virtual process condition, quantifies the influence amount of the proximity effect on the pattern in the cell under the virtual process condition, and uses the additional information of each pattern. Created as certain virtual proximity effect information.

Here, a method for quantifying the proximity effect will be described. The following two methods can be considered as methods for quantifying the proximity effect by simulation.

(1) A method of directly evaluating the finished dimensions of each pattern in the lithography process (2) In order to indirectly obtain the finished dimensions of each pattern in the lithography process by a simple function using the shape of the pattern or the exposure condition as a variable To evaluate the parameters of

Since the method (1) directly evaluates the finished dimensions in the lithography process, it is accurate for quantifying the amount of influence of the proximity effect, but the amount of influence of the proximity effect under virtual process conditions is different from the actual amount. When the correlation between the influence amounts of the proximity effect in the process is created, there is a possibility that a good correlation cannot be obtained between the finished dimension in the virtual process and the finished dimension in the actual process. For example, when there is a many-to-one correlation. Therefore, when creating a correlation between the amount of influence of the proximity effect and the amount of influence of the proximity effect in the actual process, a better correlation is obtained between the relationship between the actual process conditions expected in advance and the layout to be created. It is better to determine the parameters to be used and to adopt the method of expressing the influence of the proximity effect using the parameters as described in (2) above.

Hereinafter, a method for quantifying the influence of the proximity effect using the relative light intensity obtained by the simulation as a parameter will be described.

As a virtual process condition, a wavelength of 365 n
Exposure by light using the light of m is set, and parameters of the exposing machine are set as shown below.

Numerical aperture: 0.6 Interference degree: 0.6 Defocus: 0.0 μm Ring filter: None Under these conditions, the finished dimension of a line pattern whose pattern dimension is 0.4 μm is the center of each line pattern. FIG. 4 shows values obtained in various appropriate layouts using the light intensity in the section as a parameter. As shown in FIG. 4, the finished dimension W due to the proximity effect is represented by the following relational expression (1) using the relative light intensity E as a parameter: W = 0.445-1.68E (1). The relational expression (1) does not depend on each gate portion of the layout shown in FIG. 3, but generally holds under the above exposure conditions, and can be obtained without specifying the layout. As a result, the proximity effect at each gate can be quantified by the relative light intensity E at each gate. The relative light intensity E at each gate is obtained by light intensity simulation in the actual layout of each gate.

In the present embodiment, the light intensity at the respective central portions 21a, 22a, 23a, 24a of the gate portions 21, 22, 23, 24 shown in FIG. 3B was evaluated using a light intensity simulator. The value was adopted.

Here, the relative light intensity is defined as a value standardized so that the intensity when the entire surface of the pattern is exposed becomes 1.

Next, in the cell library generation step S3 shown in FIG. 2, the cell library generation unit 13 performs, for example, the pattern layout shown in FIG. 3B and the proximity effect influence amount of each pattern shown in FIG. 3 (b), the central portions 21a, 22a,
The information is registered and stored in the cell library 14 as additional information including virtual proximity effect information representing the light intensity at 23a and 24a.

Next, the manufacturing process determining step S shown in FIG.
4, after the number of cell libraries necessary for manufacturing a desired LSI is accumulated, the LS actually manufactured is
Define I and determine its manufacturing process.

Next, in the correlation creating step S5 shown in FIG. 2, the influence amount of the proximity effect of the actual process conditions determined in the previous manufacturing process determining step S4 and the virtual amount set at the time of designing each cell. The correlation between the process condition and the influence amount of the proximity effect is obtained.

In this embodiment, the correlation between the relative light intensity under virtual process conditions and the relative light intensity under actual process conditions is determined. Also, in the actual process conditions, it is necessary to create a relational expression for obtaining the finished dimension W using the relative light intensity E as a parameter, as in the case of the virtual process conditions.

First, in an actual process, a relational expression for obtaining a finished dimension using the relative light intensity E as a parameter is obtained. As the actual process conditions, the setting conditions of the super-resolution process using the annular filter are used as shown below.

Numerical aperture: 0.6 Interference degree: 0.6 Defocus: 0.0 μm Ring filter: Non-transmissive part corresponding to 80% of the light source radius Under these conditions, a line pattern having a pattern design dimension of 0.4 μm FIG. 6 shows the finished dimensions obtained in various suitable layouts using the light intensity at the center of each line pattern as a parameter. As shown in FIG. 6, the finished dimension W due to the proximity effect is represented by the following relational expression (2) using the relative light intensity E as a parameter: W = 0.449-2.197E (2). This relational expression (2) also does not depend on each gate portion of each layout shown in FIG. 3, but generally holds under the above exposure conditions, and can be obtained without specifying a layout. it can. Next, the correlation between the relative light intensity at the center of the 0.4 μm line pattern under virtual process conditions and the relative light intensity at the center of the 0.4 μm line pattern in the actual process is determined. Specifically, in an appropriate layout pattern whose design dimension is a 0.4 μm line pattern, the relative light intensity in a virtual process and the relative light intensity in an actual process are obtained, and as shown in FIG. The layouts can be created by performing statistical processing on a plurality of layouts with the same layout, the relative light intensity under virtual process conditions on the horizontal axis, and the relative light intensity under actual process conditions on the vertical axis.

Thus, a conversion formula representing a relative light intensity conversion curve for converting the relative light intensity E under the virtual process condition into the light intensity E1 under the actual process condition, E1 = 0.8 × 10 ^-2 -4. 626E + 1.55 × 10 ⁻³ × E ² −1.442 × 10 ⁻⁵ × E ³ + 5.965 × 10 ⁻⁶ × E ⁴ −9.356 × 10 ⁻⁷ × E ⁵ (3) it can.

The relational expression (3) does not depend on each gate portion of the layout of FIG. 3 but must be obtained without depending on the layout if the virtual process conditions and the actual process conditions are determined. Can be.

Accordingly, for a plurality of conditions used in the actual process, a relative light intensity conversion formula (3) for converting the relative light intensity of the virtual process condition into the relative light intensity of the actual process condition is prepared. If the light intensity simulation is performed only once on the pattern layout under virtual process conditions, the relative light intensity conversion formula ( By converting the relative light intensity based on 3), the light intensity under actual process conditions can be obtained.

That is, as shown in FIG. 8, when information independent of the manufacturing process is determined (pattern layout in this embodiment), evaluation of physical quantities (light intensity in this embodiment) under virtual process conditions is performed. If you do
The physical quantity of the actual process condition different from the virtual process condition can be evaluated by a simple calculation by considering the correlation between the virtual process and the actual process.

Next, the proximity effect information conversion step S shown in FIG.
6, the cell library copy creation unit 15
Library 1 for synthesis of pattern layout
After extracting each cell from No. 4 and generating a copy thereof, the proximity effect influence quantity conversion unit 16 converts the virtual proximity effect information, which is additional information of each pattern in the copied cell, into a relative light intensity conversion formula (3). Is converted into actual proximity effect information that matches the corresponding actual process condition based on the correlation shown in FIG.

Thus, a virtual process is set at the time of design, and the cell library data generated by evaluating the influence of the proximity effect on the virtual process condition is stored in the cell pattern layout. This means that the relative light intensity under the actual process conditions was obtained without performing the relative light intensity simulation again. For example, the copy of the cell library data shown in FIG. 5 is converted into the cell library data shown in FIG. 9 by the relative light intensity conversion formula (3).

Next, a pattern dimension correcting step S7 shown in FIG.
, The pattern dimension correction unit 17 performs dimension correction suitable for the manufacturing process condition on each cell library data based on the amount of influence of the proximity effect of the actual process condition of each pattern, that is, the actual proximity effect information. This dimensional correction is performed based on the relative proximity intensity information of the cell library data obtained by converting the relative light intensity shown in FIG. 9 into the relational expression (2) between the light intensity and the finished size of the gate length under the actual process conditions. It is obtained by substituting the light intensity. Therefore, the deviation amount between the finished size and the design size may be corrected as the pattern size.

Next, in the cell library arranging step S8 shown in FIG. 2, the cell library arranging section arranges the pattern layout of each cell whose size has been corrected in the previous pattern dimensional correcting step S7, and The pattern layout data 19 is created. Next, the pattern layout based on the pattern layout data corrected for the proximity effect suitable for the actual process conditions is transferred to a transparent substrate using chrome or the like that does not transmit exposure light, thereby achieving LS.
A mask device for manufacturing I is manufactured.

Using this mask device, a pattern layout is transferred to a substrate by exposure light transmitted through the mask device to form a fine pattern. Thereby, it is possible to form a fine pattern in which the difference between the design dimension and the finished dimension falls within an allowable range.

As described above, according to the present embodiment, a virtual process is assumed without determining a correction dimension at the time of pattern design, and the effect of the proximity effect of the virtual process condition on each pattern in the cell. The amount is evaluated, the influence amount is obtained as additional information of each pattern, and the additional information and the pattern layout constitute a cell library. Further, when the actual process conditions are determined, a correlation is used that maps the proximity effect influence amount of the virtual process condition to the proximity effect influence amount of the actual process condition. By converting the additional information without directly re-evaluating the effect amount of the effect, the effect of each pattern due to the proximity effect suitable for the actual process conditions can be easily evaluated. Dimension correction can be performed.

Hereinafter, a first modification of the embodiment of the present invention will be described with reference to the drawings.

In the above-described embodiment, as an example of quantifying the influence of the proximity effect of the pattern layout shown in FIG. 3B, the quantification can be performed using the light intensity at a point inside the pattern. In the modification, the same FIG.
This shows that the pattern layout shown in (b) is also effective in cases other than the case of changing from a virtual process to a super-resolution process.

That is, the defocus of the exposure device is set to 0.5
An example will be described.

Numerical aperture: 0.6 Interference degree: 0.6 Defocus: 0.5 Ring filter: None As shown in FIG. 10, under this process condition, a gate length of 0.4 μm in pattern design dimension was finished. The relationship between the size and the relative light intensity at the center of the gate portion is as follows: the amount of influence of the proximity effect, that is, the finished size W with respect to the design size depends on the light intensity E: W = 0.507-0.871E (4) It is quantified by the following relational expression (4).

Next, the influence amount of the proximity effect between the defocus process condition and the virtual process condition has a correlation shown in FIG. 11, and specifically, the light intensity E2 under the defocus process condition is virtually E2 = 0.125-17.974E + 3.399 × 10 ⁻³ × E ² −2.561 × 10 ⁻⁵ × E ³ + 8.813 × 10 ⁻⁶ × E ⁴ by using the light intensity E under various process conditions. .. (5) can be easily converted.

Hereinafter, a second modification of the embodiment of the present invention will be described with reference to the drawings.

In the first embodiment and the first modification, a pattern layout in which simple lines are arranged is used as a target layout pattern. In the second modification, the influence of the proximity effect is quantified. It is explained that it can be applied to complicated layout patterns by changing the definition of.

For example, in the pattern layout shown in FIG. 12, the sparse / dense relationship between the pattern 27 and other patterns on the periphery of the pattern 27 varies depending on the position of the pattern 27. In such a case, a light intensity distribution on the center line 27a of the pattern 27 may be used as a parameter for quantifying the influence amount of the proximity effect of the pattern layout.

That is, the light intensity distribution on the center line 27a of the pattern 27 under virtual process conditions is as shown by a relative light intensity curve 31 shown in FIG. Also, pattern 27
Has a distribution as shown in a finished dimension curve 32 shown in FIG. 13 in the y-axis direction. here,
The finished line width and the relative light intensity shown in FIG. 13 have a relationship that the finished line width increases as the relative light intensity decreases, and the finished size and the light intensity at the center of the pattern shown in FIG. Is substantially the same as the relational expression (1) evaluated under virtual process conditions.

Therefore, by converting the light intensity distribution under the virtual process conditions into the light intensity distribution under the actual process conditions, the line width distribution of the pattern 27 under the actual process conditions can be evaluated. According to this method, the present invention can be applied to a complicated shape in which all the pattern layouts are not arranged in parallel.

Also, in the case shown in FIG. 12, if the pattern is divided in advance at the position where the density of the pattern changes in the y-axis direction, the quantification of the influence amount of the proximity effect can be performed at the center of the pattern. Since the operation can be performed with light intensity, the data amount of cell library data can be reduced.

Conventionally, when the proximity effect correction is performed on the pattern layout of the cell library, the pattern layout differs from the pattern realized on the wafer in the actual manufacturing process. In some cases, the inconsistency occurred when applying. However, according to the embodiment of the present invention, since the pattern layout in the cell library matches the layout realized in the actual manufacturing process, processing by various design tools other than the proximity effect correction is performed on the cell library. It is convenient when performing.

[0075]

According to the method of generating a pattern layout for an integrated circuit according to the first aspect of the present invention, it is possible to simulate the influence of the proximity effect without being limited to a specific process condition. Since it is possible to design a general-purpose library from an early stage before the determination is made, the period from when the semiconductor integrated circuit to be actually manufactured and the manufacturing process conditions are determined to when the semiconductor integrated circuit is started to be manufactured is shortened. be able to.

According to the method for generating a pattern layout for an integrated circuit according to the second aspect or the pattern layout generating apparatus for an integrated circuit according to the fourth aspect, the present invention is not limited to a specific process condition, so that the cell library can be generalized. Further, it is possible to shorten the period from when the semiconductor integrated circuit to be actually manufactured and the manufacturing process conditions are determined to when the manufacture of the semiconductor integrated circuit is started.

Further, since it is not necessary to evaluate the influence of the proximity effect of the actual process condition after the actual process condition is determined, the proximity effect cannot be obtained when the cell library is reused for many semiconductor integrated circuits. The time required for the correction process can be reduced.

According to a third aspect of the present invention, there is provided an integrated circuit pattern layout generating method and an integrated circuit pattern layout generating apparatus. In addition to the effect of the generator, the influence of the proximity effect is evaluated using the light intensity of the circuit pattern based on the light intensity simulation based on the optical theory, so that the influence of the proximity effect can be reliably evaluated. .

According to the circuit pattern forming method of claim 6 or 7, the circuit pattern is formed by using the pattern layout data generated by the integrated circuit pattern layout generating method of claim 2 or the integrated circuit pattern layout generating apparatus of claim 4. Since the exposure is performed by the mask device having the mask pattern thus formed, it is possible to form a fine pattern in which a difference between a design dimension and a finished dimension falls within an allowable range.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an integrated circuit pattern layout generating apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation procedure of the integrated circuit pattern layout generation device according to the embodiment of the present invention;

FIG. 3 shows a pattern layout of the integrated circuit in the integrated circuit pattern layout generation device according to one embodiment of the present invention, and FIG.
(B) is a diagram showing a gate portion of the transistor portion.

FIG. 4 is a graph showing the relationship between the relative light intensity and the finished line width under virtual process conditions in the integrated circuit pattern layout generation method according to one embodiment of the present invention.

FIG. 5 is a diagram showing virtual proximity effect information of cell library data in a method for generating a pattern layout for an integrated circuit according to an embodiment of the present invention.

FIG. 6 is a graph showing the relationship between the relative light intensity under actual process conditions and the finished line width in the pattern layout generating method for an integrated circuit according to one embodiment of the present invention.

FIG. 7 is a graph showing a correlation between the influence amount of the proximity effect of the virtual process condition and the influence amount of the proximity effect of the actual process condition in the pattern layout generating method for an integrated circuit according to the embodiment of the present invention; It is.

FIG. 8 is a diagram illustrating a relationship between physical quantities of virtual process conditions and physical quantities of actual process conditions according to an embodiment of the present invention.

FIG. 9 is a diagram showing actual proximity effect information in the pattern layout generation method for an integrated circuit according to an embodiment of the present invention.

FIG. 10 is a graph showing the relationship between the relative light intensity under actual process conditions and the finished line width in the integrated circuit pattern layout generation method according to the first modification of the embodiment of the present invention.

FIG. 11 is a diagram illustrating a correlation between an influence amount of a proximity effect of a virtual process condition and an influence amount of a proximity effect of an actual process condition in a pattern layout generation method for an integrated circuit according to a first modification of the embodiment of the present invention; It is a graph showing a relationship.

FIG. 12 is a diagram illustrating a pattern layout of an integrated circuit in a method for generating a pattern layout for an integrated circuit according to a second modification of the embodiment of the present invention;

FIG. 13 is a graph showing the relationship between the relative light intensity under virtual process conditions and the finished dimensions in the integrated circuit pattern layout generation method according to the second modification of the embodiment of the present invention.

FIG. 14 is a block diagram showing a conventional pattern layout generating apparatus for an LSI circuit.

FIG. 15 is a block diagram showing a conventional pattern layout generating apparatus for an improved LSI circuit.

[Description of Signs] 11 Pattern input unit 12 Proximity effect influence amount evaluation unit 13 Cell library generation unit 14 Cell library 15 Cell library copy creation unit 16 Proximity effect influence amount conversion unit 17 Pattern dimension correction unit 18 Cell library arrangement Part 19 LSI layout data S1 Pattern input step S2 Virtual proximity effect evaluation step S3 Cell library generation step S4 Manufacturing process determination step S5 Correlation creation step S6 Proximity effect information conversion step S7 Pattern dimension correction step S8 Cell library placement step 21 Gate part 21a Central part 22 Gate part 22a Central part 23 Gate part 23a Central part 24 Gate part 24a Central part 25A Active region 25B Active region 26A Electrode 26B Electrode 26C Electrode 27 Pattern 27a Center line 31 Relative light intensity curve 32 Finish Size curve

Claims (7)

[Claims] An integrated circuit pattern layout generating method for generating a layout of a circuit pattern in which circuit elements are arranged in a cell which is a component of an integrated circuit, wherein a virtual process is performed in the circuit pattern generating step. A virtual proximity effect evaluation step of setting conditions and evaluating an influence amount of a virtual proximity effect that is a proximity effect of the circuit pattern under the virtual process condition; and a proximity of the circuit pattern when an actual process condition is applied. A real proximity effect evaluation step of evaluating the influence amount of the real proximity effect, which is an effect; a correlation creation step of obtaining a correlation between the influence amount of the virtual proximity effect and the influence amount of the real proximity effect; A pattern dimension correction step of correcting a pattern dimension of the circuit pattern based on the pattern pattern based on the pattern pattern and generating a layout of the circuit pattern. Use pattern layout generation method. 2. A pattern layout generating method for an integrated circuit for generating a layout of a circuit pattern in which circuit elements are arranged in a cell which is a component of the integrated circuit, wherein a virtual process is performed in the step of generating the circuit pattern. A virtual proximity effect evaluation step of setting a condition and evaluating an influence amount of a virtual proximity effect which is a proximity effect of the circuit pattern under the virtual process condition; and reflecting the influence amount of the virtual proximity effect on the circuit pattern. A cell library generation step of generating a cell library by adding virtual proximity effect information; and a real proximity effect for evaluating the influence amount of the real proximity effect, which is the proximity effect of the circuit pattern when actual process conditions are applied. An evaluation step, a correlation creation step of determining a correlation between the influence amount of the virtual proximity effect and the influence amount of the real proximity effect, A proximity effect information conversion step of converting the virtual proximity effect information in the cell library into actual proximity effect information of the actual process condition, and correcting a pattern dimension of the circuit pattern based on the actual proximity effect information. A pattern dimension correcting step of generating a circuit pattern layout by using the method. 3. The virtual proximity effect evaluation step and the real proximity effect evaluation step each include a step of evaluating an influence amount of the proximity effect using light intensity of the circuit pattern by light intensity simulation based on optical theory. The method according to claim 1 or 2, wherein the pattern layout is generated for an integrated circuit. 4. A pattern layout generating apparatus for an integrated circuit, which generates a layout of a circuit pattern in which circuit elements are arranged in a cell which is a component of the integrated circuit, wherein a virtual process is performed in a step of generating the circuit pattern. Virtual proximity effect evaluation means for setting a condition and evaluating an influence amount of a virtual proximity effect which is a proximity effect of the circuit pattern under the virtual process condition; and reflecting the influence amount of the virtual proximity effect on the circuit pattern. A cell library generating means for generating a cell library by adding virtual proximity effect information; and a real proximity effect for evaluating an influence amount of the real proximity effect which is a proximity effect of the circuit pattern when an actual process condition is applied. Evaluation means; correlation creation means for determining a correlation between the influence amount of the virtual proximity effect and the influence amount of the real proximity effect; A proximity effect information converting means for converting the virtual proximity effect information in the cell library into actual proximity effect information of the actual process condition, and correcting a pattern dimension of the circuit pattern based on the actual proximity effect information. And a pattern dimension correcting means for generating a layout of a circuit pattern. 5. The virtual proximity effect evaluation means and the real proximity effect evaluation means evaluate the amount of influence of the proximity effect using light intensity of the circuit pattern by light intensity simulation based on optical theory. The integrated circuit pattern layout generating apparatus according to claim 4. 6. A virtual proximity effect evaluation step of setting a virtual process condition in a circuit pattern generation step and evaluating an influence amount of a virtual proximity effect which is a proximity effect of the circuit pattern in the virtual process condition. A cell library generating step of generating a cell library by adding virtual proximity effect information reflecting the influence amount of the virtual proximity effect to the circuit pattern; and a proximity of the circuit pattern when an actual process condition is applied. An actual proximity effect evaluation step of evaluating the influence amount of the real proximity effect, which is an effect, a correlation creation step of finding a correlation between the influence amount of the virtual proximity effect and the influence amount of the real proximity effect, A proximity effect information conversion step of converting the virtual proximity effect information in the cell library into actual proximity effect information of the actual process condition based on the actual proximity effect; Mask pattern formed using the pattern layout data generation method for the integrated circuit, including a pattern dimension correction step of correcting a pattern dimension of the circuit pattern based on the result information to generate a layout of the circuit pattern. A circuit comprising: a mask device manufacturing step of manufacturing a mask device having a pattern; and a pattern layout transfer step of transferring the pattern layout to a substrate by exposing to light by exposure light transmitted through the mask device. Pattern formation method. 7. A virtual proximity effect evaluation means for setting a virtual process condition in a circuit pattern generation step and evaluating an influence amount of a virtual proximity effect as a proximity effect of the circuit pattern under the virtual process condition. A cell library generating means for generating a cell library by adding virtual proximity effect information reflecting the amount of influence of the virtual proximity effect to the circuit pattern; and a proximity of the circuit pattern when an actual process condition is applied. Real proximity effect evaluation means for evaluating the influence amount of the real proximity effect as an effect, correlation creation means for obtaining a correlation between the influence amount of the virtual proximity effect and the influence amount of the real proximity effect, A proximity effect information conversion means for converting the virtual proximity effect information in the cell library into actual proximity effect information of the actual process condition based on the actual proximity effect; Formed using a pattern layout data created by an integrated circuit pattern layout generating apparatus having pattern size correcting means for correcting a pattern size of the circuit pattern based on the result information and generating a circuit pattern layout. A circuit comprising: a mask device manufacturing step of manufacturing a mask device having a pattern; and a pattern layout transfer step of transferring the pattern layout to a substrate by exposing the pattern layout to a substrate by exposing the mask layout to exposure light transmitted through the mask device. Pattern formation method.