JPH1074063A - Driving circuit of display device, d/a converter and array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the driving circuit of a display device in which the integration is easily conducted without requiring large area thin film transistors. SOLUTION: A periodically varying voltage is applied to an analog voltage input line 13. Comparison data, which have a prescribed corresponding relationship with respect to the value of the voltage and vary in synchronism with the voltage, are successively inputted to comparison data input line 11. A comparator 12 compares the display data held in a second display data holding means 10 with the successively inputted comparison data and controls the opening and the closing of switching means 14 and 15 between the line 13 and a signal line 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a display device, and more particularly to a driving circuit for a matrix type display device.

The present invention also relates to a D / A converter, and more particularly to a D / A converter for converting digital data into an analog voltage and outputting the same.
/ A converter.

The present invention further relates to an array substrate of a display device, and more particularly to an array substrate of a display device in which drive electrodes of display pixels are formed in a matrix.

[0004]

2. Description of the Related Art A display device represented by a liquid crystal display device is:
It is used in various fields such as televisions, computer displays, portable information terminals, and the like, and liquid crystal display devices are particularly attracting attention because of their features of light weight, thinness, and low power consumption.

In recent years, in order to further reduce the size and cost of a liquid crystal display device, attempts have been made to integrate a driving circuit on a transparent substrate on which electrodes of display pixels are formed. In order to integrate a driver circuit, a high-performance thin film transistor is required. Therefore, a TFT (ThinF) using polysilicon (non-single-crystal crystalline silicon) is generally used.
ilm Transistor: a thin film transistor) is used. 900-1000 ° C for polysilicon TFT
Because it needs to be formed by a high-temperature manufacturing process
A quartz substrate that can withstand high temperatures is used as the transparent substrate.
However, since a quartz substrate is expensive, research and development of a technology for forming a polysilicon TFT by a manufacturing process at 500 to 600 ° C. in which an alkali-free glass substrate can be used is being advanced.

Attempts have also been made to form an amorphous silicon TFT circuit using amorphous silicon TFTs used for pixels of conventional liquid crystal display devices.

The driving circuit includes a so-called signal line driving circuit for sequentially supplying video signals to switching elements such as thin film transistors connected to each pixel of a pixel array arranged in a matrix. There is a so-called scan line driver circuit which sequentially drives gates of switching elements such as thin film transistors.

When a voltage is applied to the gates of the thin film transistors in a predetermined column by the scanning line driving circuit, the drain
The sources are electrically connected, and the video signal supplied from the signal line driving circuit is written to each liquid crystal pixel in a predetermined column. By performing this operation sequentially for each column, a predetermined signal is written to all the liquid crystal pixels, and an image is displayed.

Normally, a signal line driving circuit includes a shift register array and a sample circuit controlled by the output of each shift register.
It is constituted by an AND-hold circuit. sample·
The AND-hold circuit samples and holds the video signal input from the common video signal input line with the output of the shift register, that is, the shift pulse, and supplies it to each signal line. The display screen is driven from left to right or right to left according to the connection direction of the columns.

However, in the case of the signal line driving circuit configured as described above, there is a problem that a high-speed sample and hold circuit is required.

For example, in the case of a computer display device having 640 pixels in the horizontal direction and 480 pixels in the vertical direction, the sampling time per signal line is about 40 ns. Normally, the parasitic capacitance of a signal line of a liquid crystal display device is several pF to several hundred pF. To charge a predetermined voltage to this signal line, the ON resistance and the wiring resistance of the sampling transistor must be several Ω to several KΩ. It must be:

However, even in the case of high-performance polysilicon TF #, there is a problem that an extremely large area is required to obtain such an on-resistance.

Further, there is a problem that a high-speed buffer amplifier is required to drive the sampling transistor, and the area of this portion becomes large. It is uneconomical to form a large-area sampling transistor, and the output voltage error due to the parasitic capacitance between the gate electrode and the source electrode and between the gate electrode and the drain electrode increases. Can not. For this reason, measures such as extending the sampling time by dividing the display screen and driving the display screen in parallel have been considered. However, there is a problem that a circuit or the like for externally dividing the video signal is required. .

On the other hand, the liquid crystal display device is required to have higher definition, but in order to achieve higher definition, it is necessary to cope with a video signal having a wide frequency band, and the sampling time is further shortened. Become. For this reason, there is a problem that a more sophisticated sampling transistor and a video signal dividing circuit having a large number of divisions are required.

In the case of a drive circuit using a sample-and-hold circuit, there is a problem that if the ON resistance of the sampling transistor varies, the variation directly changes the frequency characteristics of the drive circuit.

In the conventional liquid crystal display device in which the driving circuits are integrated as described above, a high-performance sampling transistor having a large area and small variation is required, and an external video signal dividing circuit is required. There is.

[0017]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. That is, an object of the present invention is to provide a driving circuit of a display device which can be easily integrated. Another object of the present invention is to provide a driving circuit of a display device which can be easily integrated without requiring a large-area thin film transistor.

It is another object of the present invention to provide a driving circuit of a display device which can be integrated without depending on variations in transistor characteristics.

Another object of the present invention is to form a driving circuit of a display device which does not require an external video signal dividing circuit.

Another object of the present invention is to provide a D / A converter capable of converting digital data into an analog voltage having a stable and small variation. Another object of the present invention is to provide a D / A converter applicable to a driving circuit of a display device. It is a further object of the present invention to provide an array substrate in which a pixel array and a compactly integrated drive circuit are integrally formed.

[0021]

According to the present invention, there is provided a driving circuit for a display device, comprising: voltage applying means for applying a periodically changing analog voltage; and a signal line connected to the voltage applying means via a switch means. Comparison data input means for inputting comparison data whose value corresponds to the analog voltage and changes in synchronization with the analog voltage, display data holding means for holding the input display data, and the comparison data input means And control means for controlling connection and disconnection of the switch means by comparing the comparison data input to the display data with the display data held in the display data holding means.

The display data holding means includes a display data input means, and a first display data holding means which samples and holds a plurality of bits of display data sequentially input to the display data input means at a predetermined timing in a horizontal scanning period. And a second display data holding means for sampling the display data held in the first display data holding means at a predetermined timing of a horizontal blanking period and holding it until the next horizontal blanking period. You may do so.

According to the present invention, there is provided a driving circuit for a display device, comprising: voltage applying means for applying a periodically changing analog voltage; a signal line connected to the voltage applying means via a switch means; Comparison data input means for inputting comparison data corresponding to a voltage and changing in synchronization with the analog voltage; address data input means for inputting address data; predetermined address data connected to the address data input means; A display data input unit to which display data is input; a display data holding unit that samples and holds the display data by the gate signal from the display data input unit; Comparison data input to the input means and display data held in the display data holding means; Compared to, characterized by comprising a control means for controlling the cutoff and connection of the switching means.

The same data may be used for all bits or some bits of the comparison data and the address data. In addition, for example, all or some of the bit lines of the comparison data input line and all or some of the bit lines of the address data input line may be shared.

The driving circuit of the display device according to the present invention comprises: a voltage application means for applying a periodically changing analog voltage; a signal line connected to the voltage application means via a switch means; Comparison data input means for inputting comparison data corresponding to a voltage and changing in synchronization with the analog voltage, a shift register connected in series, display data input means for inputting display data, and the display data input means A display data holding unit that samples and holds the display data by an output of the shift register, and compares the comparison data input to the comparison data input unit with the display data held by the display data holding unit. And a control means for controlling connection and disconnection of the switch means.

[0026] The control means may connect the switch means when the comparison data and the display data match.

The control means may connect the switch means when the comparison data is smaller than the display data, and cut off the switch means when the comparison data is greater than or equal to the display data. Good.

The control means includes a digital comparator for comparing the magnitude of the comparison data input to the comparison data input means with the display data held in the display data holding means, and the switch means includes a digital comparator for comparing the digital data with the display data held in the display data holding means. It may be constituted by a thin film transistor which is opened and closed by an output.

The control means may use a flip-flop which is set by a set signal and connects the switch means, and which is reset when the comparison data and the display data coincide with each other to shut off the switch means. It may be. When the display device is, for example, a liquid crystal display device, the analog voltage applied by the voltage applying unit is applied in correspondence with the comparison data so as to correct the γ characteristic of the liquid crystal display device. Is also good.

Further, in the drive circuit of the display device of the present invention, a voltage applying means to which a periodically changing analog voltage is inputted, a signal line connected to the voltage applying means, and a plurality of bits of display data are inputted. Display data input means, comparison data input means to which comparison data of the same bit as the display data is input, and display data sequentially input to the display data input means are sampled at a predetermined timing in one horizontal scanning period. First data holding means for holding data;
A second data holding unit that samples the display data held in the first data holding unit during a horizontal blanking period and holds the display data until the next horizontal blanking period; and a second data holding unit that holds the display data until the next horizontal blanking period. A comparison unit for comparing the magnitude of the display data with comparison data input from the comparison data input unit, and opened / closed by an output of the comparison unit interposed between the voltage application unit and a signal line; Switching means may be provided.

The drive circuit of the display device according to the present invention is characterized in that the first display data holding means samples and holds a plurality of bits of display data sequentially input from the display data input means at a predetermined timing in one horizontal scanning period. And a second display data holding unit that samples display data held in the first data holding unit during the horizontal blanking period and holds the sampled data until the next horizontal blanking period. A comparing means for comparing the held display data with a plurality of bits of comparison data input from the comparison data input means; and a flip set by a signal from the set input means and reset by a signal from the comparator Switching controlled by the output of the flip-flop interposed between the flop and the voltage applying means and the signal line It may be and a stage.

The comparison data input means has a plurality of bits of digital data which rise or fall sequentially during one horizontal scanning period.
Data may be inputted, and an analog voltage which rises or falls sequentially in synchronization with the digital data applied to the comparison data input means may be applied to the voltage applying means. As described above, the voltage value input from the voltage applying means may be set so that the display characteristics of the display device are corrected with respect to the digital data value input from the comparison data input means. .

According to the D / A converter of the present invention, there is provided a voltage applying means to which the first digital data and the periodically changing analog voltage are applied, the value of which corresponds to the analog voltage and the value of the analog voltage. The second that changes synchronously
Digital data, the first digital data and the second digital data.
Output means for comparing the digital data with the first digital data and outputting an analog voltage corresponding to the first digital data. The D / A converter of the present invention may further comprise a first transmission line through which the first digital data is transmitted, a voltage application unit to which a periodically changing analog voltage is input, and the voltage through a switch unit. An output terminal connected to the application means, and a second terminal whose value corresponds to the analog voltage and changes in synchronization with the analog voltage.
A second transmission path for transmitting digital data of
Data holding means for sampling and holding the first digital data from the transmission line at a predetermined timing;
Comparing means for comparing the magnitude of the second digital data input to the transmission line with the first digital data held in the data holding means, and connecting and disconnecting the switch means by the output of the comparing means. Control means for controlling may be provided.

The output means of the D / A converter of the present invention compares the first digital data with the second digital data and determines whether the first digital data and the second digital data match. May be output.

The output means of the D / A converter of the present invention outputs the analog voltage when the second digital data is smaller than the first digital data, and outputs the second digital data when the second digital data is smaller than the first digital data. When the value is greater than or equal to the data, the output of the analog voltage may be stopped.

The array substrate of the present invention is the first substrate of an insulating substrate.
A display pixel array formed in a matrix in a region of
A scanning line for driving the pixel array in row units, a signal line for applying a display signal to the pixel array in column units, and a period formed in a second region surrounding the first region of the insulating substrate. Voltage applying means for applying a periodically changing analog voltage, the signal line connected to the voltage applying means and the switch means, and a value corresponding to the analog voltage and changing in synchronization with the analog voltage. Comparison data input means for inputting comparison data to be input, display data holding means for holding input display data, comparison data input to the comparison data input means, and display data held by the display data holding means. And control means for controlling connection and disconnection of the switch means.

Further, the array substrate of the present invention comprises a display pixel array having a first thin film transistor formed in a matrix on a first region of an insulating substrate and using polycrystalline silicon as an active layer; A scanning line that is driven in units of rows, a signal line that applies a display signal to the pixel array in units of columns, and a second region that surrounds a first region of the insulating substrate, and is formed based on display data. A second thin film transistor using the polycrystalline silicon as an active layer for driving a signal line, further comprising voltage applying means for applying a periodically changing analog voltage, and a voltage applying means connected to the voltage applying means via a switch means And a comparison data input for inputting comparison data whose value corresponds to the analog voltage and changes in synchronization with the analog voltage. Means, display data holding means for holding the input display data, and comparing the comparison data input to the comparison data input means with the display data held in the display data holding means, An array substrate, comprising: a signal line drive circuit including control means for controlling connection and disconnection.

That is, the drive circuit of the display device of the present invention converts the first digital data, which is the display data, into a display signal and applies it to the signal line of the display device. A method of applying an analog voltage corresponding to display data to a signal line by comparing display data with comparison data using comparison data which is second digital data whose value changes in synchronization with the analog voltage. It is. That is, by using the comparison data which is digital data interlocked with the applied analog voltage, the display data and the comparison data can be compared, and an analog voltage corresponding to the display data can be output.

For example, if the voltage application means and the signal line are connected when the comparison data and the display data match, a voltage corresponding to the display data is applied to the signal line as a display signal. Also, for example, when the sequentially increasing comparison data is smaller than the display data, the voltage application unit and the signal line are connected, and when the comparison data matches the display data or when the comparison data is larger than the display data, the voltage application unit is connected. The connection with the signal line may be cut off.

The relationship between the voltage applied to the voltage applying means and the comparison data may be set as required.
For example, increase / decrease of voltage value and increase / decrease of comparison data value
The reduction may be set exactly the same or similar. For example, during one horizontal scanning period, the comparison data input line has a multi-bit digital
Data may be input, and a voltage that sequentially increases may be input to the analog voltage input line in synchronization with the data.

The increase / decrease of the voltage value and the increase / decrease of the value of the comparison data may be set so as to correct the characteristics of the display device such as the γ characteristic. That is,
The applied voltage and the comparison data may be changed synchronously with a predetermined correspondence.

Here, a flow until display data is output to a signal line as a display signal voltage will be described. Here, one signal line among a number of signal lines for driving display pixels arranged in a matrix will be described.

The display data, which is the first digital data sequentially input to the display data input means such as the display data input line, is sampled at a predetermined timing and held in the display data holding means. The display data holding means may be configured in a plurality of stages. For example, a first data holding unit that samples and holds a plurality of bits of display data sequentially input from the display data holding unit such as a display data input line at a predetermined timing, and a first data holding unit. The data held by the holding means may be sampled at a predetermined timing and held by a second data holding means. Then, for example, display data is sampled at a predetermined timing within the horizontal scanning period from the display data input means to the first display data holding means, and the display data is sampled from the first display data holding means to the second display data holding means. The display data may be sampled at a predetermined timing in the horizontal blanking period. A plurality of bits of display data sequentially input from the display data input unit are sampled and held at a predetermined timing of one horizontal scanning period by the first data holding unit, and the display data is horizontally stored by the second data holding unit. It is sampled during the blanking period and held until the next horizontal blanking period. As such display data holding means, for example, a data latch may be used.

The timing for sampling the display data from the display data input means is determined by, for example, providing an address data input means such as an address data input line for inputting address data, and a signal line connected to the data holding means to the address data input means. A gate corresponding to the address to which it belongs may be connected, and the display data may be sampled from the display data input means by the output of the gate. For example, a predetermined AND gate may be connected to the address data input line, and the output of the AND gate may be connected to the control input of the data latch.

Also, for example, an address data input line and an
Instead of the D gate, a shift register whose output is connected to the control input of the data latch may be connected in series in the address direction of the signal line. The shift pulse input may be connected to the shift pulse output of the shift register having the address n-1, and the shift pulse output may be connected to the shift pulse input of the shift register having the address n + 1.

Further, the first display data holding means is used to
The timing for sampling the display data to the display data holding means is, for example, such that a control signal input line connected to the control input of the second display data holding means is provided, and sampling is performed by a control signal input to the control signal input line. It may be.

The display data as the first digital data is held in the display data holding means in this way.

On the other hand, a periodically changing analog voltage is applied to the voltage applying means, and the comparison data input line is synchronized with the voltage change applied to the voltage applying means.
Comparison data, which is second digital data that changes while maintaining a predetermined correspondence with the voltage value applied to the voltage application unit, is input.

Then, the display data held by the display data holding means is compared with the comparison data input to the comparison data input means, and an analog voltage corresponding to the display data is output. The output of the analog voltage corresponding to the display data is obtained by inserting switching means between the voltage applying means and the signal line, and comparing the opening and closing of the switching means with the display data and the comparison data. May be controlled by the output of.

For example, if the voltage application means is connected to the signal line when the comparison data and the display data match, a voltage corresponding to the display data is applied to the signal line as a display signal. Also, for example, when the sequentially increasing comparison data is smaller than the display data, the voltage application unit and the signal line are connected, and when the comparison data matches the display data or when the comparison data is larger than the display data, the voltage application unit is connected. The connection with the signal line may be cut off.

A flip-flop may be provided between the comparing means for comparing the display data with the comparison data and the switching element for connecting / disconnecting the voltage applying means and the signal line.

For example, the set input of the RS flip-flop is connected to the set signal line, and the reset input is connected to the output of the comparing means. Also, the positive output of the RS flip-flop is n
Connected to the gate electrode of a thin film transistor
Connected to the gate electrode of a thin film transistor. These thin film transistors are inserted in parallel between the voltage applying means and the signal lines. With such a connection, it is also possible to control the opening and closing of the switching means between the voltage applying means and the signal line, and to output an analog voltage corresponding to the display data to the signal line.

As described above, according to the drive circuit of the display device of the present invention, the display data input by the display data input means and held by the display data holding means is scaled with the analog voltage value applied to the voltage applying means. Since the connection between the voltage applying means and the signal line is controlled by this comparison, a voltage corresponding to the display data is applied to the signal line.

Upon receiving a comparison output of the display data and the comparison data held in the data holding means, the control means opens and closes the switch means. For example, when the display data and the comparison data match, the switch is turned on and the voltage application means is turned on. Is supplied to the signal line. When the comparison data and the display data are different, the switch element is cut off by the control means, and the voltage applied to the signal line at that time is held by the signal line capacitance. That is, a predetermined voltage corresponding to the display data held by the data holding means is applied to the signal line, and is supplied to each pixel of the display device.

Further, the control means receives the comparison output of the display data and the comparison data held in the data holding means and opens and closes the switch means. For example, when the comparison data is smaller than the display data, the switch is turned on. The analog voltage applied to the voltage applying means is supplied to the signal line. When the comparison data input from the comparison data input means sequentially rises and matches the data held in the data holding means, the switch element is cut off by the control means, and the voltage applied to the signal line at that time is reduced by the signal line capacitance. Is held by
That is, a predetermined voltage corresponding to the display data held by the data holding means is applied to the signal line, and is supplied to each pixel of the display device.

[0056]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail.

(Embodiment 1) FIG. 1 is a diagram showing an example of a circuit configuration when a driving circuit of a display device according to the present invention is applied to a liquid crystal display device for monochromatic display. FIG. 2 is a timing chart showing the operation of the drive circuit of the display device of FIG.

The circuits except for the liquid crystal pixel 1 shown in FIG. 1 are integrated on a substrate on which one electrode of the liquid crystal pixel 1 is formed. In FIG. 1, one end of a liquid crystal pixel 1 is grounded, and the other end is connected to a signal line 3 via a drain electrode-source electrode of a thin film transistor 2. The gate electrode of the thin film transistor 2 is connected to the scanning line 4. A predetermined number of pixels having such a configuration are arranged in a matrix to form a display screen. In the pixel array arranged in a matrix, the signal lines 3 are shared by the pixels in the column direction, and the scanning lines 4 are shared by the pixels in the row direction. Therefore, the signal lines 3 are arranged in the same number as the pixels in the column direction, and the scanning lines 4 are arranged in the same number as the pixels in the row direction. A predetermined voltage is applied to the scanning line 4 by a scanning line driving circuit (not shown), and the signal line 3 is driven by a signal line driving circuit described below.

In FIG. 1, a 10-bit digital numerical signal and its inverted signal are applied to the address data input line 5 as address data.

For example, if the address data is a binary value $ 000
When the 0000000} ^{is, 2 9 a, 2 8 a} , 2
^{7 a, 2 6 a, 2} 5 a, 2 4 a, 2 3 a, 2 2 a, 2 1
a, 2 ⁰ each address data input line 5 a is applied the values {0} and ^{2 9 b, 2 8 b,} 2 7 b, 2 6 b, 2 5
^{b, 2 4 b, 2 3} b, 2 2 b, 2 1 b, the 2 ⁰ b each address data input line 5 of the value {1} is applied.

Similarly, if the address data is a binary value $ 01
When 01010101} ^{is, 2 9 a, 2 8 b} , 2 7
^{a, 2 6 b, 2 5} a, 2 4 b, 2 3 a, 2 2 b, 2
¹ a, 2 ⁰ each address data input line 5 of b value {0} is ^{applied, 2 9 a, 2 8 b} , 2 7 a, 2 6 b, 2 5 a,
^{2 4 b, 2 3 a,} 2 2 b, 2 1 a, 2 0 b values {1} to each address data input line 5 of applied.

Then, for example, 10 inputs A in the first stage from the left
Each input of the ND gate 6 is 2 ⁹ b, 2 ⁸ b, 2
^{7 b, 2 6 b, 2} 5 b, 2 4 b, 2 3 b, 2 2 b, 2 1
b, 2 ⁰ b is connected to each address data input line 5, the input of the second stage 10 input AND gate 6, respectively ^{2 9 b, 2 8 b,} 2 7 b, 2 6 b, 2 ⁵ b, 2
^{4 b, 2 3 b, 2} 2 b, 2 1 b, 2 0 a is connected to each address data input line 5 of the third stage 10 input AN
Each input of the D gate 6 are each ^{2 9 b, 2 8 b,} 2 7
^{b, 2 6 b, 2 5} b, 2 4 b, 2 3 b, 2 2 b, 2
¹ a, 2 ⁰ b are connected to each address data input line 5. Similarly, each input line of each of the 10-input AND gates 6 in the fourth and subsequent stages is connected to the address data input line 5 by a different connection in each stage.

The output of the 10-input AND gate 6 is connected to the control input of an 8-bit latch 8 which operates as first display data holding means. The data input of latch 8 is
The output is connected to the display data input line 7, and the output is connected to the data input of the latch 10 which operates as the second display data holding means. The control input of the latch 10 is connected to the control signal input line 9, and the output is connected to one input of a comparator (digital comparator) 12.

The other input of the comparator 12 is connected to the comparison data input line 11, and the positive output is connected to the gate electrode of the N-type switch element 14, and the negative output is connected to the gate electrode of the P-type switch element 15. It is connected. Switch element 1
The drain electrodes 4 and 15 are connected to the analog voltage input line 13, and the source electrodes are connected to the signal line 3, respectively.

With such a connection, the address data $ 00000000 is applied to the address data input line 5.
When 00 is applied, only the output of the first-stage 10-input AND gate 6 becomes {1} and the first-stage latch 8 is driven, and the 8-bit display input to the data line 7 at that time is displayed. Data is retained. Next, $ 00000000
When 1} is input, only the output of the second-stage 10-input AND gate 6 becomes {1}, the second-stage latch 8 is driven, and the display data input to the data line 7 at that time is held. You. Further, when {000000000010} is input, only the output of the third-stage 10-input AND gate 6 becomes {1}, and the third-stage latch 8 is driven, and is then input to the display data input line 7. Display data is retained.

That is, when the numerical value applied to the address data input line is increased, the latch 8 can be sequentially driven from left to right, and when the numerical value is reduced, the latch 8 can be sequentially driven from right to left. Thus, the display data input to the display data input line 7 can be sequentially held.
In addition, the driving can be performed in an arbitrary order depending on how the numerical value is increased or decreased. Then, when the data is held in all the latches 8, each latch 8 holds the display data for one horizontal scan.

Next, after the display data is held in all the latches 8, that is, during the horizontal blanking period, the control line 9 is turned on.
, All the data held in the latch 8 is held in the latch 10 as the second display data holding means.

Until the next horizontal blanking period, AN
The D gate 6 and the latch 8 repeat the above-described operation to hold the display data for the next one horizontal scan, but the latch 10 as the second display data holding means keeps holding the display data.

For a predetermined period of one horizontal scanning period, for example, during a period when the latch 8 is sequentially performing a data holding operation, {00000000}
To {11111111} are inputted. Also, the analog voltage input line 1
3, an analog voltage which is sequentially increased or decreased in synchronization with the comparison data input line is input.

The comparator 12 compares the display data held in the latch 10 serving as the second display data holding means with the comparison data input to the comparison data input line 11, and displays the display data held in the latch 10. Is larger, the N-type switch element 14 connected to the positive output and the P-type switch element 15 connected to the negative output are made conductive, and the data is the same or the data held in the latch 10 is smaller. For example, the switch elements 14 and 15 are turned off.

Here, it is assumed that a predetermined scanning line 4 is driven by a scanning line driving circuit (not shown), and all the thin film transistors 2 connected to the driven scanning line are turned on. First,
Since {00000000} is input to the comparison data input line 11, all the switching elements 14 and 15 are turned on. The switch elements 14 and 15 are connected to the analog voltage input line 13
When the switching elements 14 and 15 are turned on, the voltage input to the analog voltage input line 13 is applied to the signal line 3, and the signal line capacitance, that is, the signal line 3 and the scanning line are connected. 4 is charged with the voltage to the parasitic capacitance between the thin film transistor 2 and the like.
Is also charged to the liquid crystal pixel 1 connected to.

The data input to the comparison data input line 11 sequentially increases, and when the data matches the data held in the latch 10 as the second display data holding means, the switch elements 14 and 15 become non-conductive, At this time, the voltage applied to the analog voltage input line 13 is held in the signal line capacitance and the liquid crystal pixel 1.

The switching elements 14 and 15 become nonconductive when the data held in the latch 10 and the data input to the comparison data input line 11 match,
Since the voltage corresponding to the comparison data is input to the analog voltage input line 13, the signal line capacitance and the voltage held in the liquid crystal pixel 1 are changed to the display data which is the first digital data held in the latch 10. A corresponding voltage, that is, a predetermined display voltage is held.

Further, the data input to the comparison data input line 11 sequentially increases to {11111111},
After all the switching elements 14 and 15 are turned off, that is, after a predetermined display voltage is held in all the liquid crystal pixels 1 connected to the turned-on thin film transistor 2, the scanning line driving circuit turns on. The thin film transistor 2 that has been turned off is turned off.

At this time, a predetermined display voltage is held in each liquid crystal pixel 1, and the display voltage is continuously held as it is. Since the display data for the next one horizontal scan is held in the latch 8 serving as the first data holding means during this time, the above operation is repeated for each scanning line 4 so that the entire display screen is displayed. A predetermined voltage is held in the liquid crystal pixel 1, and an image can be displayed.

It is preferable to input a voltage that rises or falls sequentially to the analog voltage input line 13. This is because the liquid crystal pixel 1 usually needs to be driven by an AC voltage. When driving the liquid crystal pixel 1 connected to the desired scanning line 4 via the thin film transistor 2, first input a sequentially increasing voltage to the analog voltage input line 13, and then drive the same liquid crystal pixel 1. , By inputting a voltage that sequentially decreases, the liquid crystal pixel 1 can alternately hold positive and negative voltages (inversion driving).

According to this embodiment, the display data input line 7
, A plurality of bits of display data sequentially input from the memory are sampled and held at a predetermined timing of one horizontal scanning period by a latch 8 serving as a first display data holding unit, and the data is used as a second display data holding unit. The data is sampled by the latch 10 during the horizontal blanking period and held until the next horizontal blanking period.

Then, during one horizontal scanning period, the comparison data input line 11 is supplied with a digital data of a plurality of bits which sequentially rises.
Input data and synchronize it with the analog voltage input line 1
A voltage which rises or falls sequentially is input to 3.

When the data held in the latch 10 is smaller than the data input from the comparison data input line 11,
The switch elements 14 and 15 are turned on by the comparator 12, and
The voltage applied to the analog voltage input line 13 is supplied to the signal line 3. When the data input from the comparison data input line 11 sequentially rises and matches the data held in the latch 10, the switch elements 14 and 15 are cut off by the comparator 12, and the voltage applied to the signal line 3 at that time Are held in the signal line capacitance of the signal line 3 and the liquid crystal pixel 1. That is, the liquid crystal pixel 1 holds a predetermined display voltage corresponding to the data held in the latch 10. As described above, the drive circuit of the display device according to the present invention basically includes the D / A conversion circuit that converts display data, which is digital data, into an analog voltage and outputs the analog voltage to a signal line of the display device.

According to such a drive circuit of the display device of the present invention, all the signal line drive circuits except the switch elements 14 and 15 are constituted by digital circuits. Is greater than or equal to the predetermined characteristic, there is almost no effect of the characteristic variation on the circuit operation. Only a very low frequency signal which sequentially increases or decreases during one horizontal scanning period is input to the analog voltage input line 13, and the time during which the switch elements 14 and 15 are turned on corresponds to the display voltage. In other words, since it changes as needed, the on-resistance of the switch elements 14 and 15 does not need to be extremely low, and there is no need to form a large-area thin film transistor.

In the above description of the first embodiment, when the comparison data is smaller than the held display data, the switch element is turned on by the comparator, and when the comparison data matches the held display data, the comparator is turned off. Has explained the operation in which the switch element is cut off. The present invention is not limited to this. For example, when the comparison data is smaller than or equal to the held display data, the switch is turned on by the comparator, and when the comparison data becomes larger than the held display data, the switch element is turned off by the comparator. Is also good. In this case, a comparator whose output is inverted when the comparison data becomes larger than the held display data may be used.

(Embodiment 2) The present invention is not limited to the embodiment illustrated in FIGS. FIG. 3 is a diagram showing an example of a circuit configuration when the driving circuit of the display device of the present invention is applied to a liquid crystal display device for color display.

The circuits except for the liquid crystal pixel 1 shown in FIG. 3 are integrated on a substrate on which one electrode of the liquid crystal pixel 1 is formed. In FIG. 3, one end of the liquid crystal pixel 1 is grounded, and the other end is connected to the signal line 3 via the drain-source electrode of the thin film transistor 2. The gate electrode of the thin film transistor 2 is connected to the scanning line 4.

A predetermined number of picture elements having a set of three pixels arranged in a row (horizontal) direction in the row (horizontal) direction are arranged in a matrix in a predetermined number of rows and columns to form a display screen. One pixel of each set constituting a picture element is used as a red display pixel, another one pixel is used as a green display pixel, and another one pixel is used as a blue display pixel. Note that the signal line 3 is shared by each pixel in the vertical direction, and the scanning line 4 is shared by each pixel in the horizontal direction. A predetermined voltage is applied to the scanning line 4 by a scanning line driving circuit (not shown), and the signal line 3 is driven by a signal line driving circuit described below.

In FIG. 3, a 10-bit digital numerical signal and its inverted signal are applied to address data input line 5 as address data. Each input of the first-stage 10-input AND gate 6 from the left is 2 ^{9
b, 2 8 b, 2 7} b, 2 6 b, 2 5 b, 2 4 b, 2
^{3 b, 2 2 b, 2} 1 b, 2 0 b is connected to each address data input line 5, the input of 10 input AND gate 6 in the second stage, each 2 ⁹ b, 2 ⁸ b, 2 ⁷ b, 2 ^{6
b, 2 5 b, 2 4} b, 2 3 b, 2 2 b, 2 1 b, 2 0 a
, And each input of the third-stage 10-input AND gate 6 is 2
^{9 b, 2 8 b, 2} 7 b, 2 6 b, 2 5 b, 2 4 b, 2 3
^{b, 2 2 b, 2 1} a, 2 0 b are connected to each address data input line 5. Similarly, each input line of each of the 10-input AND gates 6 in the fourth and subsequent stages is connected to the address data input line 5 by a different connection in each stage.

The output of the 10-input AND gate 6 is connected to control inputs of a set of three 8-bit latches 19, 20, and 21 which operate as first display data holding means.
The data inputs of the latches 19, 20, and 21 are connected to the red data input line 16, the green data input line 17, and the blue data input line 18, respectively, and each output operates as a second display data holding unit. Latches 22, 23, 24
Are connected to the data inputs.

The control inputs of the latches 22, 23, 24 are connected to the control signal input line 9, and the outputs are connected to one input of comparators (digital comparators) 25, 26, 27.

The other inputs of the comparators 25, 26 and 27 are connected to the comparison data input line 11, and the positive outputs are connected to the gate electrodes of the N-type switch elements 28, 29 and 30, respectively. The output is connected to each gate electrode of the P-type switch elements 31, 32, 33. Switch element 28, 2
The drain electrodes 9, 30, 31, 32, and 33 are connected to the analog voltage input line 13, and the source electrodes are connected to the signal line 3, respectively.

By making such a connection, the address data $ 00000000 is applied to the address data input line 5.
When 00｝ is input, the first-stage 10-input AND
Only the output of gate 6 becomes {1} and the first set of latches 1
9, 20, 21 are driven. Then, the 8-bit red display data input to the data line 16 at this time is held in the latch 19, the 8-bit green display data input to the data line 17 is held in the latch 20, and the data line 18
Are stored in the latch 21.

Next, when the address data {0000000001} is input to the address data input line 5, only the output of the second stage 10-input AND gate 6 becomes {1}, and the second set of latches 19, 20 and 21 are driven. Then, the 8 input to the data line 16 at that time
The bit red display data is held in the latch 19, the 8-bit green display data input to the data line 17 is held in the latch 20, and the 8-bit blue display data input to the data line 18 is held in the latch 21. Is done.

Further, when the address data {00000000010} is input to the address data input line 5, only the output of the third-stage 10-input AND gate 6 becomes {1}, and the third set of latches 19 and 20 , 21 are driven. Then, the 8 input to the data line 16 at that time
The bit red display data is held in the latch 19, the 8-bit green display data input to the data line 17 is held in the latch 20, and the 8-bit blue display data input to the data line 18 is held in the latch 21. Is done.

That is, when the numerical value applied to the address data input line is increased, the set of latches 19, 20, and 21 can be sequentially driven from left to right, and when the numerical value is reduced, the set is sequentially driven from right to left. Data line 1
The display data inputted to 6, 17, and 18 can be sequentially held. In addition, the driving can be performed in an arbitrary order depending on how the numerical value is increased or decreased. And
When the data is held in all the latches 19, 20, and 21, each of the latches 19, 20, and 21 holds the display data of red, green, and blue for one horizontal scan.

Next, after the display data is held in all the latches 19, 20, and 21, ie, all the first display data holding means, that is, during the horizontal blanking period, the control line 9 is driven. Latches 19, 20, 21
Are held by the latches 22, 23, and 24, which are the second data holding means. Until the next horizontal blanking period, the AND gate 6 and the latch 19,
20 and 21 repeat the above operation to hold the data for the next one horizontal scan, but the latches 22, 23 and 24 as the second data holding means continue to hold the data.

The comparison data input line 11 is connected to a predetermined period of one horizontal scanning period, for example, the above-mentioned latches 19, 20 and 21.
$ 0000 during the period during which the
An 8-bit numerical signal sequentially increasing from 0000} to {11111111} is input. Further, an analog voltage that sequentially increases or decreases in synchronization with the comparison data input line 11 is input to the analog voltage input line 13.

The comparators 25, 26, and 27 compare the display data held in the latches 22, 23, and 24, which are the second data holding means, with the comparison data input to the comparison data input line 11, and latch the data. If the data held in 22, 23 and 24 is larger, the N-type switch elements 28, 29 and 30 connected to the positive output and the P-type switch elements 31, 32 and 33 connected to the negative output are switched. If the data is the same or the data held in the latches 22, 23, and 24 are smaller, the switch elements 28, 29, 30, and 31, 3
2, 33 are made non-conductive.

Here, it is assumed that a predetermined scanning line 4 is driven by a scanning line driving circuit (not shown), and all the thin film transistors 2 connected to the scanning line 4 are turned on. First, since {00000000} is input to the comparison data input line 11, all the switch elements 28, 29, 30, 31, 3,
2, 33 conduct. Switch elements 28, 29, 30,
31, 32 and 33 are the analog voltage input line 13 and the signal line 3
Between the switch elements 28, 2
When 9, 30, 31, 32, and 33 become conductive, the voltage input to the analog voltage input line 13 is applied to the signal line 3, and the parasitic capacitance between the signal line 3, that is, the parasitic capacitance between the signal line 3 and the scanning line 4 and the like. As the voltage is charged, the liquid crystal pixel 1 connected to the conducting thin film transistor 2 is also charged with the voltage.

The comparison data input to the comparison data input line 11 sequentially increases, and when the comparison data matches the display data held in the latches 22, 23, 24, the switch elements 28, 2
9, 30, 31, 32, and 33 become non-conductive, and the voltage applied to the analog voltage input line 13 at that time is held in the signal line capacitance and the liquid crystal pixel 1.

Switch elements 28, 29, 30, 31, 3
The non-conduction state of the latches 2, 33 is caused by the latches 22, 23, 24.
That is, when the display data held in the second display data holding means matches the comparison data input to the comparison data input line 11, and the analog voltage input line 13 receives a voltage corresponding to the comparison data. Therefore, the parasitic capacitance and the voltage held in the liquid crystal pixel 1
The voltages correspond to the display data held in 2, 23, and 24, that is, predetermined red, green, and blue display voltages.

Further, the comparison data input to the comparison data input line 11 sequentially increases to {11111111}, and all the switch elements 28, 29, 30, 31, 3
After a predetermined display voltage is held in all the liquid crystal pixels 1 connected to the conducting thin film transistor 2 after the non-conducting state of the conducting thin film transistor 2 and 33, the conducting thin film transistor 2 Are made non-conductive. At this time, a predetermined display voltage is held in each of the liquid crystal pixels 1, and is continuously held as it is.

During this period, the display data for the next one horizontal scan is held in the latches 19, 20 and 21 as the first data holding means, so that the above operation is repeated for each scanning line 4. As a result, a predetermined voltage is held in all the liquid crystal pixels 1 on the display screen, and a color image is displayed.

According to the embodiment shown in FIG. 3, each of the red, green, and blue display data sequentially inputted from the display data input lines 16, 17, 18 is latched by the latches 19, 20, which are the first display data holding means. 21 sampled and held at a predetermined timing of one horizontal scanning period, and the data is sampled in a horizontal blanking period by latches 22, 23 and 24 as second display data holding means, and the next horizontal blanking period is sampled. Hold for a period.

During one horizontal scanning period, the comparison data input line 11 is supplied with a sequentially rising multi-bit digital signal.
Input data and synchronize it with the analog voltage input line 1
A voltage which rises or falls sequentially is input to 3.

When each data held in the latches 22, 23, and 24 is smaller than the data input from the comparison data input line 11, the comparators 25, 26, and 27 cause the switch elements 28, 29, 30, 31, and 32 to operate. , 33 conduct,
The voltage applied to the analog voltage input line 13 is supplied to the signal line 3. When the data input from the comparison data input line sequentially rises and matches the data held in the latches 22, 23, and 24, the comparators 25, 26, and 27 switch the switch elements 28, 29, 30, 31, 32, and 33. Is cut off, and the voltage applied to the signal line 3 at that time is changed to the signal line 3
And the liquid crystal pixel 1 holds. That is,
The liquid crystal pixel 1 holds a predetermined display voltage corresponding to each of the red, green, and blue display data held by the latches 22, 23, and 24.

Note that, similarly to the first embodiment, the comparison relationship between the display data and the comparison data and the connection control relationship of the switch elements can be set other than the above. For example, the comparator 12
Compares the display data held in the latch 10, which is the second display data holding means, with the comparison data input to the comparison data input line 11, and outputs a positive output when the display data and the comparison data are equal. N-type switch element 1 connected
4 and the P-type switch element 15 connected to the negative output may be made conductive.

As described above, according to the configuration illustrated in FIG. 3, the switch elements 28, 29, 30, 31, 32,
All of the signal line driving circuits except 33 can be constituted by digital circuits. Therefore, even when the signal line driving circuits are constituted by thin film transistors, if the characteristics of the thin film transistors are equal to or more than predetermined characteristics, the influence of the characteristic variation on the circuit operation is hardly affected. There is no.

Further, only a very low frequency signal which sequentially increases or decreases during one horizontal scanning period is input to the analog voltage input line 13, and the switching elements 28, 2
9, 30, 31, 32, and 33, the conduction time changes according to the display voltage, in other words, as needed, so that the switch elements 28, 29, 30, 31, 32, 33
It is not necessary to make the on-resistance extremely low, and it is not necessary to form a large-area thin film transistor.

(Embodiment 3) FIG. 4 is a diagram showing another configuration of the drive circuit of the display device of the present invention.

The drive circuit of FIG. 4 is obtained by replacing the 10-input AND gate 6 of the drive circuit of the display shown in FIG. 1 with a shift register 36. The clock input of each shift register 36 is connected to a clock line 34. The shift pulse input is the previous stage,
Connected to the shift pulse output of register 36,
The shift pulse input of the leftmost shift register 36 is connected to the shift pulse line 35. Further, the output of each shift register 36 is connected to the latch 8 which operates as the first holding means. Other circuits have the same connection as the configuration illustrated in FIG.

With such a configuration, the same operation as the driving circuit of the display device illustrated in FIG. 1 can be performed. That is, since the shift register 36 sequentially transfers the shift pulse to the next stage in synchronization with the clock, the latches 8 connected to the outputs of the shift registers 36 are sequentially driven from the left to hold the display data. Perform the operation.
Other circuits perform the same operation as the embodiment of FIG. Therefore, in the embodiment of FIG. 4, the same operation as in the embodiment of FIG. 1 can be performed, and the same effect can be obtained.

In the driving circuit of the display device of the present invention illustrated in FIG. 4, when a shift register capable of bidirectional shift is used as the shift register 36, the shift pulse is transferred from left to right. In addition to this, since the data can be transferred from right to left, it is possible to perform left-right inverted display.

(Embodiment 5) FIG. 5 is a diagram showing another configuration of the drive circuit of the display device of the present invention.

In the embodiment shown in FIG. 5, an RS flip-flop 38 is inserted in the output of the comparator 12 of the driving circuit of the display device shown in FIG. The set input of the RS flip-flop 38 is connected to the set signal line 37, and the reset input is connected to the output of the comparator 12. The positive output of the RS flip-flop 38 is connected to the gate electrode of the N-type switch element 14, and the negative output is connected to the gate electrode of the P-type switch element 15. Other circuits have the same connection as the configuration illustrated in FIG.

With such a configuration, the same operation as the driving circuit of the display device illustrated in FIG. 1 can be performed. That is, when the set signal line 37 is driven to set the RS flip-flop 38 at the same time as or before the comparison data and the analog voltage start to rise or fall, the switch elements 14 and 15 are turned on. When the comparison data matches the data held in the latch 10, the RS flip-flop 38 is reset by the comparator 12, and the switch elements 14 and 15 are cut off. Other circuits perform the same operation as the driving circuit of the display device illustrated in FIG. Therefore, the same operation as the driving circuit of the display device of the present invention illustrated in FIG. 1 can be performed by the driving circuit of the display device of the present invention having the configuration illustrated in FIG.

(Embodiment 6) The drive circuit of the display device of the present invention can be implemented in various modifications other than those described above.

The drive circuit of the display device of the present invention having the structure shown in FIG. 3 has been described as an example applied to a liquid crystal display device for performing color display. However, the circuit shown in FIG. It may be used as a circuit.

In this case, three display data input lines 16, 1
Data to be originally input from one display data input line are divided into three and input to the elements 7 and 18. That is,
The first data is input to the display data input line 16, the second data is input to the display data input line 17, and the third data is input to the display data input line 18. Next, the fourth data is input to the display data input line 16, the fifth data is input to the display data input line 17, and the sixth data is input to the display data input line 18. Hereinafter, the same applies. Then, the display data input from the display data input lines 16, 17 and 18 are simultaneously held by the latches 19, 20 and 21.

The other operations are the same as those of the driving circuit of the display device illustrated in FIG. 1, and thus the description is omitted. However, with such a configuration, three display data are input at the same time. The number of gates 6 can be reduced to 1/3 of the driving circuit of the display device having the configuration shown in FIG. 1, and the number of bits of the address data input line 5 and AND
The number of input lines of the gate 6 can be reduced by 1 bit or 2 bits.

Further, by simultaneously inputting three display data, the AND gate 6 and the latches 19, 20, 2
Since the operating frequency of 1 is １ ／, a display device with higher definition can be driven.

In this example, an example has been described in which display data is divided into three pieces and input. However, the display data may be divided into two pieces, four pieces, and more. Also, when the driving circuit of the display device of the present invention having the configuration illustrated in FIG. 3 is applied to a liquid crystal display device for color display, red display data, green display data, blue display data (or cyan display data, magenta display data, (Display data, yellow display data) may be divided and input. In such a case, of course, the number of bits of the address data input line 5, the number of input lines of the AND gate 6, the number of AND gates 6, the number of display data input lines, and one AND gate 6
May be increased or decreased as necessary.

(Embodiment 7) FIG. 6 is a diagram showing a relationship between an applied voltage and transmittance. FIG. 7 shows an example of a profile of a voltage waveform applied to an analog voltage input line so as to correct an offset voltage. FIG.

A normally white liquid crystal display device generally has a non-linear light transmission characteristic with respect to a drive voltage as illustrated in FIG. According to the drive circuit of the display device of the present invention, a drive voltage for correcting the light transmittance with respect to the display data can be obtained by applying a voltage as illustrated in FIG. 7 to the analog voltage input line. That is, by associating the correspondence between the analog voltage applied to the voltage application means and the comparison data input to the comparison data input means so as to correct the nonlinear light transmission characteristic with respect to the drive voltage, A linear light transmission characteristic can be obtained.

The same correction can be made for a normally black liquid crystal display device and other display devices. If necessary, any desired light transmission characteristics can be obtained by performing desired correction.

(Embodiment 8) In the signal application timing illustrated in FIG. 2, the case where the changing periods of the address data and the comparison data are different is exemplified. However, these periods are the same or a multiple of two. If different, all or some bits of the address data input line 5 and all or some bits of the comparison data line 11 can be shared.

For example, when the address data input line 5 is 9 bits, the comparison data line 11 is 8 bits, and the change period of the address data is の of the change period of the comparison data,
The upper 8 bits of the address data input line 5 and all the bits of the comparison data line 11 can be shared. Thus, the driving circuit of the display device having the configuration illustrated in FIG.
The configuration of the circuit can be simplified. Further, an external circuit for generating comparison data is not required, and the configuration of the display device itself can be simplified.

For example, when the address data input line 5
If the bit and the comparison data line 11 are 8 bits and the change period of the address data is twice the change period of the comparison data, all the bits of the address data input line 5 and the upper 7 bits of the comparison data line 11 are shared. be able to. Thus, the circuit can be simplified as compared with the embodiment of FIG. 1, and an external circuit for generating address data can be eliminated.

Even if all or some bits of the address data input line 5 and all or some bits of the comparison data line 11 are not shared, all or some bits of the address data and the comparison data By using the same signal for all the bits or some of the bits, an external circuit for generating address data or comparison data can be eliminated.

In the above embodiment, the comparison data has been described as sequentially increasing from {00000000} to {11111111}, but the present invention is not limited to this. For example, {11111111} to {00
You may make it descend | fall sequentially to 000000 degree | times.
In this case, for example, swap the two inputs of the comparator,
When the comparison data is larger than the data held in the latch, the switch element may be made conductive. In addition, the comparison data may be arranged in an arbitrary order.
It is only necessary that the display data, the comparison data, and the analog input voltage have a desired correspondence.

Note that the display data and the comparison data are not limited to 8 bits, and can be increased or decreased according to the required number of display gradations. The same applies to the number of bits of other digital data.

The drive circuit of the display device according to the present invention has been described above, but the present invention is not limited to these embodiments. For example, the driving circuit of the display device of the present invention having the configuration illustrated in FIG. 3 may be modified as illustrated in FIGS. 4 and 5.

In the driving circuit of the display device of the present invention having the structure shown in FIGS. 1, 3, 4 and 5, the comparator 1
Although the example in which the switch element is directly driven by the output of the 2 or RS flip-flop 38 has been described, it is also possible to drive the switching element via a buffer gate or a voltage level conversion circuit. Further, it is not always necessary to use an N-type switch element and a P-type switch element in combination, and only one of the switch elements may be used.

In the driving circuit of the display device of the present invention having the structure shown in FIGS. 1 and 5, the number of bits of the input address data is 10 bits. In this case, the maximum number of signal lines that can be handled is 1024. Become. Therefore, if the number of signal lines is larger than this, the number of bits of the input address data may be increased. Conversely, when the number of signal lines is less than 512, the number of bits of input address data can be reduced.

Similarly, the number of bits of the input address data may be increased or decreased in the drive circuit of the display device of the present invention having the configuration illustrated in FIG. As described above, when the display data is divided and a plurality of display data are input at the same time, the correspondence between the number of bits of the input address data and the maximum number of signal lines may be set as necessary. In the driving circuit of the display device of the present invention having the configuration illustrated in FIGS. 1, 3 and 5, the input address data is described as being sequentially increased. However, the present invention is not limited to this. Can be entered. In short, the connection between the numerical value of the input address data and the input of the AND gate should correspond in a desired order.

Further, in the driving circuit of the display device of the present invention having the structure shown in FIGS. 1, 3 and 5, an example is shown in which an inverted signal of input address data is also inputted. However, the present invention is not limited to this. is not. For example, an inverted signal of the input address data may be generated in the signal line driving circuit or the scanning line driving circuit, or a circuit configuration that does not use the inverted signal may be employed.

In the example shown in FIG. 3, if the red display liquid crystal pixel, the green display liquid crystal pixel, and the blue display liquid crystal pixel have different light transmission characteristics with respect to the drive voltage, the red analog voltage input line and the green By providing an analog voltage input line and an analog voltage input line for blue and connecting these to the signal line 3 via a switch element, it is possible to input and drive an analog voltage corresponding to the display characteristics of each color. .

Regarding the comparator 12 of the drive circuit of the display device having the configuration shown in FIG. 5, the magnitude of the data need not be compared, and only when the display data and the comparison data match,
The RS flip-flop 38 may be reset. In general, a comparator for comparing the coincidence of input signals has a smaller circuit scale than a comparator for comparing the magnitude of input signals, so that the signal line driving circuit can be made smaller.

In the driving circuit of the display device of the present invention having the structure shown in FIGS. 1, 3, 4, and 5, one end of the liquid crystal pixel 1 is grounded. Instead, the ground may be provided via a DC voltage source, for example. Further, an auxiliary capacitor may be connected in parallel with the liquid crystal pixel 1 in order to improve the voltage holding characteristics of the liquid crystal pixel 1, or a storage capacitor may be connected between the signal line 3 and the ground in order to adjust the signal line capacitance. A capacitor may be connected.

In the example of FIG. 2, address data is also input during the horizontal blanking period. However, as long as no address is selected for the address data during this period, any value may be input. It does not matter. Similarly, in the example of FIG. 2, the control signal is input at the end of the horizontal blanking period. However, the present invention is not limited to this, and the control signal may be applied during the horizontal blanking period.

As for the comparison data, {11111111} may be input during the horizontal blanking period, but {00000000} may be input during the horizontal blanking period.
By inputting 0 ° to make the switch element conductive and inputting a desired analog voltage, a desired voltage can be applied in advance before a display voltage is applied to the signal line. In the example of FIG. 5, the RS flip-flop can be obtained by simply setting the comparison data to {00000000}.
The flop 38 is not set, and the switch elements 14 and 15
Does not conduct, so that a similar operation may be performed by inputting a set signal to the set line 37.

Although all of the above embodiments have described the case of a liquid crystal display device, the drive circuit of the display device of the present invention is not limited to this, and can be applied to other display devices.

(Embodiment 9) FIG. 8 is a diagram schematically showing a configuration of a D / A converter of the present invention.

The D / A converter 100 includes first digital data 101, voltage applying means 102 to which a periodically changing analog voltage is applied, and a value corresponding to the analog voltage and synchronized with the analog voltage. Output means for comparing the first digital data 101 and the second digital data 103 and outputting an analog voltage corresponding to the first digital data 101. I have. In the example of FIG. 8, the output means includes a comparing means 104 for comparing the first digital data with the second digital data, and a switching means 105 whose opening and closing are controlled by the comparing means.

FIG. 9 is a diagram schematically showing the operation of the D / A converter of the present invention.

An analog voltage that increases or decreases periodically is applied to the voltage applying means 102. The second digital data 103 corresponds to the voltage value applied to the voltage applying means 102 and is synchronized with the analog voltage. And change. In the example shown in FIG. 9, a voltage that sequentially increases from Vmin to Vmax is applied to the voltage applying means 102, and {00000000} is applied to the second digital data 103.
8 shows a state in which 8-bit digital data changing from {11111111} to {11111111} is input.

The output means comprises: first digital data 101 to be converted into an analog voltage by the comparison means 104;
The second digital data 103 is compared with the second digital data 103, and a desired voltage is output by controlling the switching means 105 based on the output of the comparing means 104. For example, the first digital data 101 and the second digital data 103 are compared, and the voltage applied to the voltage applying means 102 when the first digital data 101 and the second digital data 103 match each other. May be output. When the second digital data 103 is smaller than the first digital data 101, a voltage is output, and when the second digital data 103 is larger than the first digital data 101, When they are equal, the output may be cut off.

For example, if the first digital data 101 to be converted into a voltage is {01010101}, the comparing means 104 converts the first digital data 101 and {00000000} to {11111111}.
Compare with the second digital data 103 which changes to 1 °. When the first digital data 101 and the second digital data 103 match, the voltage applying means 102
When the voltage applied to the second digital data 103 is {00000000} to {01010100}, for example, the voltage application unit 102
The switching means 105 such as a thin film transistor inserted between the input terminal and the output terminal is cut off by the comparing means 104. The second digital data 103 is $ 0101010
When it becomes 1 °, the comparing means 104 connects the switching means 105 and outputs the voltage V1 applied to the voltage applying means 102 at this time. When the second digital data 103 becomes {010110110}, the comparing means 104 outputs
4 shuts off the switch means 105.

Similarly, assuming that the first digital data 101 to be converted into a voltage is {10101010}, the comparing means 104 outputs the first digital data 1
01 and {0000000000} to {11111111}
Is compared with the second digital data 103 which changes up to. When the voltage applied to the voltage applying means 102 is output when the first digital data 101 matches the second digital data 103, the value of the second digital data 103 is changed from {00000000} to {10}.
Up to 101001 °, for example, the switching means 105 such as a thin film transistor inserted between the voltage applying means 102 and the output terminal is cut off by the comparing means 104. Second
When the digital data 103 becomes {10101010}, the comparing means 104 connects the switch means 105 and
At this time, the voltage V2 applied to the voltage applying means 102
Is output. The second digital data 103 is $ 101
When 01011 # is reached, the comparing means 104 turns off the switch means 105.

Therefore, the first digital data 10
1 is the second digital data 103 and the voltage applying means 1
02 is converted into a predetermined analog voltage based on the correspondence with the value 02 and output.

On the other hand, when the second digital data 103 is smaller than the first digital data 101, a voltage is output, and when the second digital data 103 is larger than or equal to the first digital data 101, the output is cut off. If the second digital data 1
03 is from {00000000} to {0101010}
Up to 0 °, for example, a switching means 10 such as a thin film transistor inserted between the voltage applying means 102 and the output terminal
5 is connected by the comparison means 104. When the second digital data 103 becomes {01010101}, the comparing means 104 shuts off the switch means 105, and at this time, the voltage V1 applied to the voltage applying means 102 is held at the output side capacitance. Further, the second digital data 10
When 3 is larger than {01010101}, that is, between {01011010} and {11111111}, the comparing means 104 causes the switching means 104 to switch
5 is shut off. Therefore, the first digital data 101 is converted to a predetermined analog voltage and output based on the correspondence between the second digital data 103 and the voltage applied to the voltage applying means 102. Also, the first digital data 101 to be converted into a voltage is $ 101010
The same applies to the case of 10 °.

As described above, according to the D / A converter of the present invention, the first digital data to be converted into a voltage is converted into the second digital data having a predetermined correspondence with the voltage value applied to the voltage applying means. Can be converted to an analog voltage and output.

FIG. 10 is a diagram schematically showing an example of the circuit configuration of the D / A converter of the present invention. This D / A converter includes a first digital data 101, a voltage applying means 102 to which a periodically changing analog voltage is applied, and a value corresponding to the analog voltage and changing in synchronization with the analog voltage. The second digital data 103 includes output means for comparing the first digital data 101 with the second digital data 103 and outputting an analog voltage corresponding to the first digital data 101. In the example of FIG. 8, the output means is a comparing means 104 for comparing the first digital data with the second digital data,
Switch means 10 whose opening and closing are controlled by this comparing means
5 and the operation is as described above.

The drive circuit of the display device of the present invention illustrated in FIGS. 1, 3, 4, and 5 is such that the output of the D / A converter of the present invention is used as a signal line of the display device. The D / A converter of the present invention can also be realized by a circuit configuration similar to these drive circuits.

Since the D / A converter of the present invention can be configured as a digital circuit except for the voltage application means, the D / A converter can be integrated, compact and stable. Also, for example, even when a polysilicon TFT is used as a switching element constituting a digital circuit, each TF
Stable operation can be achieved regardless of the characteristics of T.

(Embodiment 10) FIG. 11 is a diagram schematically showing a configuration of an array substrate of the present invention. FIG. 11 shows an example in which the present invention is applied to an array substrate of a liquid crystal display device.

The array substrate 200 is made of an insulating substrate 20
A display pixel array 202b formed in a matrix in the first region 202; a scanning line 203 for driving the pixel array in row units; a signal line 204 for applying a display signal to the pixel array in columns; Scan line 2 formed in a second region surrounding first region 202 of insulating substrate 201
And a signal line driving circuit 206 for driving a signal line. The signal line driving circuit 206 is a driving circuit of the display device of the present invention having the configuration described in the first to eighth embodiments. That is,
The signal line drive circuit 206 includes a voltage application unit that applies a periodically changing analog voltage, a signal line connected via the voltage application unit and the switch unit, and a signal line corresponding to the analog voltage and having Comparison data input means for inputting comparison data that changes in synchronization with the voltage,
Display data holding means for holding the input display data; comparing the comparison data input to the comparison data input means with the display data held in the display data holding means to connect and disconnect the switch means; Control means for controlling.

In the array substrate 200, as described above, the pixel array 202b, the scanning line driving circuit 205, and the signal line driving circuit 206 are integrally formed on the same substrate. The switching element 2 forming the pixel array and the switching elements forming the scanning line driving circuit 205 and the signal line driving circuit 206 each form a thin film transistor using polysilicon as an active layer.

Conventionally, high performance and large area polysilicon T
Although it was difficult to obtain a sufficient on-resistance even when FΤ, the array substrate of the present invention has a configuration in which the signal line driving circuit is suitable for integration, and the polysilicon thin film transistor is small in size. For good, a more compact array substrate is obtained. Also, if the size is the same, the array substrate can perform higher definition display.

Further, a high-speed buffer amplifier for driving the sampling transistor is not required, the area of this portion can be reduced, and a more compact array substrate can be provided.

Further, since it is not necessary to form a sampling transistor having a large area, productivity can be greatly improved and cost can be reduced. Further, errors in output voltage due to parasitic capacitance between the gate electrode and the source electrode and between the gate electrode and the drain electrode can be reduced. Therefore, since it is not necessary to divide the display screen and drive in parallel, a circuit for externally dividing the video signal is not required, and a higher definition display can be achieved while simplifying the configuration of the display device. It can be carried out. Further, according to the array substrate of the present invention, high-quality display can be performed without depending on the variation in the on-resistance of the sampling transistor.

[0159]

As described above, according to the drive circuit of the display device of the present invention, all the signal line drive circuits except the switching elements are constituted by digital circuits, so that the switching means is constituted by thin film transistors. Even if the characteristics of the thin film transistor are equal to or higher than the predetermined characteristics, the influence of the variation in the characteristics of the thin film transistor which affects the circuit operation can be almost eliminated. Also,
Only a very low frequency signal which sequentially increases or decreases during one horizontal scanning period is input to the analog voltage input line, and the time during which the switch element is conducting corresponds to the display voltage, in other words, as required. Therefore, it is not necessary to extremely reduce the on-resistance of the switching element, and it is not necessary to form a large-area thin film transistor.
Therefore, a small thin film transistor can be used, productivity can be greatly improved, and cost can be reduced.

According to the D / A converter of the present invention, all of the components other than the voltage applying means can be configured as digital circuits, so that the integration is achieved, and the device is small and operates stably. Further, for example, even when a polysilicon TFT is used as a switching element constituting a digital circuit, stable operation can be performed regardless of the characteristics of each TFT.

Further, according to the array substrate of the present invention, the signal line driving circuit has a configuration suitable for integration, and a small thin film transistor can be used, so that a more compact array substrate can be obtained. If the size is the same, higher definition display can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a circuit configuration of a drive circuit of a display device of the present invention.

FIG. 2 is a diagram showing operation timings of a drive circuit of the display device of the present invention illustrated in FIG.

FIG. 3 is a diagram showing another example of the circuit configuration of the drive circuit of the display device of the present invention.

FIG. 4 is a diagram showing another example of the circuit configuration of the drive circuit of the display device of the present invention.

FIG. 5 is a diagram showing another example of the circuit configuration of the drive circuit of the display device of the present invention.

FIG. 6 is a diagram showing a relationship between an applied voltage and transmittance.

FIG. 7 is a diagram showing an example of a profile of a voltage waveform applied to an analog voltage input line so as to correct an offset voltage.

FIG. 8 is a diagram schematically showing an example of the configuration of a D / A converter according to the present invention.

FIG. 9 is a diagram for explaining the operation of the D / A converter according to the present invention.

FIG. 10 shows another circuit configuration of the D / A converter of the present invention.
The figure which shows an example.

FIG. 11 is a view schematically showing an example of the configuration of an array substrate according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal pixel, 2 ... Thin film transistor, 3 ... Signal line, 4 ... Scanning line 5 ... Address data input line, 6 ... 10-input AND gate 7, 16, 17, 18 ... Display data input line , 8, 10, 19, 20, 21, 22, 23, 24 ... latch 9 ... control signal input line, 11 ... comparison data line 12, 25, 26, 27 ... comparator, 13 ... analog voltage Input lines 14, 28, 29, 30 N-type switch element 15, 31, 32, 33 P-type switch element 34 Clock line 35 Shift pulse line 36
... Shift register 37... Set signal line 38... RS flip-flop 100... D / A converter 101... First digital data 102. Data 104... Comparison means 105... Switch means 200... Array substrate 201 insulative substrate 202 first area 202 b display pixel array
203 ... scanning line 204 ... signal line, 20 ... 5 scanning line drive circuit, 206
…… Signal line drive circuit

Claims (15)

[Claims] 1. A voltage applying means for applying a periodically changing analog voltage, a signal line connected via said voltage applying means and a switch means, and a value corresponding to said analog voltage and said analog voltage Comparison data input means for inputting comparison data that changes in synchronization with display data, display data holding means for holding input display data, comparison data input to the comparison data input means, and holding in the display data holding means And a control means for controlling connection and disconnection of the switch means by comparing the displayed display data with the display data. 2. A display data holding means, comprising: a display data input means; and a first data sampling means for sampling and holding a plurality of bits of display data sequentially input to the display data input means at a predetermined timing in a horizontal scanning period. Display data holding means; and second display data holding means for sampling the display data held in the first display data holding means at a predetermined timing in a horizontal blanking period and holding the sampled data until the next horizontal blanking period. The driving circuit for a display device according to claim 1, comprising: 3. A voltage application unit for applying a periodically changing analog voltage, a signal line connected to the voltage application unit via a switch unit, and a value corresponding to the analog voltage and the analog voltage Comparison data input means for inputting comparison data that changes in synchronization with address data, address data input means for receiving address data, and gate means connected to the address data input means for outputting a gate signal based on predetermined address data Display data input means for inputting display data; display data holding means for sampling and holding the display data by the gate signal from the display data input means; and comparison data input to the comparison data input means And the display data held in the display data holding means. Driving circuit of a display device and control means for controlling the connection between the blocking and characterized by including the. 4. The drive circuit according to claim 3, wherein all or some bits of the comparison data and the address data are the same data. 5. A voltage applying means for applying an analog voltage that changes periodically, a signal line connected via said voltage applying means and a switch means, and a value corresponding to said analog voltage and said analog voltage Comparison data input means for inputting comparison data that changes in synchronization with a shift register connected in series; display data input means for inputting display data; and output from the shift register from the display data input means. A display data holding unit that samples and holds the display data; and compares the comparison data input to the comparison data input unit with the display data held in the display data holding unit to connect and disconnect the switch unit. A driving circuit for a display device, comprising: control means for controlling. 6. The drive circuit according to claim 1, wherein the control unit connects the switch unit when the comparison data and the display data match. 7. The control unit connects the switch unit when the comparison data is smaller than the display data, and shuts off the switch unit when the comparison data is larger than or equal to the display data. A driving circuit for a display device according to claim 1. 8. The control means is a digital comparator for comparing the magnitude of comparison data input to the comparison data input means with the display data held in the display data holding means, and the switch means is a digital comparator. The driving circuit for a display device according to claim 1, wherein the driving circuit is a thin film transistor that opens and closes by an output of the display device. 9. The flip-flop, wherein the control means is a flip-flop which is set by a set signal to connect the switch means, and which is reset when the comparison data and the display data match to shut off the switch means. The driving circuit for a display device according to claim 1, wherein: 10. The display device is a liquid crystal display device,
10. The analog voltage corresponding to the comparison data so as to correct a γ characteristic.
The driving circuit for a display device according to any one of the above. 11. A voltage applying means to which first digital data and a periodically changing analog voltage are applied, and a second voltage changing means corresponding to the analog voltage and changing in synchronization with the analog voltage. D means for comparing the digital data with the first digital data and the second digital data and outputting an analog voltage corresponding to the first digital data.
/ A converter. 12. The output means compares the first digital data with the second digital data and outputs the analog voltage when the first digital data matches the second digital data. The D / A converter according to claim 11, wherein: 13. The output means outputs the analog voltage when the second digital data is smaller than the first digital data, and outputs the analog voltage when the second digital data is larger than or equal to the first digital data. The D / A converter according to claim 11, wherein output of the analog voltage is stopped. 14. A display pixel array formed in a matrix on a first region of an insulating substrate; a scanning line for driving the pixel array in units of rows; and applying a display signal to the pixel array in units of columns. A signal line, voltage applying means formed in a second area surrounding the first area of the insulating substrate, for applying a periodically changing analog voltage, and connected via the voltage applying means and the switch means And the comparison signal input means for inputting comparison data whose value corresponds to the analog voltage and changes in synchronization with the analog voltage, and display data holding means for holding the input display data. ,
An array comprising control means for comparing the comparison data input to the comparison data input means with the display data held in the display data holding means to control connection and disconnection of the switch means. substrate. 15. A display pixel array having a first thin film transistor formed in a matrix on a first region of an insulating substrate and using polycrystalline silicon as an active layer, and scanning for driving the pixel array in units of rows. A line, a signal line for applying a display signal to the pixel array in column units, and a second line formed in a second region surrounding the first region of the insulating substrate, and driving the signal line based on display data. A voltage application unit configured to include a second thin film transistor using polycrystalline silicon as an active layer and further applying a periodically changing analog voltage; and the signal line connected to the voltage application unit via a switch unit. A comparison data input means for inputting comparison data whose value corresponds to the analog voltage and changes in synchronization with the analog voltage; Display data holding means for holding the display data, and comparing the comparison data input to the comparison data input means with the display data held in the display data holding means to control connection and disconnection of the switch means. An array substrate, comprising: a signal line drive circuit comprising control means.