JPH1070453A - Semiconductor logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a semiconductor logic circuit and to prevent malfunctions by adding a means for forced resetting into a precharge state at the time of a discriminative state to a 2nd logic gate RC. SOLUTION: The 2nd logic gate RC is provided with a delay circuit IVA and a NOR gate NOA. Then, the gate width of a PMOS inside the IV 1 is widened and the gate width of an NMOS is narrowed. Other wise, the gate width of a PMOS in an TV 2 is reduced and the gate width of a NMOS is widened. Thus, since the on-resistance of a logic block to be turned on at the time of the discriminative state is reduced, the switching of output RO to the discriminative state is accelerated. At the same time, the switching of RO to the precharge state is accelerated as well. Therefore, the period of the discriminative state is not increased but fixed. Thus, even when a circuit reducing the power consumption at the output RO in the precharge state and increasing the power consumption in the discriminative state such as the word line of a memory is driven, for example, power consumption is not increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit, and more particularly to a circuit technique suitable for increasing the speed, reducing power consumption, and preventing malfunction of a logic circuit that repeats a precharge state and a determination state.

[0002]

2. Description of the Related Art Conventionally, a semiconductor logic circuit which repeats a precharge state and a judgment state has been known. For example, CM
OS VLSI design principles (translated by Takashi Tomizawa and Yasuo Matsuyama,
The dynamic CMOS logic described on pages 138 to 141 of Maruzen) is a typical circuit. FIG. 3 shows an example in which a plurality of logic gates (inverters in this example) IV1, IV2, and IVA are cascaded to the output of the dynamic CMOS logic PC.

In this circuit, the operation waveforms when the logic block LBL is turned on by the input signals A1 and A2 are shown in FIG.
, PO, RO (1). During time t0 to t2, clock signal φ is at L level, and PC is in a precharged state. At this time, PO is at H level and RO (1) is at L level.
Level. Next, when φ switches to the H level at time t2, the PC enters the determination state,
O is switched to L level at time t3, and RO (1) is switched to H level at time t6. Next, when φ is switched to the L level at time t8, the PC is again in the precharge state, and accordingly, PO is switched to the H level at time t9 and RO (1) is switched to the L level at time t12. In this figure, the output R
To speed up the switching of O, the gates IV1,
The on-resistances of the logic blocks constituting the transistors IV2 and IVA, that is, the P-channel field-effect transistor PMOS and the N-channel field-effect transistor NMOS in this example may be reduced. In order to reduce the on-resistance of the PMOS or NMOS, the gate width of the PMOS or NMOS may be increased. However, increasing the gate width increases the parasitic capacitance of the gate, source, and drain of the PMOS or NMOS. Therefore, if the gate width is too large, the switching of the output RO will be rather delayed.

[0004]

SUMMARY OF THE INVENTION Accordingly, the present inventors
Considering that it is only necessary to speed up the switching to the determination state in order to speed up the circuit of FIG. 3, a logic block that is turned on in a precharge state in a cascade-connected logic gate (in this example, an inverter) (NMOS in IV1, IV2
Logic blocks (PMOS in IV1; NMO in IV2)
The on-resistance of S) was reduced.

That is, the gate width of the PMOS in IV1 is increased and the gate width of the NMOS is reduced, and the gate width of the PMOS in IV2 is reduced and the gate width of the NMOS is increased. In this case, the sum of the gate, source, and drain parasitic capacitances per logic gate does not increase as in the conventional example. The operation waveform when the on-resistance is different as described above is shown as RO (2) in FIG. From the figure, it can be seen that, since the on-resistance of the logic block that is turned on in the determination state is reduced, the switching to the RO determination state is accelerated from time t6 to time t5. However, a point to be noted here is that the switching of the RO to the precharge state is performed at time t1 because the ON resistance of the logic block that is turned on in the precharge state is increased.
That is, it is late from time 2 to time t16.

Therefore, the present inventors have studied in detail the adverse effects caused by delay in switching to the precharge state. As a result, the following two problems were clarified. The first problem occurs because switching to the determination state is speeded up and switching to the precharge state is delayed, resulting in an increase in the period of the determination state. That is, there are many logic circuits that consume a small amount of power in the precharge state and a large amount of power in the determination state, such as a memory cell including a flip-flop. Therefore, when such a circuit, for example, a word line of a memory is driven by the output RO, the power consumption increases as the period of the determination state increases.

Next, the second problem will be described. The second problem is that the difference between the on-resistance of the logic block that turns on in the precharge state and the on-resistance of the logic block that turns on in the determination state is further increased, for example, in order to further speed up switching to the determination state. Occurs when: As described above, the operation waveform when the difference in on-resistance is increased is
This is shown as RO (3) in FIG. From the figure, it can be seen that, since the on-resistance of the logic block that is turned on in the determination state is further reduced, the switching of the RO to the determination state is further accelerated from time t5 to time t4. But,
Since the ON resistance of the logic block that is turned on during the precharge state is further increased, the switching of the RO to the precharge state is further delayed from the time t16 (calculated at the time t20), and the switching time to the next determination state. (Calculated time t16). That is, after time t4, all the circuits are in the determination state, the precharge state does not appear, and the circuit malfunctions. In order to prevent such a malfunction, the period of the clock signal φ may be increased, that is, the operating frequency may be reduced, but this is contrary to the increase in speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor logic circuit in which the on-resistance of a logic block that is turned on in a precharge state is smaller than the on-resistance of a logic block that is turned on in a judgment state in order to speed up switching to a judgment state. Power consumption and malfunction prevention.

[0009]

An object of the present invention is to provide a first logic gate PC that repeats a precharge state and a determination state in response to a clock signal φ, and is connected to the output of the first logic gate and connected in cascade. In a semiconductor logic circuit including a logic gate block GB composed of n (n is a positive integer) stages of logic gates and a second logic gate RC connected to an output of the logic gate block, A logic block comprising a logic block that turns on at least one logic gate in a precharge state and a logic block that turns on in a determination state, and is turned on in the determination state based on the ON resistance of the logic block that turns on in the precharge state Means for reducing the on-resistance of the second logic gate and forcibly resetting the second logic gate to the precharge state in the judgment state. It is achieved by pressing.

As described above, if means for forcibly resetting to the precharge state in the judgment state is added to the second logic gate, the period of the judgment state can be reduced, and the power consumption can be reduced accordingly. Furthermore, the switching time of the output to the precharge state is later than the switching time to the next determination state, so that malfunction of the circuit can be prevented.

[0011]

FIG. 1 is a diagram showing a first embodiment of the present invention. In this example, the clock signal φ
A first logic gate PC that repeats a precharge state and a determination state according to the above condition, and a logic gate that is connected to the output of the first logic gate and that is a cascade-connected two-stage logic gate (in this example, an inverter) Block GB and a second logic gate R connected to the output of logic gate block GB.
C, a means for forcibly resetting the second logic gate RC to the precharge state in the judgment state is added to the second logic gate RC. That is, the second logic gate includes the delay circuit IVA and the NOR gate N
OA, and the input of the delay circuit IVA is connected to the output of the logic gate block GB.
Each input of the OR gate NOA is connected to the output of the logic gate block GB and the output of the delay circuit IVA.

FIG. 2 shows an operation waveform in the case where the logic block LBL is turned on by the input signals A1 and A2.
, PO, RO (1). During time t0 to t2, clock signal φ is at L level, and PC is in a precharged state. At this time, PO is at H level and RO (1) is at L level.
Level. Next, when φ switches to the H level at time t2, the PC enters the determination state,
O is switched to L level at time t3, and RO (1) is switched to H level at time t6. However, since a means for forcibly resetting to the precharge state in the determination state is added to the second logic gate RC, RO (1) switches to the L level again at time t7 to be in the precharge state. next,
When φ switches to the L level at time t8, the PC is again in the precharge state, and in response, PO switches to the H level at time t9. At this time, switching does not occur because RO (1) is already at the L level.

In this circuit, in order to speed up the switching to the judgment state, in the judgment state, the ON resistance of the logic block which is turned on in the precharge state in the cascade-connected logic gates (inverters in this example) is used. What is necessary is just to reduce the on resistance of the logic block to be turned on. That is, I
The gate width of the PMOS in V1 may be increased and the gate width of the NMOS may be decreased, and the gate width of the PMOS in IV2 may be decreased and the gate width of the NMOS may be increased. The operation waveform in the case where the ON resistance is different is shown as RO (2) in FIG. From the figure, it can be seen that, since the on-resistance of the logic block that is turned on in the determination state is reduced, the switching to the RO determination state is accelerated from time t6 to time t5. It can also be seen that the switching of the RO to the precharge state is accelerated from time t7 to time t6. For this reason, the period of the determination state is constant without increasing. Therefore, even if the output RO of this example drives a circuit that consumes less power in the precharge state and consumes more power in the determination state, for example, a word line of a memory, the power consumption does not increase. That is, the first problem can be solved.

Next, it will be described that the second problem can be solved in this embodiment. Operation waveforms when the difference between the on-resistance of the logic block that turns on in the precharge state and the on-resistance of the logic block that turns on in the determination state is further increased to further speed up the switching to the determination state in this example. Is shown as RO (3) in FIG. From the figure, it can be seen that, since the on-resistance of the logic block that is turned on in the determination state is further reduced, the switching of the RO to the determination state is further accelerated from time t5 to time t4. On the other hand, the switching of the RO to the precharge state is also accelerated from the time t6 to the time t5 as in the previous case. Therefore, as described above, the switching of the RO to the precharge state is slower than the switching to the next determination state, and the precharge state does not appear, so that the circuit does not malfunction. .

FIG. 5 is a diagram showing a second embodiment of the present invention. This example differs from FIG. 1 only in the configuration of the first logic gate PC that repeats the precharge state and the determination state according to the clock signal φ. That is, while the logic block LBL is inserted between the transistors P1 and N1 in FIG. 1, the LBL is inserted between N1 and VSS in this example. Even if the PC is configured in this manner, the discussion described with reference to FIG. That is, at least one of the logic gates in the logic gate block GB is constituted by a logic block that is turned on in the precharge state and a logic block that is turned on in the judgment state, and the precharging is performed in order to speed up the switching to the judgment state. When the on-resistance of the logic block that is turned on in the determination state is smaller than the on-resistance of the logic block that is turned on in the state, the power consumption in the precharge state is large and the power consumption in the determination state is large in the output RO of this example. Driving the circuit does not increase power consumption. Further, even when the difference in the on-resistance is further increased in order to further speed up the switching to the determination state, the circuit does not malfunction.

FIG. 6 is a view showing a third embodiment of the present invention. This example corresponds to the logic block LB in the logic gate PC of FIG.
3 shows a specific configuration example of L. In this example, LNL is set to n
And a function PO = / (A · B + C ·
(D + E)) is shown.

FIG. 7 is a diagram showing a fourth embodiment of the present invention. This example corresponds to the logic block LB in the logic gate PC of FIG.
3 shows a specific configuration example of L. In this example, LNL is C
It is composed of MOS type logic blocks, and the function PO = / (A · B
+ C · (D + E)) is shown.

FIG. 8 is a diagram showing a fifth embodiment of the present invention. This example differs from FIG. 5 only in the configuration of a logic gate block GB composed of logic gates connected in cascade. That is, in FIG. 5, the logic gate block GB is constituted by two-stage inverters, whereas in this example, GB is set to N
It is composed of an OR gate NO1 and a NAND gate NA2. Even if the GB is configured in this manner, the discussion described with reference to FIG. That is, in order to speed up the switching to the determination state, when a difference is made in the on-resistance between the logic blocks constituting the logic gates in the logic gate block GB, the output RO of the present example uses the output RO in the precharge state. Even if a circuit having low power consumption and high power consumption in the determination state is driven, the power consumption does not increase. Further, even when the difference in the on-resistance is further increased in order to further speed up the switching to the determination state, the circuit does not malfunction.

FIG. 9 is a diagram showing a sixth embodiment of the present invention. This example differs from FIG. 5 in that the logic gate block GB
And the configuration of the second logic gate RC connected to the output of this logic gate block. That is, in FIG. 5, the logic gate block GB is constituted by two stages of logic gates (inverters) connected in cascade, whereas in this example, GB is constituted by three stages of logic gates (inverters). . By doing so, the levels of the GB output GO in the precharge state and in the determination state are reversed. Accordingly, in response to this, the logic gate RC is connected to the delay circuit IVA in FIG.
In this example, the RC is constituted by a delay circuit IVA and a NAND gate NAA. As described above, even when the number of cascaded logic gates in the logic gate block GB is different,
If the configuration of the logic gate RC is changed correspondingly,
The argument described in FIG. 1 holds similarly. That is, in order to speed up the switching to the determination state, when a difference is made in the on-resistance between the logic blocks constituting the logic gates in the logic gate block GB, the output RO of the present example uses the output RO in the precharge state. Even if a circuit having low power consumption and high power consumption in the determination state is driven, the power consumption does not increase. Further, even when the difference in the on-resistance is further increased in order to further speed up the switching to the determination state, the circuit does not malfunction.

FIG. 10 is a diagram showing a seventh embodiment of the present invention. This example differs from FIG. 5 in that the configuration of the first logic gate PC that repeats the precharge state and the determination state in response to the clock signal φ and the second logic gate RC connected to the output of the logic gate block GB Configuration. That is,
In FIG. 5, the logical block LBL is inserted between N1 and VSS.
1 and VDD. This way,
The levels of the output PO of the PC in the precharge state and in the determination state are reversed. Accordingly, in response to this, the logic gate RC is constituted by the delay circuit IVA and the NOR gate NOA in FIG.
A and a NAND gate NAA. As described above, even when the level relationship between the precharge state of the output PO of the logic gate PC and the determination state is different, if the configuration of the logic gate RC is changed correspondingly, the discussion described in FIG. I do. That is, in order to speed up the switching to the determination state, when a difference is made in the on-resistance between the logic blocks constituting the logic gates in the logic gate block GB, the output RO of the present example uses the output RO in the precharge state. Even if a circuit having low power consumption and high power consumption in the determination state is driven, the power consumption does not increase. Further, even when the difference in the on-resistance is further increased in order to further speed up the switching to the determination state, the circuit does not malfunction.

FIG. 11 shows an eighth embodiment of the present invention. This example differs from FIG. 5 in that the logic gate block G
This is only the configuration of the second logic gate RC connected to the output of B. That is, in FIG. 5, the logic gate RC is connected to the delay circuit I
VA and NOR gate NOA,
In this example, the RC is composed of only the NOR gate NOA, and the control signal RS is input to one of the inputs. By configuring the RC as described above and forcibly resetting the RC to the precharge state in the determination state by the control signal RS, the discussion described in FIG. 1 is similarly established in this example. That is, in order to speed up the switching to the determination state, when a difference is made in the on-resistance between the logic blocks constituting the logic gates in the logic gate block GB, the output RO of the present example uses the output RO in the precharge state. Even if a circuit having low power consumption and high power consumption in the determination state is driven, the power consumption does not increase. Further, even when the difference in the on-resistance is further increased in order to further speed up the switching to the determination state, the circuit does not malfunction.

FIG. 12 is a diagram showing a ninth embodiment of the present invention. This example differs from FIG. 5 in that the logic gate block G
This is only the configuration of the second logic gate RC connected to the output of B. That is, in FIG. 5, the delay circuit in the logic gate RC is constituted by the inverter IVA, whereas in this example, the delay circuit in the RC is constituted by the NAND gate NAA, and the control signal DA is inputted to one of the inputs. ing. In this example, when DA is at the H level, the discussion described in FIG. 1 holds similarly. That is, in order to speed up the switching to the determination state, when a difference is made in the on-resistance between the logic blocks constituting the logic gates in the logic gate block GB, the output RO of the present example uses the output RO in the precharge state. Even if a circuit having low power consumption and high power consumption in the determination state is driven, the power consumption does not increase. Further, even when the difference in the on-resistance is further increased in order to further speed up the switching to the determination state, the circuit does not malfunction. In this example, by controlling DA to L level, RC can be freely reset to the precharge state. Therefore, for example, when a word line of a memory is driven by the RO, if the word line is a defective word line, DA is controlled to L level so that this word line cannot be forcibly selected.

FIG. 13 is a diagram showing a tenth embodiment of the present invention. This example differs from FIG. 5 in that the configuration of a logic gate block GB composed of cascade-connected logic gates and GB
Only in that a PC2 for driving the. That is, in FIG. 5, the logic gate block GB is constituted by two-stage inverters, whereas in this example, GB is replaced by the NAND gate N.
A1 and an inverter IV2. Also, NAN
One input of the D gate NA1 is connected to the output of a logic gate PC2 that repeats a precharge state and a determination state according to a clock signal φ as in the case of PC1. Even if the logic circuit is configured in this manner, the discussion described with reference to FIG. That is, in order to speed up the switching to the determination state, when a difference is made in the on-resistance between the logic blocks constituting the logic gates in the logic gate block GB, the output RO of the present example uses the output RO in the precharge state. Low power consumption,
Even if a circuit that consumes a large amount of power in the determination state is driven, the power consumption does not increase. Further, even when the difference in the on-resistance is further increased in order to further speed up the switching to the determination state, the circuit does not malfunction.

FIG. 14 is a diagram showing an eleventh embodiment of the present invention. This example differs from FIG. 5 in that the configuration of a logic gate block GB composed of cascade-connected logic gates and GB
The only difference is that PC2 and GB2 for driving are added. That is, in FIG. 5, the logic gate block GB is constituted by two-stage inverters, whereas in this example, GB1 is constituted by the inverter IV1 and the NOR gate NO2. One input of the NOR gate NO2 is connected to the output of a logic gate block GB2 connected to the output of a logic gate PC2 that repeats a precharge state and a determination state in response to a clock signal φ in the same manner as PC1. Even if the logic circuit is configured in this manner, the discussion described with reference to FIG. That is, in order to speed up the switching to the determination state, when a difference is made in the on-resistance between the logic blocks constituting the logic gates in the logic gate block GB, the output RO of the present example uses the output RO in the precharge state. Low power consumption,
Even if a circuit that consumes a large amount of power in the determination state is driven, the power consumption does not increase. Further, even when the difference in the on-resistance is further increased in order to further speed up the switching to the determination state, the circuit does not malfunction.

FIG. 15 shows a twelfth embodiment of the present invention. This embodiment shows an example in which the present invention is applied to a memory decoder. In this example, A0 to A3 are address input signals, W0 to W15 are word line drive signals, AB is an address buffer, PD is a predecoder, and WD is a word line drive circuit. The logic of this decoder is set so that only one of the word lines W0 to W15 is selectively driven in accordance with the address input signals A0 to A3. In this example, AB, P
D and WD roughly correspond to, for example, PC, GB, and RC in FIG. Therefore, also in this example, the discussion described with reference to FIG. That is, power consumption does not increase when the on-resistance of the logic block constituting the logic gate in the decoder is made different in order to increase the speed. Further, even when the difference between the on-resistances is further increased in order to further increase the speed, the decoder does not malfunction.

FIG. 16 shows a thirteenth embodiment of the present invention. This example shows an example in which the logic gate in the decoder of FIG. 15 is constituted by a field effect transistor.

FIG. 17 is a diagram showing a fourteenth embodiment of the present invention. This example shows another example in which the present invention is applied to a decoder of a memory. This example is different from FIG.
In this example, all the address buffers AB are configured by logic gates that repeat a precharge state and a determination state according to the clock signal φ.
Only 0 is constituted by a logic gate which repeats a precharge state and a judgment state according to a clock signal φ, and the address buffer AB1 is constituted by a normal logic gate.
Even when the decoder is configured in this manner, the effects of the present invention described with reference to FIG. 1 can be similarly obtained.

FIG. 18 is a diagram showing a fifteenth embodiment of the present invention. This example shows another example in which the present invention is applied to a decoder of a memory. This example is different from FIG.
In the first embodiment, the address buffer AB is configured by a logic gate that repeats a precharge state and a determination state in response to a clock signal φ. In this example, the predecoder PD1 switches between a precharge state and a determination state in response to a clock signal φ. In FIG. 15, the delay circuit in the word line drive circuit is configured by an inverter, whereas in the present embodiment, the delay circuit is configured by a NAND gate.
The point is that the control signal DW0 is input to one of the inputs of the AND gate. Even if the decoder is configured in this way, FIG.
The effects of the present invention described above can be similarly obtained. In this example, by controlling DW0 to L level, the word line W0 can be freely reset to the precharge state. That is, if W0 is a defective word line, DW0 can be controlled to L level so that this word line cannot be forcibly selected.

[0029]

As described above, according to the present invention, the first logic gate PC which repeats the precharge state and the determination state in response to the clock signal φ, and the output of the first logic gate are connected. In a semiconductor logic circuit composed of a logic gate block GB composed of n stages of logic gates connected in cascade and a second logic gate RC connected to the output of the logic gate block GB, At least one of the logic gates is turned on in a precharge state and a logic block is turned on in a judgment state, and in order to speed up switching to the judgment state, When the on-resistance of the logic block that is turned on in the judgment state is made smaller than the on-resistance, the output RO of RC causes the precharge state in the precharge state. Low power consumption, be driven circuit power consumption is large in the decision state, no power consumption is increased. Further, even when the difference in the on-resistance is further increased in order to further speed up the switching to the determination state, the circuit does not malfunction.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of FIG.

FIG. 3 is a diagram showing a conventional example.

FIG. 4 is a diagram showing operation waveforms of FIG. 3;

FIG. 5 is a diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram showing a third embodiment of the present invention.

FIG. 7 is a diagram showing a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a fifth embodiment of the present invention.

FIG. 9 is a diagram showing a sixth embodiment of the present invention.

FIG. 10 is a diagram showing a seventh embodiment of the present invention.

FIG. 11 is a diagram showing an eighth embodiment of the present invention.

FIG. 12 is a diagram showing a ninth embodiment of the present invention.

FIG. 13 is a diagram showing a tenth embodiment of the present invention.

FIG. 14 is a diagram showing an eleventh embodiment of the present invention.

FIG. 15 is a diagram showing a twelfth embodiment of the present invention.

FIG. 16 is a diagram showing a thirteenth embodiment of the present invention.

FIG. 17 is a diagram showing a fourteenth embodiment of the present invention.

FIG. 18 is a diagram showing a fifteenth embodiment of the present invention.

[Explanation of symbols]

φ: a clock signal, A1, A2: an input signal, RO: an output signal, PC: a logic gate that repeats a precharge state and a judgment state according to φ, and GB: a logic gate connected in cascade. Logic gate block, RC ... Logic gate.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Raku Yamazaki 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Takeshi Kusunoki 3681 Hayano, Mobara-shi, Chiba Pref. (72) Inventor Kunihiko Yamaguchi 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Keiichi Hishita 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Masami Usami 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (4)

[Claims] A first logic gate that repeats a precharge state and a determination state according to a clock signal φ;
N connected in cascade with the output of the logic gate of
(N is a positive integer) In a semiconductor logic circuit composed of a logic gate block GB composed of logic gates and a second logic gate RC connected to an output of the logic gate block, A logic block that turns on at least one of the logic gates in the precharge state and a logic block that turns on in the determination state, and the on resistance of the logic block that turns on in the determination state based on the on resistance of the logic block that turns on in the precharge state And a means for forcibly resetting the second logic gate to a precharged state in a judgment state is added to the second logic gate. 2. The second logic gate includes a delay circuit and a NO
An input of the delay circuit is connected to an output of the logic gate block, and an input of each of the NOR (or NAND) gates is connected to an output of the logic gate block and the delay. 2. The semiconductor logic circuit according to claim 1, wherein the semiconductor logic circuit is connected to an output of the circuit. 3. The second logic gate includes a NOR (or NAND) gate, and each input of the NOR (or NAND) gate is an output of the logic gate block and a first control signal. Connected to the first
2. The semiconductor logic circuit according to claim 1, wherein the second logic gate is forcibly reset to a precharged state in the determination state by the control signal. 4. The delay circuit according to claim 1, wherein the delay circuit is a NAND (or NOR).
The NAND (or NOR)
Each input of the gate is connected to the output of the logic gate block and a second control signal, and the second control signal forcibly resets the second logic gate to a precharge state. The semiconductor logic circuit according to claim 2.