JPH1069257A - Data driver of liquid display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data driver which eliminates the display testing section which generates test data and allows the test of liquid crystal display panels easily and at low cost by providing a test data generating section which generates test data required for displaying test patterns on a liquid crystal display panel. SOLUTION: The data driver is provided with a test data generating section 9 which generates test data TDATA of 6 bit strucrture, D to D, required for displaying test patterns, based on vertical synchronizing signal VS, a horizontal synchronizing signal HS, or a clock signal CLK instead of supplying display data supplied externally to a data register section 2. And the test data TDATA is made to be supplied to the data register section 2. This data driver is provided with a gradation voltage generating section which generates plural gradation voltages different in voltage value and a gradation voltage selecting section which selects a gradation voltage corresponding to the test data from plural gradation voltages to impress on the data line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal suitable for use in a display test of an active matrix type liquid crystal display panel which performs display by causing each pixel arranged in a matrix to perform a storage operation. The present invention relates to a display panel data driver.

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display panel, pixel electrodes are formed in a matrix and connected between data lines (signal electrodes), scan lines (scan electrodes), and data lines and pixel electrodes. A pixel electrode substrate (TFT substrate) formed with a TFT (thin film transistor) serving as a switching element whose conduction and non-conduction is controlled via a scan line, and a common electrode common to all pixel electrodes are formed. And a common electrode substrate.

A peripheral circuit for driving an active matrix type liquid crystal display panel configured as described above includes a data driver for applying a gradation voltage required for image display to a data line, and a TFT for conducting and stopping a TFT via a scan line. And a scan driver for controlling non-conduction.

Then, the TFTs in each row are sequentially turned on by the scan driver via the scan lines in each row,
Display is performed by writing the gradation voltage applied to the data line from the data driver to the pixel electrode of each row through the TFT that is turned on.

Here, the data driver can be broadly classified into an analog data driver to which an analog signal is supplied as display data from a display data supply source, and a digital data driver to which a digital signal is supplied. FIG. 52 shows a main part of an example of a conventional digital data driver.

In FIG. 52, reference numeral 1 denotes a start pulse SP supplied at a rate of one per one horizontal period for determining the start of capture of the display data DATA of 6 bits D0 to D5 supplied from the display data supply source. The display data capture signals SB1, SB2,... S synchronized with the clock signal CLK by shifting in synchronization with the clock signal CLK.
B240 is a shift register unit that sequentially outputs B240.

[0007] Reference numeral 2 denotes a display data input signal SB1, SB2,..., SB output from the shift register unit 1.
Display data DATA for 240 pixels controlled by 240
Is a data register unit that sequentially captures data.

Reference numeral 3 denotes a latch unit which simultaneously latches display data DATA of 240 pixels taken into the data register unit 2 under the control of the latch pulse LP, and 4 denotes a display of 240 pixels latched by the latch unit 3. Data DAT
A decoder for decoding A.

Reference numeral 5 denotes a DC voltage V supplied from the outside.
A8, VA7,..., VA0 are gradation voltage generators that generate gradation voltages VB63, VB62,.

Reference numeral 6 denotes a gray scale voltage VB6 output from the gray scale voltage generator 5 based on the output of the decoder 4.
3, VB62... VB0 and display data DA
The gradation voltage corresponding to TA is applied to data lines DB1, DB2,.
B240 is a selector unit for outputting to B240.

[0011]

In order to guarantee the display quality of an active matrix type liquid crystal display panel,
It is necessary to perform a display test by displaying a test pattern. Conventionally, this display test is performed by preparing a display tester that generates test data necessary to display the test pattern. This is performed by supplying test data generated by a tester to a data driver and displaying a test pattern on an active matrix type liquid crystal display panel.

However, when an active matrix type liquid crystal display panel having different operating conditions such as an operating frequency is manufactured, a display tester must be manufactured for each of the display testers. Therefore, there is a problem that a great deal of time and cost are required for the display test.

In view of the foregoing, the present invention eliminates the need for a display tester that generates test data necessary to display a test pattern, and is simple and inexpensive for displaying an active matrix liquid crystal display panel. An object of the present invention is to provide a data driver for a liquid crystal display panel capable of performing a test.

[0014]

According to the first aspect of the present invention, there is provided a data driver for a liquid crystal display panel according to the first aspect.
Forms a pixel electrode in a matrix and forms a data line, a scan line, and a switching element connected between the data line and the pixel electrode, the conduction and non-conduction of which is controlled via the scan line. The first
Of a liquid crystal display panel that applies a gradation voltage to data lines of a liquid crystal display panel formed by enclosing liquid crystal between a substrate of a liquid crystal display panel and a second substrate formed with a common electrode common to all pixel electrodes. In the data driver, a test data generator for generating test data required to display the test pattern on the liquid crystal display panel, and a grayscale voltage generator for generating a plurality of grayscale voltages having different voltage values. And a gradation voltage selection unit for selecting a gradation voltage corresponding to the test data from the plurality of gradation voltages and applying the selected gradation voltage to the data line.

According to the first aspect of the present invention, since the test data generating section for generating the test data necessary for displaying the test pattern on the liquid crystal display panel is provided, the test pattern is generated in addition to the data driver. A display tester for generating test data necessary for displaying the data is unnecessary.

According to a second aspect of the present invention, there is provided a data driver for a liquid crystal display panel according to the second aspect.
The test data generating unit generates test data for generating a plurality of types of test data necessary for displaying a plurality of types of test patterns based on a vertical synchronization signal, a horizontal synchronization signal, or a clock signal supplied from outside. It is provided with a generation unit and a test data selection unit for selecting one type of test data from a plurality of types of test data.

According to a third aspect of the present invention, a data driver for a liquid crystal display panel according to the third aspect is provided.
The test data generation unit generates test data for inverting the display polarity every predetermined time for all or a part of the plurality of types of test data.

According to a fourth aspect of the present invention, there is provided a data driver for a liquid crystal display panel according to the fourth aspect.
The test data generation unit generates a plurality of types of test data necessary for displaying a plurality of types of test patterns, respectively.
A test data storage unit in which test data to be output is specified by a test pattern selection signal supplied from the outside and stored in a continuous address for each data unit to be output, and a test pattern selection signal An address signal generation unit for generating an address signal for addressing an address area in the address area of the test data storage unit in which test data corresponding to the test pattern specified by the test pattern selection signal is stored. It has a part.

According to a fifth aspect of the present invention, there is provided a liquid crystal display panel data driver according to the fifth aspect.
The address signal generating section includes addressing direction switching means for switching the addressing direction at regular time intervals.

According to a sixth aspect of the present invention, there is provided a data driver for a liquid crystal display panel according to the sixth aspect, wherein in the second, third, fourth or fifth aspect, the plurality of types of test patterns include:
A horizontal gray scale pattern, a vertical gray scale pattern, a horizontal stripe pattern, a vertical stripe pattern, a checkered pattern, or a solid pattern over the entire surface is included.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
A first embodiment and a second embodiment of the present invention will be described.

First Embodiment FIGS. 1 to 27 FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention. In the first embodiment of the present invention, instead of supplying display data DATA supplied from the outside to the data register unit 2, a test pattern is formed based on a vertical synchronizing signal VS, a horizontal synchronizing signal HS or a clock signal CLK. Test data TDA of 6-bit configuration D0 to D5 required for display
A test data generating section 9 for generating TA is provided, and test data TDATA is supplied to the data register section 2. The other configuration is the same as that of the conventional data driver shown in FIG.

FIG. 2 is a circuit diagram showing the configuration of the test data generator 9. 2, reference numeral 10 denotes horizontal stripe pattern display data or vertical stripe pattern display data, horizontal gray scale pattern display data, vertical gray scale as test data TDATA based on the vertical synchronization signal VS, the horizontal synchronization signal HS, or the clock signal CLK. A test data generation unit that generates pattern display data, checkered pattern display data, and full-area solid pattern display data.

In the test data generation unit 10,
Numeral 11 denotes a 12-bit counter to which the vertical synchronizing signal VS is input to the counted signal input terminal IN as a counted signal.
This is an output terminal from which the count value of the second bit is output.
In this example, the output terminals Q0 to Q5 are not used,
Only output terminals Q6-Q11 are used.

FIG. 3 is a waveform diagram showing the operation of the 12-bit counter 11. FIG. 3A shows the vertical synchronizing signal VS input to the counted signal input terminal IN and the output terminal Q0.
3B show the logical levels of the output signals, and FIG. 3B shows the output signals output to the output terminals Q6 to Q11 in a reduced time axis.

In FIG. 2, reference numeral 12 denotes a horizontal synchronizing signal HS or a clock signal CLK input to the counted signal input terminal IN as a counted signal, and an output signal output to the output terminal Q6 of the 12-bit counter 11. A 6-bit up / down counter is input to the up / down control signal input terminal U / D as an up / down control signal.
This is an output terminal from which the count value of the bit is output.

When the logic level of the up / down control signal input terminal U / D is set to "0", the 6-bit up / down counter 12 performs an up-count operation and performs an up / down operation. When the logic level of the control signal input terminal U / D is set to "1", a down count operation is performed.

FIG. 4 is a waveform diagram showing the operation of the 6-bit up / down counter 12. FIG. 4A shows a case where the horizontal synchronizing signal HS is up-counted (U
/ D = “0”), the logic levels of the output terminals Q0 to Q6, and FIG. 4B shows the output when the horizontal synchronization signal HS is down-counted (U / D = “1”). The logic levels of the terminals Q0 to Q6 are shown.

Here, when the horizontal synchronizing signal HS is input to the counted signal input terminal IN of the 6-bit up / down counter 12, the 12-bit counter 11
The 6-bit up / down counter 12 and the 6-bit up / down counter 12 constitute a horizontal stripe pattern display data generation unit that generates horizontal stripe pattern display data necessary for displaying the horizontal stripe pattern.

On the other hand, when the clock signal CLK is input to the counted signal input terminal IN of the 6-bit up / down counter 12, the 12-bit counter 11 and the 6-bit up / down counter Counter 12
Thus, a vertical stripe pattern display data generation unit that generates vertical stripe pattern display data necessary for displaying the vertical stripe pattern is configured.

In FIG. 2, reference numeral 13 denotes a signal having an inverted-phase output terminal / Q connected to the data input terminal D and a horizontal synchronizing signal HS.
Is a D flip-flop circuit that constitutes a 1/2 frequency divider that is input to the clock signal input terminal C.

An AND circuit 14 performs an AND process on an output signal output to the output terminal Q6 of the 12-bit counter 11 and an output signal output to the in-phase output terminal Q of the D flip-flop circuit 13.

Reference numeral 15 denotes a NOT circuit for inverting an output signal output to the output terminal Q6 of the 12-bit counter 11, and reference numeral 16 denotes an output signal of the NOT circuit 15 and an inverted-phase output terminal / Q of the D flip-flop circuit 13. An AND circuit for performing an AND process on the output signal to be output;
And an output signal of the AND circuit 16 is OR-processed.

Here, the 12-bit counter 11 and D
Flip-flop circuit 13 and AND circuits 14 and 16
The NOT circuit 15 and the OR circuit 17 constitute a horizontal grayscale pattern display data generation unit that generates horizontal grayscale pattern display data necessary for displaying the horizontal grayscale pattern.

Reference numeral 18 denotes a D flip-flop circuit which constitutes a 1/2 frequency divider having the inverted output terminal / Q connected to the data input terminal D and the clock signal CLK input to the clock signal input terminal C. .

Reference numeral 19 denotes a 12-bit counter circuit 1
This is an AND circuit that performs an AND process on the output signal output to the output terminal Q6 and the output signal output to the in-phase output terminal Q of the D flip-flop circuit 18.

Reference numeral 20 denotes a NOT circuit for inverting an output signal output to the output terminal Q6 of the 12-bit counter 11, and reference numeral 21 denotes an output signal of the NOT circuit 20 and an inverted output terminal / Q of the D flip-flop circuit 18. An AND circuit for performing an AND process on the output signal to be output, 22 is an AND circuit 19
And an output signal of the AND circuit 21.

Here, the 12-bit counter 11 and D
Flip-flop circuit 18 and AND circuits 19 and 21
The NOT circuit 20, and the OR circuit 22 constitute a vertical grayscale pattern display data generation unit that generates vertical grayscale pattern display data necessary for displaying a vertical grayscale pattern.

Reference numeral 23 denotes a D flip-flop circuit 13
An EOR circuit for performing an EOR (exclusive OR) operation on an output signal output to the positive-phase output terminal Q of the D flip-flop circuit 18 and an output signal output to the positive-phase output terminal Q of the D flip-flop circuit 18;
Is an EOR circuit that performs an EOR process on an output signal output to the output terminal Q6 of the 12-bit counter 11 and an output signal of the EOR circuit 23.

Here, the 12-bit counter 11 and D
Flip-flop circuits 13 and 18, EOR circuit 23,
24 constitutes a checkerboard pattern display data generator that generates checkerboard pattern display data necessary for displaying a checkerboard pattern.

Further, by the 12-bit counter 11,
An entire solid pattern display data generation unit that generates the entire solid pattern display data necessary to display the entire solid pattern is configured.

Reference numeral 25 denotes a selector, XA0 to XA
A5, XB0 to XB5, XC0 to XC5, XD0 to XD
5, XE0 to XE5 are input terminals, Q0 to Q5 are output terminals, and SL0, SL1, and SL2 are select control signals.

The input terminals XA0 to XA5 are connected to the output terminals Q0 to Q5 of the 6-bit up / down counter 6.
Are input to the input terminals XB0 to XB
The output signal of the OR circuit 17 is input to B5, the output signal of the OR circuit 22 is input to the input terminals XC0 to XC5, the output signal of the EOR circuit 24 is input to the input terminals XD0 to XD5, and the input terminal XE0 The output signals output to the output terminals Q6 to Q11 of the 12-bit counter 11 are input to .about.XE5.

Here, the select control signal SL0 =
When “0”, SL1 = “0”, and SL2 = “0”, the input terminals XA0 to XA5 are selected and the input terminals XA0 to XA5 are selected.
A0 to XA5 are connected to output terminals Q0 to Q5.

Also, the select control signal SL0 = "1",
When SL1 = "0" and SL2 = "0", the input terminals XB0 to XB5 are selected, and the input terminals XB0 to XB
B5 is connected to output terminals Q0 to Q5.

Also, select control signal SL0 = "0",
When SL1 = “1” and SL2 = “0”, the input terminals XC0 to XC5 are selected and the input terminals XC0 to XC0 are selected.
C5 is connected to output terminals Q0 to Q5.

Also, the select control signal SL0 = "1",
When SL1 = "1" and SL2 = "0", the input terminals XD0 to XD5 are selected and the input terminals XD0 to XD
D5 is connected to output terminals Q0 to Q5.

Also, select control signal SL0 = "0",
When SL1 = “0” and SL2 = “1”, the input terminals XE0 to XE5 are selected, and the input terminals XE0 to XE0 are selected.
E5 is connected to output terminals Q0 to Q5.

The first embodiment of the present invention configured as described above
When using the form, the active matrix type liquid crystal display panel has six types of test patterns, a horizontal gray scale pattern, a vertical gray scale pattern, a horizontal stripe pattern, a vertical stripe pattern, a checkered pattern, and a full solid pattern. Patterns can be selectively displayed.

Here, when a horizontal gray scale pattern is displayed as the test pattern, as shown in FIG. 5, a horizontal synchronizing signal is input to the counted signal input terminal IN of the 6-bit up / down counter 12. HS and the select control signal SL0 = "0", SL1 =
By setting “0” and SL2 = “0”, the selector 25 selects the input terminals XA0 to XA5.

In this manner, the 6-bit up / down counter 12 operates during the period in which the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to 64th vertical periods. The synchronization signal HS is counted up.

That is, the output terminals Q0, Q1, Q2, Q3, Q4, Q5 of the 6-bit up / down counter 12
Is [000000] every horizontal period.
→ [100,000] → [010000] → [11000
[0111] → [011111] → [111111], and such a change is repeated.

As a result, the output terminals Q0,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [000000] → [10
0000] → [010000] → [110000] → ・
・ ・ → [011111] → [111111]
Such a change will be repeated.

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) of the first horizontal line
= [000000] during the period in which the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to 64th vertical periods. ), Each of the first, second, third, fourth... 63th, 64th, 65th, 66th, 67th,. Data TDATA (D0, D1, D2, D3, D4, D
5) = [000000], [100000], [010
000], [110000] ... [011111],
[111111], [000000], [10000
0], [010000],... Can be supplied. Therefore, as shown in FIG. 6B, the display surface 27 of the active matrix type liquid crystal display panel is provided.
Can display a horizontal grayscale pattern.

On the other hand, during the period in which the logic level of the output terminal Q6 of the 12-bit counter 11 is "1", such as the 65th to 128th vertical periods, the 6-bit up / down counter 12 operates in the horizontal direction. The synchronization signal HS is counted down.

That is, the output terminals Q0, Q1, Q2, Q3, Q4, Q5 of the 6-bit up / down counter 12
Of [111111] every one horizontal period
→ [011111] → [101111] → [00111
[10000] → [1000000] → [000000], and such a change is repeated.

As a result, the output terminals Q0,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [111111] → [01] every one horizontal period.
1111] → [101111] → [001111] → ・
・ ・ → [1000000] → [000000]
Such a change will be repeated.

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) for the first horizontal line
= [111111], the 12-bit counter 1 such as the 65th to 128th vertical period
During the period in which the logical level of the output terminal Q6 of the No. 1 is “1”, as shown in FIG. 7A, the first, second, third, fourth... 65, 66, 6
For each pixel electrode of 7 horizontal lines ...
Test data TDATA (D0, D1, D2, D3, D
4, D5) = [111111], [011111],
[101111], [001111] ... [1000
00], [000000], [111111], [01
711], [101111],... Can be supplied to the display surface 27 of the active matrix type liquid crystal display panel as shown in FIG. ) Can be displayed.

When a vertical gray scale pattern is displayed as a test pattern, a clock signal CLK is applied to the counted signal input terminal IN of the 6-bit up / down counter 12 as shown in FIG. Input and select control signal SL0 = "0", SL1 =
By setting “0” and SL2 = “0”, the selector 25 selects the input terminals XA0 to XA5.

In this way, the 6-bit up / down counter 12 operates during the period when the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to 64th vertical periods. The signal CLK will be counted up.

That is, the output terminals Q0, Q1, Q2, Q3, Q4, Q5 of the 6-bit up / down counter 12
The logical level of [000000] → [100] in one cycle of the clock signal CLK, that is, every one dot period.
000] → [010000] → [110000] →
->[011111]-> [111111], and such a change is repeated.

As a result, the output terminals Q0,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [000000] → [1
[00000] → [010000] → [110000] →
... → [011111] → [111111], and such a change is repeated.

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) of the first vertical line
= [000000] during the period in which the logical level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to the 64th vertical periods. ), The first, second, third, fourth... 63th, 64th, 65th, 66th, and 67th vertical lines. Data TDATA (D0, D1, D2, D3, D4, D
5) = [000000], [100000], [010
000], [110000] ... [011111],
[111111], [000000], [10000
0], [010000],... Can be supplied. As shown in FIG. 9B, the display surface 27 of the liquid crystal display panel of the active matrix system can be supplied as shown in FIG.
Can display a vertical grayscale pattern.

On the other hand, during the period in which the logic level of the output terminal Q6 of the 12-bit counter 11 is "1", such as the 65th to 128th vertical periods, the 6-bit up / down counter 12 The signal CLK will be counted down.

That is, the output terminals Q0, Q1, Q2, Q3, Q4, Q5 of the 6-bit up / down counter 12
Is [11111] every dot period.
1] → [011111] → [101111] → [001
111] → ・ ・ ・ → [100000] → [00000
0], and such a change is repeated.

As a result, the output terminal Q0 of the selector 25,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [111111] → [0
11111] → [101111] → [001111] →
... → [1000000] → [000000], and such a change is repeated.

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) of the first vertical line
= [111111], the 12-bit counter 1 such as the 65th to 128th vertical period
During the period in which the logical level of the output terminal Q6 of the No. 1 is "1", as shown in FIG. 10A, the first, second, third, fourth... 65, 66, 6
For each pixel electrode of 7 vertical lines ...
Test data TDATA (D0, D1, D2, D3, D
4, D5) = [111111], [011111],
[101111], [001111] ... [1000
00], [000000], [111111], [01
1111], [101111],... Can be supplied. Therefore, as shown in FIG. 10B, the display surface 27 of the active matrix type liquid crystal display panel has the structure shown in FIG. ) Can be displayed.

When a horizontal stripe pattern is displayed as the test pattern, as shown in FIG. 11, the select control signals SL0 = "1", SL1 = "0", and SL2 = "
As "0", in the selector 25, the input terminal XB
0 to XB5 are selected.

FIG. 12 is a waveform chart for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to 64th vertical periods. 12 (A) is a 12-bit counter 11
12 (B) shows the horizontal synchronizing signal HS input to the clock signal input terminal C of the D flip-flop 13, and FIG. 12 (C) shows the logical level of the in-phase output terminal Q of the D flip-flop 13. Logic level, FIG.
FIG. 12E shows an output signal of the AND circuit 14, and FIG.
(F) is an output signal of the AND circuit 16, and FIG.
3 illustrates an output signal of the R circuit 17.

That is, during the period in which the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to 64th vertical periods, the logic level of the output signal of the OR circuit 17 changes every one horizontal period. Then, "0" → "1" →
"0" → "1" → ... → "0" → "1", and such a change is repeated.

As a result, the output terminal Q0 of the selector 25,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [000000] → [11] every horizontal period.
[1111] → [000000] → [111111] → ・
・ ・ → [000000] → [111111]
Such a change will be repeated.

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) of the first horizontal line
= [000000], control is performed during a period in which the logical level of the output terminal Q6 of the 12-bit counter 11 is “0”, such as the first to 64th vertical periods, as shown in FIG. ), The first, second, third,
The display test data TDATA (D0, D1, D2, D3, and D) are respectively applied to the pixel electrodes of the fourth to 63rd, 64th, 65th, 66th, and 67th horizontal lines.
4, D5) = [000000], [111111],
[000000], [111111] ... [0000
00], [111111], [000000], [11
1111], [000000],... Can be supplied, so that a horizontal stripe pattern is displayed on the display surface 27 of the active matrix type liquid crystal display panel as shown in FIG. be able to.

FIG. 14 is a waveform diagram for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is "1", such as the 65th to 128th vertical periods. (A) is a 12-bit counter 1
14 (B) is the horizontal synchronizing signal HS input to the clock signal input terminal C of the D flip-flop 13, and FIG. 14 (C) is the normal phase output terminal Q of the D flip-flop 13. FIG. 14D shows the logic level of the inverted-phase output terminal / Q of the D flip-flop 13, FIG. 14E shows the output signal of the AND circuit 14, and FIG.
(F) is an output signal of the AND circuit 16, and FIG.
3 illustrates an output signal of the R circuit 17.

That is, for example, from the 65th to the 128th vertical period,
During the period in which the logical level of the output terminal Q6 of the 2-bit counter 11 is "1", the logical level of the output signal of the OR circuit 17 changes from "1" to "0" every horizontal period.
"1" → "0" → ... → "1" → "0", and such a change is repeated.

As a result, the output terminal Q0 of the selector 25,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [111111] → [00] every one horizontal period.
0000] → [111111] → [000000] → ・
・ ・ → [111111] → [000000]
Such a change will be repeated.

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) of the first horizontal line
= [111111], the 12-bit counter 1 such as the 65th to 128th vertical period
During the period in which the logical level of the output terminal Q6 of the No. 1 is “1”, as shown in FIG. 15A, the first, second, third, fourth... 65, 66, 6
For each pixel electrode of 7 horizontal lines ...
Display test data TDATA (D0, D1, D2, D
3, D4, D5) = [111111], [00000
0], [111111] [000000] ... [11
1111], [000000], [111111],
Since gray scale voltages corresponding to [000000], [111111],... Can be supplied, as shown in FIG. A horizontal stripe pattern in which the display polarity is opposite to that of the horizontal stripe pattern shown in B) can be displayed.

When a vertical stripe pattern is displayed as the test pattern, as shown in FIG. 16, the select control signals SL0 = "0", SL1 = "1", and SL2 = "
In the selector 25, the input terminal XC
0 to XC5 are selected.

FIG. 17 is a waveform chart for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to 64th vertical periods. 17 (A) is a 12-bit counter 11
17 (B) shows the clock signal CLK input to the clock signal input terminal C of the D flip-flop 18, and FIG. 17 (C) shows the logic of the positive-phase output terminal Q of the D flip-flop 18. FIG. 17D shows the logic level of the inverted-phase output terminal / Q of the D flip-flop 18, FIG. 17E shows the output signal of the AND circuit 19, and FIG.
17 (F) is an output signal of the AND circuit 21, and FIG.
3 illustrates an output signal of the R circuit 22.

That is, during the period in which the logical level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to 64th vertical periods, the logical level of the output signal of the OR circuit 22 changes every one dot period. Then, "0" → "1" →
[0] → [1] →... → [0] → [1], and such a change is repeated.

As a result, the output terminal Q0 of the selector 25,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [000000] → [1
11111] → [000000] → [111111] →
... → [000000] → [111111], and such a change is repeated.

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) of the first vertical line
= [000000], when the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to 64th vertical periods, FIG. ), The first, second, third,
The test data TDATA (D0, D1, D2, D3, D4,...) Are respectively applied to the pixel electrodes of the fourth to 63rd, 64th, 65th, 66th, and 67th vertical lines.
D5) = [000000], [111111], [00
0000], [111111] ... [00000
0], [111111], [000000], [111
111], [000000],... Can be supplied, so that a vertical stripe pattern is displayed on the display surface 27 of the active matrix type liquid crystal display panel as shown in FIG. be able to.

FIG. 19 is a waveform chart for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is "1", such as the 65th to 128th vertical periods. (A) is a 12-bit counter 1
19 (B) is the clock signal CLK input to the clock signal input terminal C of the D flip-flop 18, and FIG. 19 (C) is the logical level of the output terminal Q6 of the D flip-flop 18. Logic level, FIG. 19 (D)
1E is the logic level of the inverted output terminal / Q of the D flip-flop 18, FIG. 19E is the output signal of the AND circuit 19, FIG.
9 (F) shows an output signal of the AND circuit 21 and FIG. 19 (G) shows an output signal of the OR circuit 22.

That is, for example, from the 65th to the 128th vertical period,
During the period when the logical level of the output terminal Q6 of the 2-bit counter 11 is “1”, the logical level of the output signal of the OR circuit 22 changes from “1” → “0” →
"1" → "0" → ... → "1" → "0", and such a change is repeated.

As a result, the output terminal Q0 of the selector 25,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [111111] → [0
00000] → [111111] → [000000] →
... → [111111] → [000000], and such a change is repeated.

Therefore, the test data TDATA (D0, D1, D2, D3, D4, D5) of the first vertical line
= [111111], the 12-bit counter 1 such as the 65th to 128th vertical period
During the period in which the logical level of the output terminal Q6 of the No. 1 is “1”, as shown in FIG. 20A, the first, second, third, fourth,... 65, 66, 6
For each pixel electrode of 7 vertical lines ...
Test data TDATA (D0, D1, D2, D3, D
4, D5) = [111111], [000000],
[111111], [000000] ... [1111]
11], [000000], [111111], [00
0000], [111111],... Can be supplied to the display surface 27 of the active matrix type liquid crystal display panel as shown in FIG.
As shown in FIG. 18B, a vertical stripe pattern in which the display polarity is reversed from the vertical stripe pattern shown in FIG. 18B can be displayed.

When a checkerboard pattern is displayed as a test pattern, as shown in FIG. 21, the select control signals SL0 = “1”, SL1 = “1”, and SL2 =
In the selector 25, the input terminal XD
0 to XD5 are selected.

FIG. 22 is a waveform chart for explaining the operation when the logical level of the output terminal Q6 of the 12-bit counter 11 is "0", such as the first to 64th vertical periods. 22 (A) is a horizontal synchronizing signal H input to the clock signal input terminal C of the D flip-flop 13.
S, FIG. 22B shows the logic level of the positive-phase output terminal Q of the D flip-flop 13, FIG. 22C shows the clock signal CLK input to the clock signal input terminal C of the D flip-flop 18, and FIG. ) Is the logical level of the positive-phase output terminal Q of the D flip-flop 18, FIG. 22E is the output signal of the EOR circuit 23, FIG. 22F is the logical level of the output terminal Q6 of the 12-bit counter 11, FIG. (G) is E
3 illustrates an output signal of the OR circuit 24.

That is, in the odd horizontal period such as the 1st to 64th vertical periods in which the logic level of the output terminal Q6 of the 12-bit counter 11 is "0", the EOR
The logic level of the output signal of the circuit 24 is “0” → “1” →
"0" → "1" → ... → "0" → "1", and in the even horizontal period, the output signal of the EOR circuit 24 is
"1" → "0" → "1" → "0" → ... → "1" →
It changes to “0”, and such a change is repeated.

As a result, the output terminal Q0 of the selector 25,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [000000] → [111111] → [0000] every one dot period in the odd horizontal period.
00] → [111111] → ・ ・ ・ → [000000]
→ [111111], and in the even-numbered horizontal period, [111111] → [000
000] → [111111] → [000000] → ...
-→ [111111] → [000000], and such a change is repeated.

Therefore, the test data TDATA (D0, D1, D
2, D3, D4, D5) = [000000], test data TDATA of the first vertical line in the even horizontal period
(D0, D1, D2, D3, D4, D5) = [1111
11], the output terminal Q6 of the 12-bit counter 11 such as the first to 64th vertical periods
During the period in which the logical level of
As shown in (A), the first, second, third, fourth,..., 63, 64, 65,
The test data TDATA (D0, D1,.
D2, D3, D4, D5) = [000000], [11
1111], [000000], [111111] ...
[000000], [111111], [00000]
0], [111111], [000000],..., And on even-numbered horizontal lines, the first, second, third, fourth,. For each pixel electrode of the 64th, 65th, 66th, 67th vertical lines,...
(D0, D1, D2, D3, D4, D5) = [1111
11], [000000], [111111], [00
0000] ... [111111], [00000]
0], [111111], [000000], [111
111] can be supplied, so that a checkered pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel as shown in FIG.

FIG. 24 is a waveform chart for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter 11 is "1", such as the 65th to 128th vertical periods. (A) is a D flip-flop 13
Horizontal synchronization signal H input to the clock signal input terminal C
S, FIG. 24B shows the logic level of the positive-phase output terminal Q of the D flip-flop 13, FIG. 24C shows the clock signal CLK input to the clock signal input terminal C of the D flip-flop 18, and FIG. ) Is the logical level of the positive-phase output terminal Q of the D flip-flop 18, FIG. 24E is the output signal of the EOR circuit 23, FIG. 24F is the logical level of the output terminal Q6 of the 12-bit counter 11, FIG. (G) is E
3 illustrates an output signal of the OR circuit 24.

That is, for example, from the 65th to the 128th vertical period,
In an odd horizontal period in which the logic level of the output terminal Q6 of the 2-bit counter 11 is "1", EOR
The output signal of the circuit 24 changes from “1” to “1” every dot period.
"0" → "1" → "0" → ... → "1" → "0", and in the even horizontal period, the output signal of the EOR circuit 24 becomes "0" → "1" → " 0 "→" 1 "→ ... →
“0” → “1” is changed, and such a change is repeated.

As a result, the output terminals Q0,
Test data TDATA (D0, D1, D2, D3, D4, D) output from Q1, Q2, Q3, Q4, Q5
5) is [111111] → [000000] → [1111] every one dot period in the odd horizontal period.
11] → [000000] → ・ ・ ・ → [111111]
→→ [000000], and in the even-numbered horizontal period, [000000] → [111] every dot period.
111] → [000000] → [111111] → ...
->[000000]-> [111111], and such a change is repeated.

Therefore, the test data TDATA (D0, D1, D
2, D3, D4, D5) = [111111], test data TDATA of the first vertical line in the even horizontal period
(D0, D1, D2, D3, D4, D5) = [0000
00], the 65th to the twelfth
In a period in which the logic level of the output terminal Q6 of the 12-bit counter 11 is "1" such as an eight vertical period, as shown in FIG.
1st, 2nd, 3rd, 4th ... 63rd, 64th, 6th
, The test data TDATA (D0, D
1, D2, D3, D4, D5) = [111111],
[000000], [111111], [00000]
0] ... [111111], [000000], [1
11111], [000000], [111111]
.. Can be supplied, and in even-numbered horizontal lines, the first, second, third, fourth,... 63rd, 64th, 65th, 66th, and 67th vertical line··
・ Test data TD for each pixel electrode
ATA (D0, D1, D2, D3, D4, D5) = [0
00000], [111111], [000000],
[111111] ... [000000], [1111]
11], [000000], [111111], [00
0000].. Can be supplied, and as shown in FIG. 25B, the display surface 27 of the active matrix type liquid crystal display panel is
A checkerboard pattern in which the display polarity is opposite to the checkerboard pattern shown in (B) can be displayed.

Further, as the test pattern,
In the case of displaying a pattern, as shown in FIG. 26, the select control signal SL0 = "0", SL1 = "0", SL
By setting 2 = “1”, the selector 25 selects the input terminals XE0 to XE5.

Since the 12-bit counter 11 operates as shown in FIG. 3, in this case, the output terminals Q6, Q7, Q8, Q9,
The logic levels of Q10 and Q11 change every 64 vertical periods.
[000000] → [100000] → [01000
0] → [110000] → ... → [011111] →
[111111], and such a change is repeated.

Therefore, the output terminal Q of the selector 25
0, Q1, Q2, Q3, Q4, Q5, test data TDATA (D0, D1, D2, D3, D4,
D5) is [000000] → every 64 vertical periods
[100000] → [010000] → [11000
[0111] → [011111] → [111111], and such a change is repeated.

As a result, as shown in FIG. 27A, the 1st to 64th frames, the 65th to 128th frames, and the 1st to 64th frames
29th to 192nd frame, 193rd to 256th frame ... 3969 to 4032th frame, 4033th to
In the 4096th frame, the test data TDATA (D0, D1, D2,
D3, D4, D5) = [000000], [10000
0], [010000], [110000] ... [0
2711] and [111111] can be supplied, and as shown in FIG. 27B, the gray scale voltage is displayed on the display surface 27 of the active matrix type liquid crystal display panel every 64 vertical periods. Can be changed to display the entire solid pattern.

When the output signals output to the output terminals Q6 to Q11 of the 12-bit counter 11 are inverted, the direction of the gradation change is reversed from that of the solid pattern shown in FIG. 27B. A solid pattern on the entire surface can be displayed.

As described above, according to the first embodiment of the present invention, a horizontal stripe pattern, a vertical stripe pattern, a horizontal gray scale pattern, a vertical gray scale pattern, a vertical gray scale pattern, and a checkered pattern are used as test patterns on an active matrix type liquid crystal display panel. Since a pattern and a solid pattern can be selectively displayed, a display tester that generates test data necessary to display a test pattern can be eliminated, and it is easy and inexpensive. A display test of an active matrix liquid crystal display panel can be performed.

Second Embodiment FIG. 28 to FIG. 51 The second embodiment of the present invention is similar to the first embodiment of the present invention shown in FIG. The test data generator shown is provided, and the other components are configured in the same manner as the first embodiment of the present invention.

Here, the test data generating section shown in FIG. 28 can optionally select test data TDATA (D0-D
As 5), test data for displaying a vertical stripe pattern, a horizontal stripe pattern, a vertical gray scale pattern, a horizontal gray scale pattern, a full solid pattern, and a checkered pattern is generated.

In FIG. 28, reference numeral 30 denotes test data TDATA.
(D0 to D5), A0 to A8 are address signal input terminals, and Q0 to Q5 are test data TD.
A data output terminal to which ATA (D0 to D5) is output.

FIG. 29 is a diagram showing the contents of the test data TDATA (D5 to D0) stored in the ROM 30. In this figure, the addresses A8 to A0 and the test data D5 to D5 are shown.
D0 is indicated by a hexadecimal number.

That is, in the ROM 30, the address 0
00h to 03Fh are portions for storing vertical stripe pattern display data as test data.
0h, 001h, 002h ..., 03Eh, 03Fh
00h, 3Fh, 00h ... 00 respectively
h and 3Fh are stored.

Addresses 040h to 07Fh are used to store horizontal stripe pattern display data as test data. Addresses 040h, 041h, and 042
h ... 07Eh and 07Fh are 00h,
.. 00h, 3Fh are stored.

Addresses 080h to 0BFh are used to store vertical grayscale pattern display data as test data.
81h, 082h ... 0BEh and 0BFh store 00h, 01h, 02h ... 3Eh and 3Fh, respectively.

Addresses 0C0h to 0FFh are used to store horizontal grayscale pattern display data as test data.
.. 0FEh and 0FFh store 00h, 01h, 02h... 3Eh and 3Fh, respectively.

Addresses 100h to 13Fh are used to store the entire solid pattern display data as test data.
102h ... 13Eh and 13Fh have 0 respectively.
0h, 01h, 02h... 3Eh, 3Fh are stored.

Addresses 140h to 17Fh are used to store checkerboard pattern display data as test data. Addresses 140h, 141h, 142
h ... 17Eh and 17Fh are 00h,
.. 00h, 3Fh are stored.

In FIG. 28, reference numerals 31, 32 and 33 denote test pattern selection signals SL3 and SL supplied from the outside.
4 and SL5 are test pattern selection signal input terminals to which the test pattern selection signals SL3 and S5 are input.
FIG. 9 is a diagram illustrating a relationship between L4 and SL5 and a test pattern to be selected.

That is, in this example, when the test pattern selection signal SL3 = "0", SL4 = "0", and SL5 = "0", the vertical stripe pattern is selected as the test pattern. Become.

The test pattern selection signal SL3 =
When “1”, SL4 = “0”, and SL5 = “0”, the horizontal stripe pattern is selected as the test pattern.

The test pattern selection signal SL3 =
When “0”, SL4 = “1”, and SL5 = “0”, the vertical grayscale pattern is selected as the test pattern.

The test pattern selection signal SL3 =
When “1”, SL4 = “1”, and SL5 = “0”, the horizontal gray scale pattern is selected as the test pattern.

The test pattern selection signal SL3 =
When “0”, SL4 = “0”, and SL5 = “1”, the entire solid pattern is selected as the test pattern.

The test pattern selection signal SL3 =
When “1”, SL4 = “0”, and SL5 = “1”, the checkered pattern is selected as the test pattern.

In FIG. 28, reference numeral denotes a clock signal CLK, a horizontal synchronizing signal HS, and a horizontal synchronizing signal HS.
This is a timer circuit that outputs a divide-by-2 horizontal synchronization signal 2HS divided by 2, a vertical synchronization signal VS, and a 64-divided vertical synchronization signal 64VS obtained by dividing the vertical synchronization signal VS by 1/64.

FIG. 31 is a waveform diagram showing the clock signal CLK, the horizontal synchronization signal HS, the divided-by-2 horizontal synchronization signal 2HS, the vertical synchronization signal VS, and the divided-by-64 vertical synchronization signal 64VS output from the timer circuit 34. .

In FIG. 28, reference numeral 35 designates the clock signal CLK, the horizontal synchronizing signal HS or the vertical synchronizing signal VS output from the timer circuit 34 by using the test pattern selection signals SL3, SL4 and SL5 as a select control signal. FIG. 32 is a diagram showing the relationship between the test pattern selection signals SL3, SL4, and SL5 and the signal output from the selector 35.

That is, the selector 35 sets the test pattern selection signal SL3 = “0”, SL4 = “0”, and SL5 =
“0” or SL3 = “0”, SL4 = “1”, SL5 =
“0” or SL3 = “1”, SL4 = “0”, SL5 =
In the case of "1", the clock signal CLK is selected, and the test pattern selection signal SL3 = "1", SL4 = "0", S
L5 = “0” or SL3 = “1”, SL4 = “1”, S
When L5 = “0”, the horizontal synchronization signal HS is selected, and the test pattern selection signal SL3 = “0”, SL4 =
The configuration is such that the vertical synchronization signal VS is selected when “0” and SL5 = “1”.

In FIG. 28, reference numeral 36 denotes a test pattern selection signal SL3, SL4, or SL5 as a select control signal, and a divide-by-2 horizontal synchronization signal 2HS or a divide-by-64 vertical synchronization signal 64VS output from the timer circuit 34. FIG. 33 is a diagram showing the relationship between test pattern selection signals SL3, SL4, and SL5 and signals output from the selector 35.

That is, the selector 36 sets the test pattern selection signal SL3 = “0”, SL4 = “0”, and SL5 =
“0” or SL3 = “1”, SL4 = “0”, SL5 =
“0” or SL3 = “0”, SL4 = “1”, SL5 =
“0” or SL3 = “1”, SL4 = “1”, SL5 =
“0” or SL3 = “0”, SL4 = “0”, SL5 =
In the case of “1”, the 64 divided vertical synchronization signal 64VS is selected, and the test pattern selection signal SL3 = “1”, SL4 =
When “0” and SL5 = “1”, the divide-by-2 horizontal synchronization signal 2HS is selected.

In FIG. 28, reference numeral 37 denotes a selector 3
5 and the horizontal synchronizing signal H
S or the vertical synchronization signal VS is input to the counted signal input terminal IN as a counted signal, and the divided-by-2 horizontal synchronization signal 2HS or the divided-by-64 vertical synchronization signal 64VS output from the selector 36 is increased as an up / down control signal. / Down control signal input terminal U / D is a 6-bit up / down counter, and Q0 to Q5 are output terminals for outputting count values of the first to sixth bits.

The 6-bit up / down counter 37 has a 6-bit up / down counter shown in FIG.
When the logic level of the up / down control signal input terminal U / D is set to "0", the counter 12 performs an up-count operation, and the up / down control signal input terminal U / D When the logical level of the data is set to "1", the down-count operation is performed.

Further, in this example, an address signal generator is constituted by a timer circuit 34, a selector 35, a selector 36, and a 6-bit up / down counter 37, and a 6-bit up / down / up counter is provided. The output terminals Q0 to Q5 of the counter 37 are connected to address signal input terminals A0 to A5 of the ROM 30, respectively, and the test pattern selection signal input terminals 31 to 33 are connected to address signal input terminals A6 to A8 of the ROM 30, respectively. Have been.

In the case of using the second embodiment of the present invention having the test data generator configured as described above,
On the active matrix type liquid crystal display panel, vertical stripe pattern, horizontal stripe pattern, vertical gray scale pattern, horizontal gray scale pattern,
A solid pattern or a checkered pattern on the entire surface can be selectively displayed.

Here, when displaying a vertical stripe pattern as a test pattern, as shown in FIG. 34, a test pattern selection signal SL3 = “0”, SL4 = “0”, S
L5 = “0”.

Thus, selector 35 selects and outputs clock signal CLK, and selector 36 selects clock signal CLK.
Since the divided-by-4 vertical synchronization signal 64VS is selected and output, the 6-bit up / down counter 37
Means that the clock signal CLK is counted using the 64 divided vertical synchronization signal 64VS as an up / down control signal.

FIGS. 35 and 36 are waveform diagrams for explaining the operation in this case. FIG. 35 shows the case where the 64 divided vertical synchronizing signal 64VS = "0", and FIG. 36 shows the divided 64 vertical synchronizing signal. The case where the logic level of 64VS = "1" is shown.

FIG. 35A and FIG.
Divide-by-4 vertical synchronization signal 64VS, FIG. 35 (B), FIG. 36
(B) is a clock signal CLK, FIG. 35 (C), FIG.
(C) is an address signal input terminal A0 to A8 of the ROM 30.
35 (D) and FIG. 36 (D) show the address ADD to be accessed, and FIGS. 35 (E) and 36 (E) show the test data TDATA output from the ROM 30.

The address ADD shown in FIGS. 35 (D) and 36 (D) and the test data TDATA shown in FIGS. 35 (E) and 36 (E) are represented by hexadecimal numbers.

That is, as shown in FIG. 35, the 12-bit up / down counter 37 performs up-counting during the period when the divide-by-64 vertical synchronizing signal 64VS is "0". Signal input terminal A0
The logical levels of .about.A8 are as shown in FIG.
The address ADD to be accessed is 000h → 001h → 0 every dot period as shown in FIG.
... 03Fh, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 00h to 3Fh to 00h,..., 3Fh every dot period, and such changes are repeated. Will be.

Therefore, when controlling to supply the gray scale voltage corresponding to the test data at the address 000h to the pixel electrode of the first vertical line, the divided-by-64 vertical synchronization signal 64VS is set to “0”. During the period, a vertical stripe pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel, as in the case shown in FIG.

On the other hand, as shown in FIG.
Since the 6-bit up / down counter 37 counts down while the divided vertical synchronization signal 64VS is "1", the logic levels of the address signal input terminals A0 to A8 of the ROM 30 are as shown in FIG. The address ADD to be accessed is as shown in FIG.
As shown in the figure, every dot period, 03Fh → 03E
h → 03Dh →... → 000h, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 3Fh → 00h → 3Fh →... → 00h every dot period, and such a change is repeated. Will be.

Therefore, when controlling so as to supply the gray scale voltage corresponding to the test data at the address 03Fh to the pixel electrode on the first vertical line, the divided-by-64 vertical synchronization signal 64VS is set to "1". During the period, as in the case shown in FIG. 20, a vertical stripe pattern whose display polarity is opposite to that of the vertical stripe pattern shown in FIG. 18 can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

When a horizontal stripe pattern is displayed as a test pattern, as shown in FIG. 37, test pattern selection signals SL3 = “1”, SL4 = “0”, SL
5 = “0”.

In this way, the selector 35 selects and outputs the horizontal synchronizing signal HS, and the selector 36
Since the divided vertical synchronizing signal 64VS is selected and output, the 6-bit up / down counter 37
The horizontal synchronizing signal HS is counted by using the 64 divided vertical synchronizing signal 64VS as an up / down control signal.

FIGS. 38 and 39 are waveform diagrams for explaining the operation in this case. FIG. 38 shows a case where the 64 divided vertical synchronization signal 64VS = "0", and FIG. 39 shows a 64 divided vertical synchronization signal. 64VS = "1" is shown.

Here, FIGS. 38 (A) and 39 (A) show 6
38 divided vertical sync signal 64VS, FIG. 38 (B), FIG.
(B) is a horizontal synchronizing signal HS, FIG. 38 (C), FIG.
(C) is an address signal input terminal A0 to A8 of the ROM 30.
38 (D) and 39 (D) show the address ADD to be accessed, and FIGS. 38 (E) and 39 (E) show the test data TDATA output from the ROM 30.

Note that the address ADD shown in FIGS. 38 (D) and 39 (D) and the test data TDATA shown in FIGS. 38 (E) and 39 (E) are represented by hexadecimal numbers.

That is, as shown in FIG. 38, the 6-bit up / down counter 37 performs an up-count while the divided-by-64 vertical synchronizing signal 64VS is "0". Signal input terminals A0
The logical level of A8 is as shown in FIG. 38 (C), and the accessed address ADD is 040h → 041h → 042 every horizontal period as shown in FIG. 38 (D).
h →... → 07Fh, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 00h to 3Fh to 00h,..., 3Fh every horizontal period, and such changes are repeated. Will be.

Therefore, when controlling so that the gradation voltage corresponding to the test data at the address 040h is supplied to the pixel electrode on the first horizontal line, the divided-by-64 vertical synchronization signal 64VS is set to "0". 13, a horizontal stripe pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel, as shown in FIG.

On the other hand, as shown in FIG.
Since the 6-bit up / down counter 37 counts down while the divided vertical synchronization signal 64VS is “1”, the logic levels of the address signal input terminals A0 to A8 of the ROM 30 are as shown in FIG. The address ADD to be accessed is as shown in FIG.
As shown in FIG. 7, every horizontal period, 07Fh → 07Eh
→ 07Dh →... → 040h, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 3Fh → 00h → 3Fh →... → 00h every horizontal period, and such changes are repeated. Will be.

Therefore, when controlling so that the test data at the address 07Fh is supplied to the pixel electrode on the first horizontal line, the divided-by-64 vertical synchronizing signal 64V
During the period when S is “1”, the display surface 27 of the active matrix type liquid crystal display panel is
A horizontal stripe pattern in which the display polarity is reversed from that of the horizontal stripe pattern shown in FIG. 13 can be displayed.

When a vertical gray scale pattern is displayed as a test pattern, as shown in FIG. 40, a test pattern selection signal SL3 = "0", SL4
= "1" and SL5 = "0".

In this way, the selector 35 selects and outputs the clock signal CLK, and the selector 36
Since the divided-by-4 vertical synchronization signal 64VS is selected and output, the 6-bit up / down counter 37
Means that the clock signal CLK is counted using the 64 divided vertical synchronization signal 64VS as an up / down control signal.

FIGS. 41 and 42 are waveform diagrams for explaining the operation in this case. FIG. 41 shows the case where the 64 divided vertical synchronization signal 64VS = "0", and FIG. 42 shows the 64 divided vertical synchronization signal. 64VS = "1" is shown.

Here, FIG. 41 (A) and FIG.
Divide-by-4 vertical synchronization signal 64VS, FIG. 41 (B), FIG. 42
(B) is a clock signal CLK, FIG. 41 (C), FIG.
(C) is an address signal input terminal A0 to A8 of the ROM 30.
41 (D) and 42 (D) show the address ADD to be accessed, and FIGS. 41 (E) and 42 (E) show the test data TDATA output from the ROM 30.

The addresses ADD shown in FIGS. 41 (D) and 42 (D) and the test data TDATA shown in FIGS. 41 (E) and 42 (E) are represented by hexadecimal numbers.

That is, as shown in FIG. 41, the 6-bit up / down counter 37 counts up during the period in which the divide-by-64 vertical synchronizing signal 64VS is "0". Signal input terminals A0
The logical level of A8 is as shown in FIG. 41 (C), and the accessed address ADD is 080h → 081h → 08 every dot period as shown in FIG. 41 (D).
... → 0BFh, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 00h to 01h to 02h to 3Fh every horizontal period, and such changes are repeated. Will be.

Therefore, when controlling so that the gray scale voltage corresponding to the test data at the address 080h is supplied to the pixel electrode of the first vertical line, the divided-by-64 vertical synchronizing signal 64VS becomes "0". , A vertical grayscale pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel, as in the case shown in FIG.

On the other hand, as shown in FIG.
Since the 6-bit up / down counter 37 counts down while the divided vertical synchronization signal 64VS is "1", the logic levels of the address signal input terminals A0 to A8 of the ROM 30 are as shown in FIG. The address ADD to be accessed is as shown in FIG.
As shown in the figure, 0BFh → 0BE every dot period
h → 0BDh →... → 080h, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 3Fh → 3Eh → 3Dh →... → 00h every dot period, and such a change is repeated. Will be.

Therefore, when controlling so that the gray scale voltage corresponding to the test data at the address 0BFh is supplied to the pixel electrode on the first vertical line, the divided-by-64 vertical synchronization signal 64VS is set to "1". 9, a vertical gray scale pattern whose display polarity is opposite to that of the vertical gray scale pattern shown in FIG. 9 is displayed on the display surface 27 of the active matrix type liquid crystal display panel, as in the case shown in FIG. be able to.

When a horizontal gray scale pattern is displayed as a test pattern, as shown in FIG. 43, a test pattern selection signal SL3 = "1", SL4
= "1" and SL5 = "0".

In this way, the selector 35 selects and outputs the horizontal synchronizing signal HS, and the selector 36
Since the divided vertical synchronizing signal 64VS is selected and output, the 6-bit up / down counter 37
The horizontal synchronization signal CLK is counted using the 64 divided vertical synchronization signal 64VS as an up / down control signal.

FIGS. 44 and 45 are waveform diagrams for explaining the operation in this case. FIG. 44 shows a case where the 64 divided vertical synchronization signal 64VS = "0", and FIG. 45 shows a 64 divided vertical synchronization signal. 64VS = "1" is shown.

Here, FIG. 44 (A) and FIG.
Divided by 4 vertical synchronization signal 64VS, FIG. 44 (B), FIG.
(B) is a horizontal synchronizing signal HS, FIG. 44 (C), FIG.
(C) is an address signal input terminal A0 to A8 of the ROM 30.
44 (D) and 45 (D) show the address ADD to be accessed, and FIGS. 44 (E) and 45 (E) show the test data TDATA output from the ROM 30.

The addresses ADD shown in FIGS. 44 (D) and 45 (D) and the test data TDATA shown in FIGS. 44 (E) and 45 (E) are represented by hexadecimal numbers.

That is, as shown in FIG. 44, while the divided-by-64 vertical synchronizing signal 64VS is "0", the 6-bit up / down counter 37 counts up and the address signal of the ROM 30 is increased. Input terminals A0 to A8
44 (C), and the address ADD to be accessed is 0C0h → 0C1h → 0C2h every horizontal period as shown in FIG. 44 (D).
→ ... → 0FFh, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 00h to 01h to 02h to 3Fh every one horizontal period, and this change is repeated. Become.

Therefore, when controlling so that the gray scale voltage corresponding to the test data at the address 0C0h is supplied to the pixel electrode of the first horizontal line, the divided-by-64 vertical synchronization signal 64VS is set to “0”. , A horizontal gray scale pattern can be displayed on the display surface 27 of the active matrix type liquid crystal display panel, as in the case shown in FIG.

On the other hand, as shown in FIG.
Since the 6-bit up / down counter 37 counts down while the divided vertical synchronization signal 64VS is "1", the logic levels of the address signal input terminals A0 to A8 of the ROM 30 are as shown in FIG. The address ADD to be accessed is as shown in FIG.
As shown in FIG. 7, every horizontal period, 0FFh → 0FEh
→ 0FDh →... → 0C0h, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 3Fh → 3Eh → 3Dh →... → 00h every horizontal period, and this change is repeated. Become.

Therefore, when controlling so that the gray scale voltage corresponding to the test data at the address 0FFh is supplied to the pixel electrode on the first horizontal line, the divided-by-64 vertical synchronizing signal 64VS becomes “1”. 7, a horizontal gray scale whose display polarity is opposite to that of the horizontal gray scale shown in FIG. 6 can be displayed on the display surface 27 of the active matrix type liquid crystal display panel, as in the case shown in FIG.

When a solid pattern is displayed as a test pattern, as shown in FIG. 46, test pattern selection signals SL3 = "0", SL4 = "0", SL
5 = “1”.

In this way, the selector 35 selects and outputs the vertical synchronizing signal VS, and the selector 36
Since the divided vertical synchronizing signal 64VS is selected and output, the 6-bit up / down counter 37
The vertical synchronization signal VS is counted using the divided-by-64 vertical synchronization signal 64VS as an up / down control signal.

FIGS. 47 and 48 are waveform diagrams for explaining the operation in this case. FIG. 47 shows a case where the 64 divided vertical synchronization signal 64VS = "0", and FIG. 48 shows a 64 divided vertical synchronization signal. 64VS = "1" is shown.

Here, FIGS. 47 (A) and 48 (A)
FIG. 47 (B), FIG. 48
(B) is a vertical synchronization signal VS, FIG. 47 (C), FIG.
(C) is an address signal input terminal A0 to A8 of the ROM 30.
47 (D) and FIG. 48 (D) show the address ADD to be accessed, and FIGS. 47 (E) and 48 (E) show the test data TDATA output from the ROM 30.

The address ADD shown in FIGS. 47 (D) and 48 (D) and the test data TDATA shown in FIGS. 47 (E) and 48 (E) are represented by hexadecimal numbers.

That is, as shown in FIG. 47, the 6-bit up / down counter 37 performs up-counting while the divided-by-64 vertical synchronizing signal 64VS is "0". Signal input terminals A0
The logical level of A8 is as shown in FIG. 47 (C), and the accessed address ADD is 100h → 101h → 102 every vertical period as shown in FIG. 47 (D).
h →... → 13Fh, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 00h to 01h to 02h to 3Fh every vertical period, and such changes are repeated. Will be.

Therefore, the 64 divided vertical synchronization signal 64V
During the period when S is “0”, the display surface 27 of the active matrix type liquid crystal display panel is
It is possible to display an entire solid pattern in which the gradation is changed every 64 vertical periods.

On the other hand, as shown in FIG.
Since the 6-bit up / down counter 37 counts down while the divided vertical synchronization signal 64VS is “1”, the logic levels of the address signal input terminals A0 to A8 of the ROM 30 are as shown in FIG. The address ADD to be accessed is as shown in FIG.
As shown in the figure, 13Fh → 13Eh every one vertical period.
→ 13Dh →... → 100h, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 3Fh → 3Eh → 3Dh →... → 00h every vertical period, and such a change is repeated. Will be.

Therefore, the 64 divided vertical synchronization signal 64V
During the period in which S is "1", a solid pattern which reverses the direction of gradation change from the solid pattern shown in FIG. 27 can be displayed on the display surface 27 of the active matrix type liquid crystal display panel.

When a checkerboard pattern is displayed as a test pattern, as shown in FIG. 49, a test pattern selection signal SL3 = "1", SL4 = "0", SL4
5 = “1”.

Thus, selector 35 selects and outputs clock signal CLK, and selector 36 selects clock signal CLK.
Since the divided horizontal synchronization signal 2HS is selected and output, the 6-bit up / down counter 37
The clock signal CLK is counted using the divided horizontal synchronization signal 2HS as an up / down control signal.

FIGS. 50 and 51 are waveform diagrams for explaining the operation in this case. FIG. 50 shows a case where the 2/2 horizontal synchronization signal 2HS = "0", and FIG. 51 shows a 2/2 horizontal synchronization signal. 2HS = "1" is shown.

Here, FIG. 50 (A) and FIG. 51 (A)
Divided horizontal synchronization signal 2HS, FIG. 50 (B), FIG. 51 (B)
50 (C) and FIG. 51 (C) are the logic levels of the address signal input terminals A0 to A8 of the ROM 30, FIG. 50 (D) and FIG. 51 (D) are the addresses ADD to be accessed, FIG. (E) and FIG.
The test data TDATA output from 0 is shown.

The address ADD shown in FIGS. 50 (D) and 51 (D) and the test data TDATA shown in FIGS. 50 (E) and 51 (E) are represented by hexadecimal numbers.

That is, as shown in FIG. 50, the 6-bit up / down counter 37 performs up-counting during the period when the divide-by-2 horizontal synchronization signal 2HS is "0". Signal input terminals A0 to A8
50C, and the address ADD to be accessed is 140h → 141h → 142h every horizontal period as shown in FIG. 50D.
→→→ 17Fh, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 00h to 3Fh to 00h,..., 3Fh every horizontal period, and such changes are repeated. Will be.

On the other hand, as shown in FIG. 51, the 6-bit up / down counter 37 counts down during the period when the divide-by-2 horizontal synchronization signal 2HS is "1". Address signal input terminal A of ROM 30
The logical levels of 0 to A8 are as shown in FIG. 51 (C), and the address ADD to be accessed is 17Fh → 17Eh → every one horizontal period as shown in FIG. 51 (D).
17Dh →... → 140h, and such a change is repeated.

As a result, the test data TDATA (D5 to D0) output from the ROM 30 changes from 3Fh → 00h → 3Fh →... → 0h every horizontal period.
Such a change will be repeated.

Therefore, for example, the test data TDATA (D5 to D
0) = 00h and the test data TDATA (D5 to D0) of the first vertical line in the even-numbered horizontal period is controlled to be 3Fh, as in the case shown in FIG.
Display surface 2 of active matrix type liquid crystal display panel
7, a checkerboard pattern can be displayed.

As described above, according to the second embodiment of the present invention, a vertical gray scale pattern, a horizontal gray scale pattern, a vertical stripe pattern, a horizontal stripe pattern, and a whole surface are used as test patterns on an active matrix type liquid crystal display panel. Since the solid pattern and the checkered pattern can be selectively displayed, a display tester that generates test data necessary for displaying the test pattern can be eliminated, and it is easy and inexpensive. A display test of an active matrix liquid crystal display panel can be performed.

[0194]

As described above, according to the present invention, an active matrix type liquid crystal display panel is provided with a test data generator for generating test data necessary for displaying a test pattern. In addition, a display tester for generating test data necessary for displaying a test pattern can be dispensed with, and a display test of an active matrix type liquid crystal display panel can be easily performed at a low cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a test data generator provided in the first embodiment of the present invention.

FIG. 3 is a waveform diagram illustrating an operation of a 12-bit counter included in a test data generation unit included in the first embodiment of the present invention.

FIG. 4 is a waveform diagram showing an operation of a 6-bit up / down counter provided in a test data generator provided in the first embodiment of the present invention.

FIG. 5 is a circuit diagram for explaining a case where a horizontal gray scale pattern is displayed using the first embodiment of the present invention.

FIG. 6 is a diagram for explaining a case where a horizontal gray scale pattern is displayed using the first embodiment of the present invention.

FIG. 7 is a diagram for explaining a case where a horizontal grayscale pattern is displayed using the first embodiment of the present invention.

FIG. 8 is a circuit diagram for explaining a case of displaying a vertical gray scale pattern using the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a case where a vertical grayscale pattern is displayed using the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a case where a vertical grayscale pattern is displayed using the first embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating a case where a horizontal stripe pattern is displayed using the first embodiment of the present invention.

FIG. 12 is a waveform diagram for explaining an operation when the logical level of the output terminal Q6 of the 12-bit counter is “0” when displaying a horizontal stripe pattern using the first embodiment of the present invention; is there.

FIG. 13 is a diagram illustrating a case where a horizontal stripe pattern is displayed using the first embodiment of the present invention.

FIG. 14 is a waveform diagram for explaining an operation when the logical level of the output terminal Q6 of the 12-bit counter is “1” when displaying a horizontal stripe pattern using the first embodiment of the present invention; is there.

FIG. 15 is a diagram illustrating a case where a horizontal stripe pattern is displayed using the first embodiment of the present invention.

FIG. 16 is a circuit diagram illustrating a case where a vertical stripe pattern is displayed using the first embodiment of the present invention.

FIG. 17 is a waveform chart for explaining the operation when the logical level of the output terminal Q6 of the 12-bit counter is “0” when displaying the vertical stripe pattern using the first embodiment of the present invention. is there.

FIG. 18 is a diagram illustrating a case where a vertical stripe pattern is displayed using the first embodiment of the present invention.

FIG. 19 is a waveform chart for explaining the operation when the logical level of the output terminal Q6 of the 12-bit counter is “1” when displaying the vertical stripe pattern using the first embodiment of the present invention. is there.

FIG. 20 is a diagram illustrating a case where a vertical stripe pattern is displayed using the first embodiment of the present invention.

FIG. 21 is a circuit diagram illustrating a case where a checkered pattern is displayed using the first embodiment of the present invention.

FIG. 22 is a waveform diagram for explaining an operation when the logic level of the output terminal Q6 of the 12-bit counter is “0” when a checkered pattern is displayed using the first embodiment of the present invention. is there.

FIG. 23 is a diagram illustrating a case where a checkered pattern is displayed using the first embodiment of the present invention.

FIG. 24 is a waveform chart for explaining the operation when the logic level of the output terminal Q6 of the 12-bit counter is “1” when a checkered pattern is displayed using the first embodiment of the present invention. is there.

FIG. 25 is a diagram illustrating a case where a checkered pattern is displayed using the first embodiment of the present invention.

FIG. 26 is a circuit diagram for explaining a case of displaying an entire solid pattern using the first embodiment of the present invention.

FIG. 27 is a diagram for explaining a case of displaying an entire solid pattern using the first embodiment of the present invention.

FIG. 28 is a circuit diagram showing a test data generator provided in the second embodiment of the present invention.

FIG. 29 is a diagram showing stored contents of a ROM included in the second embodiment of the present invention.

FIG. 30 is a diagram showing a relationship between a test pattern selection signal and a selected test pattern in the second embodiment of the present invention.

FIG. 31 is a waveform chart showing signals output by a timer circuit provided in the second embodiment of the present invention.

FIG. 32 is a diagram illustrating a relationship between a test pattern selection signal and a signal output from a selector that outputs a counted signal according to the second embodiment of the present invention.

FIG. 33 is a diagram illustrating a relationship between a test pattern selection signal and a signal output from a selector that outputs an up / down control signal in the second embodiment of the present invention.

FIG. 34 is a circuit diagram illustrating a case where a vertical stripe pattern is displayed using the second embodiment of the present invention.

FIG. 35 is a waveform diagram illustrating a case where a vertical stripe pattern is displayed using the second embodiment of the present invention.

FIG. 36 is a waveform diagram illustrating a case where a vertical stripe pattern is displayed using the second embodiment of the present invention.

FIG. 37 is a circuit diagram illustrating a case where a horizontal stripe pattern is displayed using the second embodiment of the present invention.

FIG. 38 is a waveform diagram illustrating a case where a horizontal stripe pattern is displayed using the second embodiment of the present invention.

FIG. 39 is a waveform diagram for explaining a case where a horizontal stripe pattern is displayed using the second embodiment of the present invention.

FIG. 40 is a circuit diagram for describing a case of displaying a vertical grayscale pattern using the second embodiment of the present invention.

FIG. 41 is a waveform diagram illustrating a case where a vertical grayscale pattern is displayed using the second embodiment of the present invention.

FIG. 42 is a waveform chart for explaining a case of displaying a vertical grayscale pattern using the second embodiment of the present invention.

FIG. 43 is a circuit diagram illustrating a case where a horizontal gray scale pattern is displayed using the second embodiment of the present invention.

FIG. 44 is a waveform diagram for explaining a case where a horizontal gray scale pattern is displayed using the second embodiment of the present invention.

FIG. 45 is a waveform diagram illustrating a case where a horizontal gray scale pattern is displayed using the second embodiment of the present invention.

FIG. 46 is a circuit diagram for explaining a case of displaying a full-area solid pattern using the second embodiment of the present invention.

FIG. 47 is a waveform chart for explaining a case of displaying an entire solid pattern using the second embodiment of the present invention.

FIG. 48 is a waveform chart for explaining a case of displaying an entire solid pattern using the second embodiment of the present invention.

FIG. 49 is a circuit diagram illustrating a case where a checkered pattern is displayed using the second embodiment of the present invention.

FIG. 50 is a waveform diagram illustrating a case where a checkered pattern is displayed using the second embodiment of the present invention.

FIG. 51 is a waveform diagram illustrating a case where a checkered pattern is displayed using the second embodiment of the present invention.

FIG. 52 is a circuit diagram showing a main part of an example of a conventional digital data driver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register part 2 Data register part 3 Latch part 4 Decoder part 5 Gradation voltage generation part 6 Selector part 9 Test data generation part

Claims (6)

[Claims] 1. A pixel electrode is formed in a matrix and connected between a data line, a scan line, and the data line and the pixel electrode, and conduction and non-conduction are controlled via the scan line. A liquid crystal display panel formed by filling liquid crystal between a first substrate having a switching element formed thereon and a second substrate having a common electrode common to all pixel electrodes. A data driver for a liquid crystal display panel for applying a gradation voltage to a line, comprising: a test data generator for generating test data necessary for displaying a test pattern on the liquid crystal display panel; A gray-scale voltage generating unit that generates a gray-scale voltage of a plurality of gray-scale voltages; A data driver for a liquid crystal display panel, comprising: 2. The test data generator according to claim 1, further comprising: a plurality of types of test data necessary for displaying a plurality of types of test patterns based on a vertical synchronization signal, a horizontal synchronization signal, or a clock signal supplied from outside. 2. The liquid crystal display panel according to claim 1, further comprising: a test data generation unit that generates a test data; and a test data selection unit that selects one type of test data from the plurality of types of test data. Data driver. 3. The test data generating section generates test data for inverting the display polarity every predetermined time for all or a part of the plurality of types of test data. Item 3. A data driver for a liquid crystal display panel according to item 2. 4. The test data generating section stores a plurality of types of test data necessary for displaying a plurality of types of test patterns at successive addresses for each data unit to be output. A test data storage unit in which test data to be output is specified by a test pattern selection signal supplied from the storage unit, and an address area of the test data storage unit based on the test pattern selection signal. An address signal generating unit for generating an address signal for addressing an address area in which test data corresponding to a test pattern specified by the test pattern selection signal is stored. Item 2. A data driver for a liquid crystal display panel according to item 1. 5. The data driver for a liquid crystal display panel according to claim 4, wherein said address signal generation section includes addressing direction switching means for switching an addressing direction at predetermined time intervals. 6. The plurality of types of test patterns include a horizontal gray scale pattern, a vertical gray scale pattern, a horizontal stripe pattern, a vertical stripe pattern, a checkered pattern, or a solid pattern. A data driver for a liquid crystal display panel according to claim 2, 3, 4, or 5.