JPH1065682A - Monitor device for atm communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer monitor control information stored in a memory at high speed. SOLUTION: A monitor device is provided with an address prediction part 5 which previously predicts an address in the OAM processing memory 2 of OAM information (monitor control information) which CPU 4 reads at the access and a cache memory 7 where OAM information which is read from the OAM processing memory 2 based on the predicted address at the idle time of access to the OAM processing memory 2 by an OAM processing circuit 1. OAM information being a read object can immediately be read from the cache memory 7 by CPU 4 so as to transfer it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
The present invention relates to a monitoring device that stores and processes monitoring control information in a memory in a communication device, and particularly relates to a method of transferring stored monitoring control information.

[0002]

2. Description of the Related Art In an ATM communication apparatus, an STM (Synchronous
ous Transfer Mode: other monitoring information collected by the synchronous transmission mode), VP with a combination of types 2 ²⁸ (Virtual P
ath) / VC (Virtual Channel) monitoring information (OAM (Ope
ration and maintenance information), the ability to collect a huge number of monitoring information is required.

As a method of collecting monitoring information in the ATM communication device, there is, for example, a method described in the 1996 IEICE General Conference B-1005 (Takada, Yoshida, Nara et al.). FIG. 9 shows a configuration example of a system to which this method is applied. 9, alarm information detected and processed by the alarm processing unit 72 of the line unit 71 accommodating the line is sent to the monitoring unit 74 via the communication processing unit 73, and is collectively transmitted to the alarm processing unit 75 of the monitoring unit 74. After being collected and processed there,
It is sent to the host device via 78. Collection of alarm information requires real-time processing. In the above method, in order to improve the number of pieces of alarm information that can be collected and processed in a unit time, the monitoring unit 74 and the line unit 71 are individually provided with a high-performance CP.
U76 and 77 (32-bit configuration) are arranged, and the processing of VP / VC alarm information is performed by the CPU 77 of the line unit 71, and the processing of HW alarm information is performed by the CPU 75 of the monitoring unit 74, thereby dispersing the processing. ing.

[0004] Processing (OAM) such as the alarm processing section 72 in FIG.
The OAM processing unit that performs the processing) has an OA based on the processing result.
Some stores and manages M information in a memory. FIG.
FIG. 1 shows a configuration example of such an OAM processing unit. In FIG. 10, the OAM processing circuit 1 sets the received input cell 112 to V
The output cell 113 is transmitted after the PI conversion, and the OAM processing memory 2 is accessed and the OAM processing memory 2 stored therein is accessed.
The information is updated based on the contents of the input cell 112. CPU 4
The OAM processing memory 2 is accessed, OAM information is read, and the value stored in the addition operation memory 10 is updated. The bus interface 3 is an OAM
This is for arbitrating access between the AM processing circuit 1 and the CPU 4, and preferentially processes access from the OAM processing circuit 1. FIG. 11 shows an example of arbitration of the bus interface 3 in one cell cycle (about 2.8 μs). In FIG. 10, a period 91- during which the OAM processing of the OAM processing circuit 1 is performed.
During 1,91-2 (the waiting period T), the access of the CPU 4 is restricted. For example, CP at time 93 included in period 91-1
If U4 requests access, the access will take place during period 9
It will be performed after the time t1 when 1-1 has elapsed.

[0005]

In the above prior art,
Since the access of the CPU 4 is delayed at the maximum by the waiting period T, and the delay occurs every time the access of the CPU 4 is performed, it takes a long time to read and transfer the OAM information when collecting the OAM information.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to transfer monitoring control information in an ATM communication device at a higher speed.

[0007]

In order to achieve the above object, a monitoring device according to the present invention comprises a first memory in which a plurality of pieces of monitoring control information are stored and a communication content of an own ATM communication device. Processing means for storing or updating monitoring control information in the first memory, wherein the processing means reads monitoring control information from the first memory during a period when the processing means does not access the first memory; A monitoring device of an ATM communication device, wherein the monitoring control information requests reading of the monitoring control information by designating address information associated with the monitoring control information, and the monitoring control device specifies the reading at the time of a read request. Address prediction means for predicting address information before the designation, and monitoring corresponding to the predicted address information read from the first memory in accordance with the prediction A second memory in which the control information is stored; and, in response to a read request from the monitor control means, the monitor control information associated with the address information designated by the monitor control means is stored in the second memory. If you have
Access means for reading the monitoring control information from the second memory.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a supervisory control system of an ATM communication device according to an embodiment of the present invention. In FIG. 1, a supervisory control system includes an OAM processing circuit 1 for performing OAM processing,
An OAM processing memory 2 for storing AM information and the like;
A bus interface 3 for arbitrating access to the AM processing memory 2; a CPU 4 for performing processing such as OAM information calculation processing in accordance with a program; an address prediction unit 5 for predicting an address specified by the CPU 4 when reading OAM information; An address calculation unit 6 for converting the address thus specified and the address designated by the CPU 4 into a real address of the OAM processing memory 2;
A cache memory 7 for storing a plurality of pieces of OAM information of the AM processing memory 2, a cache memory management unit 8 for managing the state of the cache memory 7, a cache target determination unit 9 for determining a memory to be accessed by the CPU 4, an OAM And an addition operation memory 10 for storing a result of the information operation process.

The OAM processing circuit 1 performs VPI conversion on the input cell 112 to output the output cell 113 and performs OAM processing according to the information detected from the input cell 112. In this OAM processing, OAM is performed based on the detected information.
The OAM information stored in the AM processing memory 2 is updated. For example, if a user cell loss is detected, OA
The detected number is accumulated in the user cell loss number stored in the M processing memory 2. The bus interface 3 processes the access from the OAM processing circuit 1 preferentially.

The CPU 4 accesses the cache memory 7 or the OAM processing memory 2 to read the OAM information. The cache target determination unit 9 determines whether the access target of the CPU 4 is the OAM processing memory 2 or the cache memory 7 based on the address specified by the CPU 4 at the time of access. The address specified by CPU4 is OA
When the M processing memory 2 is targeted (non-cache target), the OAM information stored in the OAM processing memory 2 is read. If the address specified by the CPU 4 targets the cache memory 7 (cache target), the predicted address predicted for the current access by the CPU 4 is compared with the address actually specified by the CPU 4 in the current access. When the addresses match, OAM information is read from the cache memory 7 (cache hit). If the addresses do not match,
The OAM information is read from the AM processing memory 2 (cache unhit).

FIG. 2 shows a processing flow of the OAM information reading processing in the monitoring control system. The process of reading the OAM information is divided into a non-cache target case, a cache hit in a cache hit, and a cache unhit in a cache target. Hereinafter, a process of reading the OAM information for each of these cases will be described.

(1) Case of non-cache target In this monitoring control system, first, the cache target determination unit 9
Address 101 specified by CPU 4 when reading monitoring information
Then, it is determined whether or not the access target of the CPU 4 is the cache memory 7 (step 11). If it is determined that the cache is not targeted, the address calculation unit 6
The address 101 (102) specified by the PU 4 is converted into the real address 103 of the OAM processing memory 2 and output to the bus interface 3. Then, the address prediction unit 5 instructs the bus interface 3 to read the OAM information by the control signal 104 (step 16). In response to this instruction, the bus interface 3 determines whether or not the OAM information has been transferred between the OAM processing circuit 1 and the OAM processing memory 2 based on the control signal 105, and the transfer has been performed. If so, this determination is repeated (step 17). And OAM
If it is determined that the information has not been passed,
The control signal 106 including the real address 103 is given to the OAM processing memory 2 to read the OAM information (step 1).
8) Write "0" to the storage location of the read OAM information in the OAM processing memory 2 (step 19).

(2) In the case of a cache unhit When the cache target determination unit 9 determines that the access target of the CPU 4 is the cache memory 7, the address prediction unit 5 sets the OA currently stored in the cache memory 7
The CPU predicts the predicted address
It is determined whether or not there is an address corresponding to the address designated at the time of access (step 12).

If there is no matching predicted address, the control signal 107 notifies the cache memory management unit 8 of a cache unhit. The cache memory management unit 8 that has received the notification
It is checked whether or not OAM information is stored in the memory (step 14). If OAM information is present, "0" is written therein and the cache memory 7 is cleared (step 15). In a state where data is not stored in the cache memory 7, the process proceeds to step 16 described in the non-cache target process, performs address conversion and bus control, reads OAM information from the OAM processing memory 2,
Write "0" at the read position (steps 16-1
9). The monitoring system is configured so that cache unhit does not occur in normal operation.

(3) In the case of a cache hit The access target of the CPU 4 is the cache memory 7 (step 11, Yes), and the predicted address predicted for the OAM information currently stored in the cache memory 7 is the CP address.
If there is an address that matches the address specified by U4 (step 12, Yes), the address predicting unit 5 stores the address 101 specified at the time of access by the CPU 4 into the cache memory 7.
Control signal containing the real address
The OAM information is read from the cache memory 7 by 110 (step 13).

In the above processing, the OA read by the CPU 4
Since the M information is transferred from the OAM processing memory 2 to the cache memory 7 in advance, the CPU 4 can read the OAM information without waiting when the access is to be cached and a cache hit occurs.

Next, a process of writing the OAM information stored in the OAM processing memory 2 into the cache memory 7 will be described.

FIG. 3 shows an example of a processing flow of a writing process to the cache memory 7. In the processing shown in the figure, first, the address prediction unit 5
In accordance with 00, the CPU 4 predicts in advance the address specified when reading the OAM information, and sends the predicted address 102 to the address calculation unit 6 (step 21). The address calculation unit 6
The transmitted predicted address 102 is converted into a real address 103 of the OAM processing memory 2 and sent to the OAM processing memory 2. Next, the address prediction unit 5 instructs the bus interface 3 to read the OAM information by the control signal 104 (step 22). In response to this instruction, the bus interface 3
It is determined based on the control signal 105 whether or not OAM information has been transferred between the AM processing circuit 1 and the OAM processing memory 2. If the transfer has been performed, this determination is repeated (step 23). ). When it is determined that the OAM information has not been transferred, the control signal 106 is sent to the OAM processing memory 2 in parallel with the real address 103 to read the OAM information, and the read OAM information is cached. Writing to the memory 7 (step 24). Then, "0" is written to the storage position of the read OAM information in the OAM processing memory 2 (step 25). The cache memory management unit 8 checks whether or not there is a free area in which the OAM information is not stored in the cache memory 7.
(Step 26) If there is a free area, the control signal 111 notifies the address prediction unit 5 that new OAM information can be stored (Steps 26 and 21). This allows
The above processing (steps 21 to 26) is repeated. Thus, the writing process based on the predicted address is repeated until the cache memory 7 is filled with the OAM information. Then, when there is no more free space in the cache memory 7 (step 26, No), the end of writing is notified to the address prediction unit 5 by the control signal 111.

FIG. 4 shows an example of an address map of the OAM processing memory 2. As shown in FIG.
The VP constituting the OAM information 33 is stored in the AM processing memory 2.
In addition to the alarm 31 and the VP performance alarm 32, an HW alarm, a device failure alarm, and the like are stored. The VP alert 31 includes information such as VP-AIS, VP-FERF, and VP-ERR for each of the 4096 connections, and the VP performance alert 32 indicates the number of user cell losses and the number of user cell errors for each connection. , The number of error bits, the number of OAM cell losses, and the like. Since the total number of OAM information 33 is represented by the product of the number of connections and the type of information, the access frequency of the CPU 4 becomes extremely high. Therefore, in the present monitoring system, the processing of the CPU 4 is set so that the OAM information 33 is read out as a cache target, and the transfer of the OAM information 33 is speeded up.

FIG. 5 shows that the CPU 4 collects the OAM information 33.
FIG. 4 is a diagram showing an example of an address designated by a and an address predicted by an address prediction unit 5. In FIG. 5, (1), (2), (3),
.., (20480) indicate the order in which the OAM information is read. The address specified by the CPU 4 when collecting the OAM information 33 is determined based on the type of information as shown in FIG. 5A, or determined based on the connection number as shown in FIG. 5B. In some cases. The CPU 4 executes the above 2
5 is specified by the address prediction switching signal 100. According to the specification, information of (1), information of (2), information of (2), and information of (2) shown in FIG. Next, the OAM information 33 is read in the order of the information (3). The address prediction unit 5 also predicts an address in the reading order specified by the address prediction switching signal 100, and
Output the same predicted address as the address specified by the CPU 4 prior to the specification by the CPU 4. As a result, a continuous cache hit becomes possible, and the transfer of the OAM information becomes faster. The address prediction switching signal 100 can be arbitrarily switched by the administrator.

FIG. 6 shows an OAM implemented by the CPU 4.
It shows an example of the processing flow of the information calculation processing.
In this example, OA is performed based on the information type shown in FIG.
The figure shows a case where M information is read and n (type) OAM information is processed for each VPI (connection) to which a number from “0” to “4095” is assigned.

The CPU 4 first sets “0” at time t, OA
"1" is set for the M information type k and "0" is set for the number VPI (steps 41 to 43). Next, the processing target OAM information specified by k and VPI is stored in the cache memory.
7 (or the OAM processing memory 2), and reads out the firmware operation information to be processed at the previous time (t-1) from the addition operation memory 10 in which the firmware operation information of the operation result of this processing is stored (step S1). 44,45). The reading of the OAM information at this time is performed by the processing described with reference to FIG. It should be noted that the order of reading the OAM information and the firmware operation information does not matter. Next, CPU4
Performs the addition processing of the read firmware operation information and the OAM information, and stores the processing result as the firmware operation information at the current time t (steps 46 and 47). And the number VP
I is incremented (step 48), and VPI = 40
The processing of the above steps 44 to 48 is repeated until 95 is reached (step 49). Then, processing of all numbers VPI for the OAM information type k is performed, and when VPI = 4095 (step 49, No), the CPU 4 sets the OAM information type k
Is incremented, and the above processing is repeated for a new OAM information type k (steps 50 and 51). Thus,
The OAM information calculation processing of all OAM information types at time t is completed in one second. Next, the CPU 4 increments the time t and repeats the above processing (steps 52 and 5).
3). Then, when t = 900 seconds (= 15 minutes) (Step 53, No), the OAM information calculation processing ends.

FIG. 7 shows OA in the OAM information calculation processing.
FIG. 9 is a sequence diagram illustrating an example of a procedure for reading M information. In the example of FIG. 7, first, when the CPU 4 reads the first OAM information A from the OAM processing memory 2, under the control of the address prediction unit 5 and the cache memory management unit 8, the second and subsequent OAM information B, C and D are OAM processing memory 2
Is transferred to the cache memory 7. For this reason, CP
U4 is continuously set in the OAM processing circuit 1 while the OAM processing is being performed (waiting period T).
Information B, C, and D can be read from the cache memory 7.

In the above processing, the OAM information can be read from the cache memory 7 without waiting, so that the CPU 4 can execute the OAM information arithmetic processing at a high speed. In addition, like the system described in FIG.
When transferring the collected OAM information to other circuit units,
For the same reason, the monitoring system can execute the transfer at high speed.

The VP performance alarm 32 includes OAM information for calculating the total number of errors in cells and the like in 15 minutes, and the presence / absence of an error (regardless of the number) every second to detect the presence of an error in 15 minutes. There is OAM information for calculating the total number.
The OAM information for calculating the total number of errors is accumulated from "0" every second in the OAM processing memory 2, and the accumulated value is 15
The total is accumulated on the addition operation memory 10 900 times per minute.
On the other hand, the OAM information for calculating the total number of detected errors is also OA.
In the M processing memory 2, it is accumulated from "0" every second,
Even when the accumulated value is 2 or more, the addition operation memory 10 increases the value by “1”. It is also possible to configure so that the total number of errors is obtained on the OAM processing memory 2 without storing "0" which is performed every time the OAM information is read from the OAM processing memory 2.

In the monitoring system, as described above, the VP
There are cases where all OAM information of I = 0 to 4095 is collected, and cases where OAM information is collected only for a specific VPI such as VPI = 0 to 255. For example, in the system described with reference to FIG.
255 OAM information is collected, and V
A use form that allows OAM information of PI = 0 to 4095 to be collected is considered. In such a case, VPI = 0 to 2
In a monitoring system that collects 55 OAM information, VPI = 25
By predicting the addresses of OAM information of 6 to 4095 and storing them in the cache memory 7, cache unhits occur continuously. FIG. 8 shows an example of a write process to the cache memory for preventing a cache unhit in such a case. The processing in FIG.
The processing of step 20 for preventing writing to the cache memory 7 when the cache is not turned on is added to the top of the processing of FIG. CPU4 is V
When the OAM information of PI = 256 to 4095 is stored in the cache memory 7, the address prediction unit 5 is instructed to turn off the cache, and in other cases, it is instructed to turn on the cache.
As a result, the address of OAM information of VPI = 256 to 4095 is not predicted and stored in the cache memory 7, and cache unhit does not occur.

[0028]

According to the present invention, the transfer of the monitoring control information in the ATM communication device can be performed at a higher speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a monitoring control system of an ATM communication device according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an example of a process of reading OAM information in the monitoring control system.

FIG. 3 is a flowchart illustrating an example of a writing process to a cache memory in the monitoring control system.

FIG. 4 is a diagram showing an example of an address map of an OAM processing memory in the monitoring control system.

FIG. 5 is a diagram illustrating an example of address prediction at the time of reading OAM information in the monitoring control system.

FIG. 6 is a flowchart illustrating an example of OAM information calculation processing in the monitoring control system.

FIG. 7 is an example of a sequence diagram showing a procedure for reading OAM information in the processing of FIG. 6;

FIG. 8 is a flowchart illustrating another example of the write processing to the cache memory in the monitoring control system.

FIG. 9 is a diagram illustrating a configuration example of a monitoring system according to a conventional technique.

FIG. 10 is a diagram illustrating a configuration example of an OAM processing circuit according to the related art.

FIG. 11 is a diagram for explaining a delay in access timing of a CPU according to the related art.

[Explanation of symbols]

1 ... OAM processing circuit, 2 ... OAM processing memory, 3 ...
Bus interface, 4 CPU, 5 address predictor, 6 address calculator, 7 cache memory,
8: Cache memory management unit, 9: Cache target determination unit, 10: Addition operation memory, 11: Cache target determination process, 12: Cache hit determination process, 13: Cache memory read process, 14: Cache memory storage data determination process, 15: Cache memory data clear processing, 16: Address conversion / bus control processing, 17: O
AM processing determination processing, 18: OAM processing memory read processing, 19: OAM processing memory data clear processing,
20: Cache-on judgment processing, 21: Address prediction processing, 22: Address conversion / bus control processing, 23: OAM
Processing judgment processing, 24… Cache memory storage processing, 25
… Memory data clear processing for OAM processing, 26… Cache memory write judgment processing, 31… VP alarm, 32…
VP performance information, 33: OAM information, 41: time initial setting, 42: OAM information type initial setting, 43: VPI initial setting, 44: OAM information reading processing, 45: firmware operation information reading processing, 46: firmware operation processing, 47…
Firm operation information storage processing, 48 VPI increment processing, 49 VPI end judgment processing, 50 OAM information type increment processing, 51 OAM information type end judgment processing, 52 time increment processing, 53 time end judgment processing, 54 ... OAM information type end determination processing, 71 ... line section, 72 ... alarm processing section, 73 ... communication processing section, 74 ... monitoring section, 75 ... alarm processing section, 76 ... CPU, 77 ... CPU,
78: Upper interface unit, 91-1, 91-2: Time domain during OAM processing, 92: Time domain outside OAM processing, 93
... Access timing from CPU, 100 ... Address prediction switching signal, 101,102,103 ... Address control, 104 ... Access control, 105,106 ... Address control, 107 ... Access control, 108 ... Read data, 109 ... Data clear control, 110 ... Address control and Access control, 111
... write control, 112 ... input cells, 113 ... output cells,
181 ... Address control.

Claims (10)

[Claims] A first memory for storing a plurality of pieces of supervisory control information;
Processing means for storing or updating the monitoring control information in the memory, and reading the monitoring control information from the first memory while the processing means is not accessing the first memory. A monitoring device of an apparatus, wherein a monitoring control unit that requests reading of the monitoring control information by designating address information associated with the monitoring control information, and an address information that the monitoring control unit specifies at the time of a read request. Address prediction means for predicting before the designation, read from the first memory according to the prediction,
A second memory for storing monitoring control information associated with the predicted address information; and a monitoring control associated with the address information designated by the monitoring control means in response to a read request from the monitoring control means. An access unit for reading the monitoring control information from the second memory when the information is stored in the second memory; 2. The monitoring device for an ATM communication device according to claim 1, wherein said access means stores monitoring control information associated with address information designated by said monitoring control means in said second memory. The monitoring device for an ATM communication device, wherein the monitoring control information is read from the first memory when the monitoring control information is not read. 3. The monitoring device for an ATM communication device according to claim 2, wherein the address information specified by the monitoring control unit and the address information predicted by the address prediction unit are associated with the address information. An address conversion unit configured to convert monitoring control information into real address information indicating a storage position in the first memory, wherein the monitoring control information stored in the first memory is read using the real address information A characterized by
Monitoring device for TM communication devices. 4. The monitoring device for an ATM communication device according to claim 2, wherein said monitoring control means specifies that monitoring control information is read from said first memory when said reading request is issued. The monitoring device for an ATM communication device, wherein the access unit reads the monitoring control information from the first memory when the monitoring control unit designates reading from the first memory. 5. The monitoring device for an ATM communication device according to claim 2, wherein the access unit recognizes address information associated with monitoring control information stored in the second memory, and performs the monitoring. A monitoring device for an ATM communication device, characterized in that when the address information specified by the control means at the time of a read request is included in the recognized address information, it is determined that monitoring control information is stored in the second memory. 6. The monitoring device for an ATM communication device according to claim 2, wherein an additional process is performed on the monitoring control information, and when the monitoring control information is read from the first memory. And a means for storing a zero value in a storage location of the read monitoring control information in the first memory. 7. The monitoring device for an ATM communication device according to claim 2, wherein said monitoring control means reads said plurality of pieces of monitoring control information in a predetermined reading order, and said address prediction means includes said predetermined reading. The prediction of the address information is performed so that the monitoring control information is stored in the second memory in order.
Monitoring device for TM communication devices. 8. The monitoring device for an ATM communication device according to claim 7, wherein said monitoring control means converts the plurality of monitoring control information into a connection number of a communication on which the monitoring control information is updated, Alternatively, a monitoring device for an ATM communication device, wherein the reading is performed in a predetermined reading order based on the type of the monitoring control information. 9. The monitoring device for an ATM communication device according to claim 2, wherein said monitoring control is read from said first memory and stored in said second memory in accordance with a prediction by said address prediction means. A monitoring device for an ATM communication device, comprising means for restricting information to predetermined monitoring control information. 10. The monitoring device for an ATM communication device according to claim 1, wherein said monitoring control means reads said second memory from said second memory independently of access to said first memory by said processing means. The monitoring device for an ATM communication device, wherein monitoring control information is read out, and reading out of the monitoring control information from the second memory is performed faster than reading out the monitoring control information from the first memory.