JPH1065671A - Test system for atm device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect parts where a cell is lost and the cell is erroneously distributed in an ATM(asynchronous transfer mode) device with a simple constitution. SOLUTION: In a module 10 in a transmission line 200 for transmitting the ATM cell, an inter-devcie cell where a flag is on/off-controled in a prescribed position is generated in a cell generation circuit 50 and it is inserted into a test cell string through a cell insertion circuit 40. In modules 20 and 30 in a downstream, passing cells while the inter-devcie cell of off-flag is detected after the inter-device cell of the on-flag is detected is counted cell counters 60 and 70. Counted values are compared and collated one another in a test result judgment block 90 and a cell loss and an erroneous distribution of cell are identified in the modules of the non-matched parts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test system for an ATM (Asynchronous Transfer Mode) device, and more particularly to a test method for an ATM device in an ATM communication system.

[0002]

2. Description of the Related Art In a test of an ATM device, there is a test for specifying a place where a transmission cell is discarded or mis-distributed.
For example, there is a technique disclosed in JP-A-5-183573. FIG. 2 is a block diagram showing this test method.

Referring to FIG. 2, on a transmission line 200,
A test cell is transmitted from a not-shown transmitting-side ATM device. The test cell is a pseudo random (PN) for testing.
The pattern is divided into several parts, each of these divided parts is placed on a test cell, and is transmitted over the transmission line 200 in the ATM mode in that order.

In the receiving-side ATM device 201, the test cell on the transmission line 200 is detected by a test cell detection circuit 202, separated from the transmission line 200, and further disassembled.

The PN pattern synchronization detection circuit 208 has a selector 206 and a reference PN pattern generation circuit 207. The PN pattern taken out of the test cell is taken into the reference PN pattern generation circuit 207 via the B side of the selector 206. The reference PN pattern generation circuit 207 newly generates the same reference PN pattern as the PN pattern generated on the transmission side by using the acquired PN pattern.

[0006] The comparison circuit 203 compares the reference PN pattern with the PN pattern extracted from the test cell detection circuit 202 for each bit constituting the pattern.

The error bit counter 204 includes a comparator 20
The number of bits that did not match at 3 is counted. The PN pattern synchronization protection circuit 205 synchronizes the reference PN pattern generated from the reference PN pattern generation circuit 207 and the reception PN pattern by the test cell detection circuit 202 with reference to the comparison result in the comparison circuit 203. It is determined whether or not the synchronization has been established.
6 is switched to the A side.

Therefore, after that, the bit error counter 2
At 04, the test for measuring the bit error is under test.

When the number of erroneous bits increases, the synchronization is lost. The selector 206 is switched to the B side again to achieve bit synchronization.
, The bit error count is started. Therefore, based on the bit error detection result of the error bit counter 204, it is possible to detect cell discard (loss) and mis-distribution.

[0010]

SUMMARY OF THE INVENTION Conventional A shown in FIG.
In the test method of the TM device, when the cell format is changed or the bit slice processing is performed, it is difficult to perform the verification using the PN synchronization. The reason is that, for example, the so-called bit slice processing for processing half of 16-bit data in units of 8-bit data is performed due to the limit of the processing capacity of the ATM device, or the cell format is changed for the sake of simplicity. This is because it is difficult to verify the PN pattern when a change is made.

If there are a large number of ATM devices 201 to be verified, the hardware shown in FIG. 2 is required in each device, which complicates the configuration and increases the cost.

It is an object of the present invention to provide an ATM device in which bit slicing processing can be performed with a very simple and simple structure to specify a cell loss or cell misplacement.
A test system for a TM device is provided.

[0013]

According to the present invention, an ATM is provided.
A test system for an ATM device provided in a transmission line, wherein one ATM device generates an intra-device cell and
Means for sending to the TM transmission line, and means for controlling on / off of a flag assigned to a predetermined position of the cell in the device, wherein the ATM installed downstream of the one ATM device
An ATM device, comprising: an ATM device for detecting ON / OFF of a flag of a cell in the device received from the ATM transmission line, and counting cells passed between an ON flag and an OFF flag. Test system is obtained.

Further, a plurality of ATM devices installed downstream are provided, and the ATM device is characterized by having a collating means for collating the count results of each counting means of these ATM devices with each other.

The counting means has a counter which starts counting the passing cells in response to the detection of the on-flag and maintains the count value immediately before in response to the detection of the off-flag. .

A certain ATM device generates cells in the device, sets a flag at a specific position of the cell in the device, controls the flag to be turned on / off externally,
The M device can identify the cell loss and mis-delivery by counting the number of passing cells from the detection of the ON flag to the detection of the OFF flag of the cell in the device.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, ATM devices (hereinafter, referred to as modules) 10 to 30 are arranged in the cell transmission line 200. One module 10 includes a cell generation circuit 50 that generates an in-device cell, and a cell insertion circuit 40 that inserts the in-device cell into a cell line to be tested on the cell transmission line 200.

The test control block 80 includes a cell generation circuit 50
The on / off setting control is performed on a flag provided at a predetermined position of the in-device cell generated in step (1).

The cells transmitted from the module 10 are transmitted to a plurality of modules 20 and 3 located downstream of the cell transmission line 200.
(Two modules are shown in the figure, but may be three or more) and transmitted.

In these downstream modules 20 and 30, cell counters 60 and 7 for counting passing cells are provided.
0 is provided respectively. These cell counters 60 and 7
0 counts the number of cells that have passed between the ON flag and the OFF flag of the in-device cell from the module 10, respectively.

That is, when the cell generation circuit 50 of the module 10 detects that the flag of the generated cell in the device indicates ON, the counters 60 and 70 are reset to start the cell count. Then, when it is detected that the flag of the next arriving cell in the apparatus indicates OFF, the counters 60 and 70 hold the cell count value immediately before that, and the held count value is used as the test result determination block 9
0.

In the test result determination block 90, when the count values of the respective modules are collated with each other and they do not match, it is possible to specify that cell discarding or cell mis-distribution has occurred.

In the test control block 80, a cell insertion position into which an internal cell whose flag is to be turned on and an internal cell whose flag is to be turned off is previously determined. If the number of passing cells between the device cell and the OFF flag is set, regardless of the relative comparison and collation of the cell counter of each module,
The determination can be made based on a single count value.

[0025]

According to the present invention, since the number of passing cells is simply counted, the determination of cell discarding and cell mis-distribution and the identification of an abnormal location can be performed for each module even at a bit sliced location. There is an effect that it becomes possible only by providing.

There is also an effect that it is not necessary to create and transmit a cell having a PN pattern for a test.

[Brief description of the drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a system block diagram showing a conventional ATM device test system.

[Explanation of symbols]

 10, 20, 30 module 40 cell insertion circuit 50 cell generation circuit 60, 70 cell counter 80 test control block 90 test result determination block 200 cell transmission line

Claims (3)

[Claims] 1. A test system for an ATM device provided in an ATM transmission line, wherein one ATM device generates a cell in the device and sends it to the ATM transmission line; Turn on the flag assigned to the predetermined position /
Means for performing off control, wherein the ATM device installed downstream of the one ATM device detects on / off of a flag of the cell in the device received from the ATM transmission line, and detects an on flag to an off flag. A test system for an ATM device, comprising counting means for counting the number of cells that have passed through. 2. The ATM device according to claim 1, wherein a plurality of ATM devices are provided downstream of said ATM device, and said ATM device has a collating means for collating the count results of respective counting means of said ATM devices with each other. Testing system for ATM equipment. 3. The apparatus according to claim 2, wherein the counting means has a counter which starts counting the passing cells in response to the detection of the ON flag and maintains a count value immediately before the counting in response to the detection of the OFF flag. Claim 1 or 2
A test system for an ATM device as described.