JPH1065520A - Coincidence detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coincidence detection circuit in which the number of components is reduced so as to reduce the circuit area. SOLUTION: Two 1st switch circuits SC1 are connected in series between a power supply V1 and an output terminal TO. Two input signals being binary signals A, B are given respectively to the 1st switch circuit SC1 and a 1st level of the input signals A, B is used for a gate signal, which makes the switch circuit SC1 conductive. Two 2nd switch circuits SC2 are connected in parallel between two input terminals Ti1, Ti2 receiving the input signals A, B and the output terminal TO. The two 2nd switch circuits SC2 are conductive by using a 2nd level nearly equal to a power supply V1 level of the input signal received by an input terminal not connected to the 2nd switch circuits SC2 as a gate signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coincidence detection circuit mounted on various semiconductor integrated circuit devices.

[0002] In recent years, semiconductor integrated circuit devices have been required to have higher integration and larger scale. Therefore, it is necessary to reduce the number of elements and the circuit area of many coincidence detection circuits mounted on such a semiconductor integrated circuit device.

[0003]

2. Description of the Related Art FIG. 19 shows an example of a two-input EOR circuit used as a conventional coincidence detecting circuit. Input signal A
Are input to the inverter circuit 2a via the transfer gate 1b and are also input to the inverter circuit 2c.

An output signal of the inverter circuit 2c is input to the inverter circuit 2a via a transfer gate 1a. The input signal B is input to the P-channel side gate of the transfer gate 1a and the N-channel side gate of the transfer gate 1b, and is inverted by an inverter circuit 2b to be transferred to the N-channel side gate of the transfer gate 1a. The signal is input to the P channel side gate of the gate 1b. An output signal X is output from the inverter circuit 2a.

The operation of the EOR circuit configured as described above will be described. When both the input signals A and B become L level,
The transfer gate 1a becomes conductive and the transfer gate 1b becomes nonconductive. Then, the input signal A becomes the inverter circuit 2
The output signal X is inverted by c and further inverted by the inverter circuit 2a, and the output signal X becomes L level.

When the input signal A goes low and the input signal B goes high, the transfer gate 1a is turned off and the transfer gate 1b is turned on. Then, the input signal A is inverted by the inverter circuit 2a and output as the output signal X, so that the output signal X becomes H level.

When the input signal A goes high and the input signal B goes low, the transfer gate 1b is turned off and the transfer gate 1a is turned on. Then, the input signal A is inverted by the inverter circuit 2c, further inverted by the inverter circuit 2a, and output as the output signal X, so that the output signal X becomes H level.

When input signals A and B both attain an H level, transfer gate 1b conducts and transfer gate 1
a becomes non-conductive. Then, the input signal A is inverted by the inverter circuit 2a and output as the output signal X.
The output signal X becomes L level.

By the above operation, the EOR circuit operates based on the truth values shown in FIG.
The EOR logic of B is output. Therefore, the EOR circuit operates as a coincidence detecting circuit that outputs an L-level output signal X when the input signals A and B match, and outputs an H-level output signal X when they do not match.

[0010]

However, in the above-described two-input EOR circuit, each of the transfer gates 1a and 1b and each of the inverter circuits 2a to 2c are each provided with one N-type transistor.
Since it is composed of a channel MOS transistor and a P-channel MOS transistor, a total of ten MOS transistors are required.

Therefore, in a semiconductor integrated circuit in which a large number of such coincidence detecting circuits are mounted, there is a problem that a circuit area increases due to an increase in the number of transistors. An object of the present invention is to provide a coincidence detection circuit that can reduce the number of elements and contribute to a reduction in circuit area.

[0012]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, two first switch circuits SC1 are connected in series between the power supply V1 and the output terminal To. Two input signals A and B, which are binary signals, are input to the first switch circuit SC1, respectively, and the first level of the input signals A and B is made conductive as a gate signal. Two second switch circuits SC2 are connected in parallel between the two input terminals Ti1 and Ti2 to which the input signals A and B are input and the output terminal To. Each second switch circuit SC2 is enabled to conduct as a gate signal at a second level substantially equal to the power supply V1 level of an input signal input to an input terminal not connected to the second switch circuit SC2.

According to the second aspect, two N-channel MOS transistors are connected in series between the low potential side power supply and the output terminal, and the first and second input signals to which the first and second input signals are input are provided. A gate of each of the N-channel MOS transistors is connected to a terminal, and a first P-channel MOS transistor having a gate to which the first input signal is input is interposed between the second input terminal and the output terminal. , A second P-channel M having the second input signal input to a gate
An OS transistor is interposed between the first input terminal and the output terminal.

According to the third aspect, two P-channel MOS transistors are connected in series between the high potential side power supply and the output terminal, and the first and second input signals to which the first and second input signals are input are provided. A gate of each of the P-channel MOS transistors is connected to a terminal, and a first N-channel MOS transistor having the gate to which the first input signal is input is interposed between the second input terminal and the output terminal. , A second N-channel M having the second input signal input to the gate
An OS transistor is interposed between the first input terminal and the output terminal.

According to a fourth aspect of the present invention, an output based on an H level signal output from the first and second N-channel MOS transistors is provided between the first and second N-channel MOS transistors and an output terminal. An amplitude expanding circuit for expanding the amplitude of the signal is provided.

According to the present invention, an output based on an L-level signal output from the first and second P-channel MOS transistors is provided between the first and second P-channel MOS transistors and an output terminal. An amplitude expanding circuit for expanding the amplitude of the signal is provided.

According to the present invention, two P-channel MOS transistors are connected in series between the high potential side power supply and the output terminal, and the first and second input signals to which the first and second input signals are inputted. A gate of each of the P-channel MOS transistors is connected to a terminal, and a first N-channel MOS transistor having the gate to which the first input signal is input is interposed between the second input terminal and the output terminal. , A second N-channel M having the second input signal input to the gate
An OS transistor is interposed between the first input terminal and the output terminal to constitute a first coincidence detection circuit, and two N-channel MOS transistors are provided between the low potential side power supply and the output terminal.
Transistors are connected in series, the gates of the N-channel MOS transistors are respectively connected to first and second input terminals to which first and second input signals are input, and the first input signal is connected to the gate. Input first P-channel M
An OS transistor is interposed between the second input terminal and the output terminal, and a second P-channel MOS transistor having a gate to which the second input signal is input is connected to the first input terminal and the output terminal. Interposed between to constitute a second match detection circuit, the output signal of the first match detection circuit, and the output signal of the second match detection circuit to select one of the selection circuit Output enabled.

According to a seventh aspect of the present invention, the amplitude expanding circuit comprises an inverter circuit for inverting the input signal, and a feedback circuit for expanding the amplitude of the input signal based on an output signal of the inverter circuit. From the input signal and the output signal of the expansion circuit, a coincidence detection signal having the same logic as the logic of the output signal of the expansion amplitude circuit with respect to the first and second input signals is selected and output based on the additional input signal. A switch circuit was provided.

(Function) In the first aspect, the input terminals Ti1, T1
When the levels of the input signals A and B input to i2 match, the power supply V1 or the second level is output from the output terminal To, and when the levels of the input signals A and B do not match,
The first level is output.

According to the present invention, when both of the input signals input to the input terminals become H level, the N-channel MOS transistor is turned on, and an output signal of L level is output from the output terminal. When both input signals become L level,
The first and second P-channel MOS transistors are turned on, and an L-level input signal is output as an output signal. When one of the input signals is at the H level and the other is at the L level, the H-level input signal is output as an output signal.

According to the third aspect, when both of the input signals input to the input terminals are at L level, the P-channel MOS transistor is turned on, and an H level output signal is output from the output terminal. When both input signals become H level,
The first and second N-channel MOS transistors are turned on, and an H-level input signal is output as an output signal. When one of the input signals becomes H level and the other becomes L level, the L level input signal is output as an output signal.

According to the fourth aspect, the amplitude of the H level output signal is expanded by the amplitude expanding circuit. According to the fifth aspect, the amplitude of the L-level output signal is expanded by the amplitude expanding circuit.

According to the present invention, one of the output signals of the first match detection circuit and the second match detection circuit is selected and output by the selection circuit. According to the seventh aspect, based on the output signal of the coincidence detection circuit and the additional input signal, the switch circuit outputs an output signal having the same logic as the logic of the coincidence detection circuit.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 is a block diagram of an E embodying the present invention.
1 shows a first embodiment of a NOR circuit. An input terminal Ti1 to which the input signal A is input is connected to gates of an N-channel MOS transistor Tr1 and a P-channel MOS transistor Tr3. An N-channel MOS transistor Tr2 is connected between the input terminal Ti1 and the output terminal To.

The input terminal Ti2 to which the input signal B is input is
The gate of the transistor Tr2 and the gate of the P-channel MOS transistor Tr4 are connected. The input terminal T
The transistor Tr1 is connected between i2 and the output terminal To. The transistors Tr3 and Tr4 are connected to the power supply VDD and the output terminal T.
o are connected in series. Then, an output signal X is output from the output terminal To.

The operation of the ENOR circuit configured as described above will be described. When both the input signals A and B become H level, the transistors Tr1 and Tr2 are turned on and the transistors Tr3 and Tr4 are turned off.

Then, the H-level input signals A and B are output to the output terminal To via the transistors Tr1 and Tr2.
The output signal X becomes H level. When the input signal A goes high and the input signal B goes low, the transistor T
r1 is turned on, and the transistor Tr2 is turned off. Further, the transistor Tr3 is turned off, and the transistor Tr4 is turned on.

Then, the L-level input signal B is output to the output terminal To via the transistor Tr1. Therefore,
The output signal X becomes L level. When the input signal A goes low and the input signal B goes high, the transistor T
r1 is turned off and the transistor Tr2 is turned on. Further, the transistor Tr3 is turned on, and the transistor Tr4 is turned off.

Then, the L-level input signal A is output to the output terminal To via the transistor Tr2. Therefore,
The output signal X becomes L level. When both the input signals A and B become L level, the transistors Tr1 and Tr2 are turned off and the transistors Tr3 and Tr4 are turned on. Therefore, the power supply VDD is supplied to the output terminal To, and the output signal X becomes H level.

With such an operation, when the input signals A and B match, the output signal X goes to H level, and when the input signals A and B do not match, the output signal X goes to L level. Therefore, a match detection circuit for detecting the match between the input signals A and B is constituted by the ENOR circuit.

In the ENOR circuit configured as described above, the following operation and effect can be obtained. (A) When both the input signals A and B are at the H level, the input signals A and B are output as the output signal X via the transistors Tr1 and Tr2, and when both of the input signals A and B are at the L level, VDD is output as the output signal X, and when one of the input signals A and B goes to the H level and the other goes to the L level, the L-level input signal is output as the output signal X. Therefore, an ENOR circuit that outputs the ENOR logic of the input signals A and B can be configured. (B) An EOR circuit can be configured by using a total of four transistors including two N-channel MOS transistors and two P-channel MOS transistors. (C) Since the number of elements of the EOR circuit constituting the coincidence detection circuit can be reduced, the circuit area of a semiconductor integrated circuit device equipped with a large number of the coincidence detection circuits can be reduced. (Second Embodiment) FIG. 3 shows a second embodiment.
In this embodiment, an EOR circuit is configured by adding a P-channel MOS transistor Tr5 and an inverter circuit 11a to the EOR circuit of the first embodiment.

That is, the node N1 corresponding to the output terminal To of the first embodiment is connected to the inverter circuit 11a.
The output signal X is output from the inverter circuit 11a to the output terminal To.

The source of the transistor Tr5 is connected to the power supply VDD, and the drain is connected to the inverter circuit 11
a is connected to the input terminal and the gate is connected to the output terminal To.

In the EOR circuit configured as described above, the output signal of the first embodiment is applied to the inverter circuit 11a.
The inverted output signal X is output. Accordingly, an EOR logic match detection circuit is provided which outputs an L level output signal X when the input signals A and B match, and outputs an H level output signal X when the input signals A and B do not match.

With the above-described coincidence detection circuit, the following operation and effect can be obtained. (A) If the inverter circuit 11a is configured by a P-channel MOS transistor and an N-channel MOS transistor, an EOR circuit can be configured by a total of seven MOS transistors. Therefore, the number of elements of the coincidence detection circuit can be reduced, and the circuit area can be reduced. (B) When both the input signals A and B become H level and the node N1 is pulled up to the H level via the transistors Tr1 and Tr2, the level of the node N1 becomes higher than the level of the input signals A and B than the transistors Tr1 and Tr2. Although lowered by the threshold value of Tr2, the transistor Tr5 is turned on by the L-level output signal X of the inverter circuit 11a, and the node N1 is almost raised to the power supply VDD level. Therefore, the operation when both the input signals A and B are at the H level can be stabilized, and the load driving capability can be improved by the operation of the inverter circuit 11a.

(Third Embodiment) FIG. 4 shows a third embodiment. In this embodiment, the N-channel MOS transistor of the first embodiment is replaced with a P-channel MOS transistor.
EO, replacing the P-channel MOS transistor with an N-channel MOS transistor
This constitutes an R circuit.

That is, the input terminal Ti3 to which the input signal A is input is connected to the gates of the N-channel MOS transistor Tr8 and the P-channel MOS transistor Tr7.
A P-channel MOS transistor Tr6 is connected between the input terminal Ti3 and the output terminal To.

The input terminal Ti4 to which the input signal B is input is
The gate of the transistor Tr6 and the gate of the N-channel MOS transistor Tr9 are connected. The input terminal T
The transistor Tr7 is connected between i4 and the output terminal To. The transistors Tr8 and Tr9 are connected to the power supply Vss and the output terminal T
o are connected in series. Then, an output signal X is output from the output terminal To.

The operation of the EOR circuit configured as described above will be described. When both the input signals A and B become H level, the transistors Tr6 and Tr7 are turned off and the transistors Tr8 and Tr9 are turned on. Then, the output terminal To goes to the power supply Vss level, that is, the L level.

When the input signal A goes high, the input signal B
Becomes L level, the transistor Tr7 is turned off and the transistor Tr6 is turned on. Further, the transistor Tr9 is turned off, and the transistor Tr8 is turned on.

Then, the H-level input signal A is output to the output terminal To via the transistor Tr6. Therefore,
The output signal X becomes H level. When the input signal A goes low and the input signal B goes high, the transistor Tr6
Is turned off, and the transistor Tr7 is turned on. Further, the transistor Tr9 is turned on, and the transistor Tr8 is turned off.

Then, the H-level input signal B is output to the output terminal To via the transistor Tr7. Therefore,
The output signal X becomes H level. When both the input signals A and B become L level, the transistors Tr6 and Tr7 are turned on and the transistors Tr8 and Tr9 are turned off. Accordingly, the input signals A and B of L level are supplied to the output terminal To via the transistors Tr6 and Tr7, and the output signal X becomes L level.

With such an operation, when the input signals A and B match, the output signal X goes to L level, and when the input signals A and B do not match, the output signal X goes to H level. Therefore, the EOR circuit constitutes a coincidence detecting circuit for detecting the coincidence of the input signals A and B.

In the EOR circuit configured as described above,
The following operation and effect can be obtained. (A) When both input signals A and B are at L level, input signals A and B are output as output signal X via transistors Tr6 and Tr7, and when both input signals A and B are at H level, power supply When Vss is output as the output signal X, and one of the input signals A and B is at the H level and the other is at the L level, the input signal at the H level is output as the output signal X. Therefore, E which outputs EOR logic of the input signals A and B is output.
An OR circuit can be formed. (B) An EOR circuit can be configured by using a total of four transistors including two N-channel MOS transistors and two P-channel MOS transistors. (C) Since the number of elements of the EOR circuit constituting the coincidence detection circuit can be reduced, the circuit area of a semiconductor integrated circuit device equipped with a large number of the coincidence detection circuits can be reduced. (Fourth Embodiment) FIG. 5 shows a fourth embodiment. This embodiment is different from the third embodiment in that the EOR
An ENOR circuit is formed by adding an N-channel MOS transistor Tr10 and an inverter circuit 11b to the circuit.

That is, the node N2 corresponding to the output terminal To of the third embodiment is connected to the inverter circuit 11b.
The output signal X is output from the inverter circuit 11b to the output terminal To.

The source of the transistor Tr10 is connected to the power supply Vss, and the drain is connected to the inverter circuit 1
1a, and the gate is connected to the output terminal To.

In the ENOR circuit configured as described above,
The output signal of the third embodiment is applied to an inverter circuit 11
An output signal X inverted at b is output. Accordingly, a match detection circuit of ENOR logic that outputs an H-level output signal X when the input signals A and B match and outputs an L-level output signal X when the input signals A and B do not match is configured.

With the above-described coincidence detection circuit, the following operation and effect can be obtained. (A) If the inverter circuit 11b is configured by a P-channel MOS transistor and an N-channel MOS transistor, an ENOR circuit can be configured by a total of seven MOS transistors. Therefore, the number of elements of the coincidence detection circuit can be reduced, and the circuit area can be reduced. (B) When both the input signals A and B are at the L level and the node N2 is lowered to the L level via the transistors Tr6 and Tr7, the level of the node N2 is higher than the levels of the input signals A and B from the transistors Tr6 and Tr6. Although it remains at the level higher by the threshold value of Tr7, the transistor Tr10 is turned on by the H-level output signal X of the inverter circuit 11b, and the node N2 is lowered to almost the power supply Vss level. Therefore, the operation when both the input signals A and B are at the L level can be stabilized, and the load driving capability can be improved by the operation of the inverter circuit 11b. (Fifth Embodiment) FIG. 6 shows a fifth embodiment. In this embodiment, an output signal of either the ENOR circuit 12 having the same configuration as that of the first embodiment or the EOR circuit 13 having the same configuration as that of the third embodiment is controlled by a control signal C. It can be selected.

That is, the node N3, which is the output terminal of the ENOR circuit 12, is connected to the N-channel MOS transistor Tr1.
The node N4, which is connected to the output terminal To via 1 and the output terminal of the EOR circuit 13, is connected to the output terminal To via the P-channel MOS transistor Tr12. Then, the control signal C is input to the gates of the transistors Tr11 and Tr12.

With this configuration, when the control signal C goes high, the transistor Tr11 is turned on and the transistor Tr12 is turned off, so that the ENOR circuit 1
The node N3, which is the output signal of No. 2, is output from the output terminal To as the output signal X.

When the control signal C goes low, the transistor Tr11 is turned off and the transistor Tr12 is turned on, and the node N4, which is the output signal of the ENOR circuit 13, is output as the output signal X from the output terminal To. You.

In such a configuration, EOR logic and EN
In the coincidence detection circuit in which the OR logic can be selected and output by the control signal C, the same operation and effect as those of the first and third embodiments can be obtained. (Sixth Embodiment) FIG. 7 shows a sixth embodiment. This embodiment is similar to the EOR of the second embodiment.
N-channel MOS transistors Tr13, Tr16,
In this configuration, P-channel MOS transistors Tr14 and Tr15 and an inverter circuit 11c are added and controlled by input signals C1 and C2.

That is, the node N1 is input to the inverter circuit 11c via the transistor Tr13, and the output signal of the inverter circuit 11a is output from the transistor Tr1.
4 to the inverter circuit 11c.

The input signal of the inverter circuit 11c is output as the output signal X via the transistor Tr15, and the output signal of the inverter circuit 11c is
The output signal X is output via the transistor Tr16.

The input signal C1 is applied to the transistor Tr1.
3 and Tr14, and the input signal C2 is input to the gates of the transistors Tr15 and Tr16. In the majority circuit configured as described above, for example, the input signals A,
When both B become H level, the node N1 becomes H level,
The output signal of the inverter circuit 11a becomes L level.

In this state, when the input signals C1 and C2 both become H level, the transistors Tr13 and Tr16 are turned on, and the transistors Tr14 and Tr15 are turned off. Then, the input signal of the inverter circuit 11c becomes H level, the output signal becomes L level, and the output signal X becomes L level.

When both the input signals A and B are at the H level and the input signal C1 is at the H level and C2 is at the L level, the transistors Tr13 and Tr15 are turned on.
The transistors Tr14 and Tr16 are turned off. Then, the output signal X becomes H level.

When both the input signals A and B are at H level and the input signal C1 is at L level and C2 is at H level, the transistors Tr13 and Tr15 are turned off and the transistors Tr14 and Tr16 are turned on. Then, the output signal X becomes H level.

When both the input signals A and B are at the H level and the input signals C1 and C2 are at the L level, the transistors Tr13 and Tr16 are turned off, and the transistors Tr14 and Tr15 are turned on. Then, the output signal X
Becomes L level.

In such a circuit, as long as the input signals A and B match and the input signals C1 and C2 match,
The output signal X becomes L level. Therefore, one 2-input E
The OR circuit, the transistors Tr13 to Tr16, and the inverter circuit 11d can form a four-input EOR circuit, and the circuit area of the four-input EOR circuit can be reduced. (Seventh Embodiment) FIG. 8 shows a seventh embodiment. This embodiment is similar to the ENO of the fourth embodiment.
P-channel MOS transistors Tr18, Tr19 in the R circuit
, N-channel MOS transistors Tr17 and Tr20, and an inverter circuit 11d, and are controlled by input signals C3 and C4.

With such a configuration, it is possible to add the same functions and effects as those of the sixth embodiment to the fourth embodiment. That is, one ENOR circuit,
Transistors Tr17 to Tr20 and inverter circuit 11d
Thus, a four-input ENOR circuit can be configured. (Eighth Embodiment) FIG. 9 shows an eighth embodiment. This embodiment is different from the second embodiment in that the inverter circuits 11e to 11h and the transfer gates 12a to 12d
And control is performed by the input signals C5 and C6.

The node N1 is connected to the input terminal of the inverter circuit 11g via the transfer gate 12a, and further connected to the inverter circuit 1g via the transfer gate 12c.
1h is connected to the input terminal.

The output signal of the inverter circuit 11a is:
The input terminal of the inverter circuit 11g is connected via a transfer gate 12b, and the output terminal of the inverter circuit 11g is connected to the inverter circuit 11g via a transfer gate 12d.
h is connected to the input terminal. Then, an output signal X is output from the inverter circuit 11h.

The input signal C5 is supplied to the transfer gate 12
a of the N-channel side gate and P of the transfer gate 12b
Input to the channel side gate. Further, the input signal C
5 is inverted by the inverter circuit 11e, and the P-channel side gate of the transfer gate 12a and the transfer gate 1
It is input to the N-channel side gate of 2b.

The input signal C6 is supplied to the transfer gate 12
c on the P-channel side and N on the transfer gate 12d.
Input to the channel side gate. Further, the input signal C
6 is inverted by the inverter circuit 11f, and the N-channel side gate of the transfer gate 12c and the transfer gate 1
Input to 2d P-channel side gate.

With such a configuration, the input signals C5, C
6 both attain the H level, the transfer gates 12a, 12a
d conducts, and 12b and 12c become non-conductive. Also,
When the input signal C5 goes high and the input signal C6 goes low, the transfer gates 12a and 12c are turned on and the transfer gates 12b and 12d are turned off. When the input signal C5 goes low and the input signal C6 goes high, the transfer gates 12a and 12c become nonconductive and the transfer gates 12b and 12b
12d conducts. When the input signals C5 and C6 both become L level, the transfer gates 12a and 12d become non-conductive, and the transfer gates 12b and 12c become conductive.

With such an operation, the same operation as in the sixth embodiment can be performed, and a four-input EOR circuit can be configured by the operation of the last-stage inverter circuit 11h. (Ninth Embodiment) FIG. 10 shows a ninth embodiment. In this embodiment, the inverter circuit 11e of the seventh embodiment is replaced by a latch circuit 13a, and an output signal X is output from the transistors Tr19 and Tr20 via a latch circuit 13b.

With such a configuration, in addition to the operation and effect of the seventh embodiment, the output signal X can be operated at full amplitude between the power supply VDD and the power supply Vss by the operation of the latch circuit 13b. Becomes (Tenth Embodiment) FIG. 11 shows a tenth embodiment. This embodiment is similar to the EOR of the second embodiment.
Circuits are connected in two stages in series.

That is, the output signal X1 of the first EOR circuit 14a that outputs the EOR logic of the input signals A and B is input as an input signal to the second EOR circuit 14b, and the second EOR circuit 14b has The input signal C7 is input. The output signal X is output from the second EOR circuit 14b.

With such a configuration, the output signal X1 of the first EOR circuit 14a which takes the EOR logic of the input signals A and B, and the EOR logic of the input signal C7 are output from the second EOR circuit 14b to the output signal X2. Can be output as (Eleventh Embodiment) FIG. 12 shows an eleventh embodiment. This embodiment shows a specific configuration of the inverter circuit used in each of the above embodiments. Generally, a CMOS inverter circuit is used as the inverter circuit,
In order to further improve the load driving capability, such a B
An iCMOS configuration is employed.

That is, the input signal IN is a P-channel MO
The signal is input to the gates of the S transistor Tr21 and the N channel MOS transistor Tr22. The transistor Tr2
1 has its source connected to the power supply VDD and its drain connected to the resistor R1.
Is connected to the drain of the transistor Tr22. The source of the transistor Tr22 is connected to a power supply Vss via a resistor R2.

The drain of the transistor Tr21 is N
It is connected to the base of a PN transistor Tr23, and the collector of the transistor Tr23 is connected to the power supply VDD. The emitter of the transistor Tr23 is connected to the output terminal To and the collector of the NPN transistor Tr24.

The base of the transistor Tr24 is connected to the source of the transistor Tr22, and the emitter is connected to the power supply Vss. The drain of the transistor Tr22 is connected to the output terminal To.

The inverter circuit configured as above is
The output stage is composed of NPN transistors Tr23 and Tr24. A bipolar transistor generally has a higher current driving capability than a MOS transistor if the area is the same.
Therefore, by using this inverter circuit, the load drive capability of each of the above embodiments can be improved. (Example of Use of the Match Detection Circuit) (1) FIG. 13 shows an example of a 4-bit UP counter using the EOR circuit shown in the above embodiment.

The flip-flop circuits FF1 to FF4 are
A clock signal CK is input, and each output signal Q is output as 4-bit output signals Q1 to Q4. In the flip-flop circuit FF1, the output signal XQ is
Is entered as In the flip-flop circuit FF2,
An output signal X of the EOR circuit 15a is input as data D, and the EOR circuit 15a
It outputs EOR logic of the output signal XQ of F1 and the output signal XQ of flip-flop circuit FF2.

In the flip-flop circuit FF3, EOR
An output signal X of the circuit 15b is input as data D, and the EOR circuit 15b outputs the data D to the flip-flop circuits FF1 and FF1.
An EOR logic of the NAND logic signal of the output signal Q of the FF2 and the output signal XQ of the flip-flop circuit FF3 is output.

In the flip-flop circuit FF4, EOR
The output signal X of the circuit 15c is input as data D, and the EOR circuit 15c is connected to the flip-flop circuits FF1 to FF1.
An EOR logic of the NAND logic signal of the output signal Q of the FF3 and the output signal XQ of the flip-flop circuit FF4 is output.

The flip-flop circuits FF1 to FF1
The clear signal CLR is input to the FF4, and when the clear signal CLR is input, each flip-flop circuit FF
Output signals Q1 to Q4 of 1 to FF4 are all reset to 0.

In the 4-bit UP counter thus configured, each of the flip-flop circuits FF1 to FF4 outputs the data D as the output signal Q based on the rising of the clock signal CK.

Then, the NAND circuit and the EOR circuit 15
a to 15c, a 4-bit output signal Q that sequentially counts up the number of rises of the clock signal CK
1 to Q4 are output.

In such a counter circuit, the circuit area can be reduced by using the EOR circuit described in the above embodiment. (2) FIG. 14 shows an example of a two-input half adder using the EOR circuit of the second embodiment.

The input signals A and B are supplied to the inverter circuit 16
The signals are input to the EOR circuit 17 via the a and 16b, and are also input to the NOR circuit 18. Then, the carry-out signal Co is output from the NOR circuit 18.

In the adder configured as described above, when the input signals A and B become "0, 0", the output signal X becomes "0",
The carry-out signal Co becomes "0". Input signal A,
When B becomes "1,0" or "0,1", the output signal X becomes "1" and the carry-out signal Co becomes "0".

When the input signals A and B become "1,1", the output signal X becomes "0", but the carry-out signal Co becomes "1". Therefore, an adder for adding the input signals A and B can be configured. (3) FIG. 15 shows a comparison circuit using the EOR circuit of the second embodiment, and shows 2-bit input signals A2 and A
1 is a circuit for comparing the magnitude of input signals B2 and B1 of 2 bits.

The signal A2 of the upper bit of each input signal
B2 is input to the EOR circuit 17, and the EOR circuit 17
Is input to the OR circuit 19a. The upper bit signal A2 is supplied to the inverter circuit 16d via the inverter circuit 16d.
The upper bit signal B2 is input to the AND circuit 20b, and is input to the NAND circuit 20b.

The lower bit signal A1 is supplied to the OR circuit 19b.
And the lower bit signal B1 is input to the OR circuit 19b via the inverter circuit 16c. The output signal of the OR circuit 19b is
is input to a. Output signals of the OR circuit 19a and the NAND circuit 20b are input to the NAND circuit 20a,
Output signal X is output from NAND circuit 20a.

In the comparison circuit configured as described above, when the upper bit signals A2 and B2 are both "1" or "0", the output signal of the EOR circuit 17 becomes L level. At this time, one of the input signals of the NAND circuit 20b is at the L level.
The output signal b becomes H level.

In this state, when the lower bit signal B1 becomes "1" and A1 becomes "0", both the input signals of the OR circuit 19b become L level, and the output signal of the OR circuit 19b becomes L level. .

Then, since both the input signals of OR circuit 19a are at L level, the output signal of OR circuit 19a is at L level and output signal X of NAND circuit 20a is at H level.
Level.

When the lower bit signal B1 becomes "0" and A1 becomes "1" with respect to the same upper bit signal,
Since both the input signals of the OR circuit 19b are at the H level, the output signal of the OR circuit 19b is at the H level.

Then, the output signal of OR circuit 19a goes high and the output signal of NAND circuit 20a goes low. Also, when the lower bit signals A1 and B1 both become "1" or "0" with respect to a similar upper bit signal, one of the input signals of the OR circuit 19b becomes H level, so that the OR circuit 19b Becomes H level.

Then, the output signal of OR circuit 19b goes high and the output signal of NAND circuit 20a goes low. On the other hand, when one of the upper bit signals A2 and B2 becomes "1" and the other becomes "0", the output signal of the EOR circuit 17 becomes H level. Then, the output signal of the OR circuit 19a becomes H level regardless of the output signal of the OR circuit 19b.

In this state, when the upper bit signal A2 becomes "0" and B2 becomes "1", the input signals of the NAND circuit 20b both become H level and the NAND circuit 20b
Is at the L level. Then, the output signal X of the NAND circuit 20a becomes H level.

The signal A2 of the upper bit is "1" and B
When 2 becomes "0", the input signals of the NAND circuit 20b are both at the L level, and the output signal of the NAND circuit 20b is at the H level. Then, the input signals of NAND circuit 20a are both at H level, and output signal X is at L level.

By the operation described above, this comparison circuit allows the input signals A1, A2, B1, B2 to output A1, A2 <
When they are B1 and B2, they output an H-level output signal X,
When A1, A2 ≧ B1, B2, the circuit operates to output an L-level output signal. (4) FIG. 16 shows a known multiplication circuit using the half adder shown in FIG. The upper bit signal A2 of the 2-bit input signals A2 and A1 is input to AND circuits 21d and 21b, and the lower bit signal A1 is input to the AND circuits 21a and 21b.
21c.

The upper bit signal B2 of the 2-bit input signals B2 and B1 is input to AND circuits 21d and 21c, and the lower bit signal B1 is input to the AND circuits 21a and 21c.
b.

The output signal X1 is output from the AND circuit 21a, and the output signals of the AND circuits 21b and 21c are input to the half adder 22a as input signals a1 and a2. The output signal x of the half adder 22a is output as the output signal X2 of the higher order bit of the output signal X1, and the carry-out signal co is input to the half adder 22b.
Is entered as

The output signal of the AND circuit 21d is input to the half adder 22b as an input signal a2. The output signal x of the half adder 22b is the output signal X2
And the carry-out signal co is output as the most significant bit output signal X4.

With such a configuration, 4-bit output signals X4 to X1 obtained by multiplying 2-bit input signals A2, A1 and B2, B1 are output. (5) FIG. 17 shows a multiplication and addition circuit using the half adder shown in FIG. 14 and the full adder 23 shown in FIG.

The full adder shown in FIG. 18 is obtained by adding a NOR circuit 24 to the circuit shown in FIG. And
The input signals a1 and a2 are input to the EOR circuit 25a via the inverter circuits 16e and 16f, and the EOR circuit 25b
Is supplied with the output signal of the EOR circuit 25a and the carry-in signal ci via the inverter circuit 16g.

The inverter circuits 16e to 16g
Is input to the NOR circuit 24, and the NOR circuit 24
Circuit 24 outputs carry-out signal co. Therefore, the output signal x of the EOR circuit 25b and the NOR circuit 2
4 generates a 2-bit output signal obtained by adding the input signals a1 and a2 and the carry-in signal ci.

In FIG. 17, input signals A2, A1, B
2, B1, C2, and C1 are 2-bit signals. The input signal C1 is supplied to the half adder 22c by the input signal a.
Entered as 1. The input signal A1 is input to AND circuits 21e and 21g, and the input signal B1 is
The signals are input to the D circuits 21e and 21f.

The input signal A2 is supplied to an AND circuit 21f,
21h, and the input signal B2 is input to an AND circuit 2
1g and 21h. Further, the input signal C2
Is input to the full adder 23b as the carry-in signal ci.

The output signal of the AND circuit 21e is input to a half adder 22c as an input signal a2.
The output signal x of 2c is output as the output signal X1 of the least significant bit. The carry-out signal co of the half adder 22c is input to the full adder 23a as a carry-in signal ci.

The output signal of the AND circuit 21f is input as an input signal a1 to the full adder 23a.
The output signal of the circuit 21g is supplied to the full adder 23a by the input signal a.
Entered as 2.

The output signal x of the full adder 23a is output as the output signal X2 of the upper bit of the output signal X1, and the carry-out signal co of the full adder 23a is input to the full adder 23b as the input signal a1. Is done.

The output signal of the AND circuit 21h is input to the full adder 23b as an input signal a2. And
The output signal x of the full adder 23b is output as the output signal X3 of the upper bit of the output signal X2,
Is the output signal X of the most significant bit
4 is output.

In the multiplying and adding circuit thus configured, the 4-bit output signals X4 to X4 obtained by adding the input signals C2 and C1 to the multiplied values of the input signals A2 and A1 and the same B2 and B1.
X1 is generated.

[0109]

As described in detail above, the present invention can provide a coincidence detecting circuit which can reduce the number of elements and contribute to a reduction in circuit area.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment.

FIG. 4 is a circuit diagram showing a third embodiment.

FIG. 5 is a circuit diagram showing a fourth embodiment.

FIG. 6 is a circuit diagram showing a fifth embodiment.

FIG. 7 is a circuit diagram showing a sixth embodiment.

FIG. 8 is a circuit diagram showing a seventh embodiment.

FIG. 9 is a circuit diagram showing an eighth embodiment.

FIG. 10 is a circuit diagram showing a ninth embodiment.

FIG. 11 is a circuit diagram showing a tenth embodiment.

FIG. 12 is a circuit diagram showing an eleventh embodiment.

FIG. 13 is a circuit diagram showing a 4-bit UP counter using an EOR circuit.

FIG. 14 is a circuit diagram showing a 2-bit 2-input half adder.

FIG. 15 is a circuit diagram showing a 2-bit 2-input comparator.

FIG. 16 is a circuit diagram showing a 2-bit 2-input multiplier.

FIG. 17 is a circuit diagram showing a 2-bit 2-input multiplication and 2-bit adder.

FIG. 18 is a circuit diagram showing a full adder used in FIG. 17;

FIG. 19 is a circuit diagram showing a conventional example.

FIG. 20 is an explanatory diagram showing operation logic of a conventional example.

[Explanation of symbols]

 SC1 first switch circuit SC2 second switch circuit V1 power supply To output terminal A, B input signal Ti1, Ti2 input terminal

Claims (7)

[Claims] 1. Two first switch circuits are connected in series between a power supply and an output terminal, and two input signals, which are binary signals, are input to the first switch circuits, respectively.
The first level of the input signal is made conductive as a gate signal, and two second switch circuits are connected in parallel between two input terminals to which the input signal is input and the output terminal, and A coincidence detection circuit characterized in that the second switch circuit is capable of conducting as a gate signal a second level substantially equal to the power supply level of an input signal input to an input terminal not connected to the second switch circuit. . 2. An N-channel MOS transistor is connected in series between a low-potential-side power supply and an output terminal, and said first and second input terminals receive first and second input signals. The gates of the respective N-channel MOS transistors are connected to each other, and a first P-channel MOS transistor having the gate inputted with the first input signal is interposed between the second input terminal and the output terminal. A coincidence detection circuit, wherein a second P-channel MOS transistor having a gate inputted with two input signals is interposed between the first input terminal and the output terminal. 3. Two P-channel MOS transistors are connected in series between a high-potential-side power supply and an output terminal, and said first and second input terminals receive first and second input signals. The gates of the respective P-channel MOS transistors are connected to each other, and a first N-channel MOS transistor having the gate inputted with the first input signal is interposed between the second input terminal and the output terminal. A coincidence detecting circuit, wherein a second N-channel MOS transistor having a gate to which two input signals are input is interposed between the first input terminal and the output terminal. 4. The first and second N-channel MOS transistors are connected between an output terminal and the first and second N-channel MOS transistors.
4. The coincidence detecting circuit according to claim 3, further comprising an amplitude expanding circuit for expanding an amplitude of an output signal based on an H level signal output from the channel MOS transistor. 5. The first and second P-channel MOS transistors are connected between an output terminal and the first and second P-channel MOS transistors.
3. The coincidence detecting circuit according to claim 2, further comprising an amplitude expanding circuit for expanding an amplitude of an output signal based on an L level signal output from the channel MOS transistor. 6. Two P-channel MOS transistors are connected in series between a high potential side power supply and an output terminal, and said first and second input terminals receive first and second input signals. The gates of the respective P-channel MOS transistors are connected to each other, and a first N-channel MOS transistor having the gate inputted with the first input signal is interposed between the second input terminal and the output terminal. A second N-channel MOS transistor having a gate inputted with the second input signal is interposed between the first input terminal and the output terminal to constitute a first match detection circuit, Two N-channel MOs between output terminals
S transistors are connected in series, the gates of the N-channel MOS transistors are respectively connected to first and second input terminals to which first and second input signals are inputted, and the first input signal is gated. The first P-channel MOS transistor input to the first input terminal is interposed between the second input terminal and the output terminal, and the second P-channel MOS transistor inputting the second input signal to the gate is connected to the first P-channel MOS transistor. A second match detection circuit is configured by being interposed between the input terminal of the first match detection circuit and the output terminal of the second match detection circuit. A match detection circuit characterized in that the selection is made possible by a selection circuit. 7. The amplitude expansion circuit, comprising: an inverter circuit for inverting the input signal thereof; and a feedback circuit for expanding the amplitude of the input signal based on an output signal of the inverter circuit. A switch circuit that selects and outputs a coincidence detection signal having the same logic as the logic of the output signal of the enlarged amplitude circuit with respect to the first and second input signals based on the additional input signal, of the input signal and the output signal. The coincidence detection circuit according to claim 4, wherein the coincidence detection circuit is provided.