JPH1065182A - Semiconductor device, manufacturing methods of semiconductor integrated device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a MOS-type transistor of SOI structure without using an SOI substrate. SOLUTION: An element active region 13, composed of a channel forming region 13a which is constricted in the widthwise direction of a gate, a source region 13b and a drain region 13c which extend in the lengthwise direction of a gate respectively and surrounded with an element isolating region 12 of insulating oxide film, is formed on a P-type silicon semiconductor substrate 11. A gate electrode 15 is formed on the element isolating region 12 and the channel forming region 13a of the element active region 13 on the P-type silicon semiconductor substrate 11, through the intermediary of a gate insulating oxide film 14. A lower insulating layer 12a formed of the same insulating oxide film is the element isolating region 12 is formed only in a region of the semiconductor substrate 11 under the channel forming region 13, located under the gate electrode 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS transistor having an SOI structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices, 50
Large-scale integrated circuits (= LSI) in which more than 100,000 transistors are integrated have been developed. This high integration is indispensable for high-speed technologies such as parallel arithmetic processing and the like.
The degree of acceleration has been increasing with the increase in the functions of. However, power consumption increases as the number of elements increases, so that low power consumption is strongly demanded.

The most effective technique for reducing the power consumption of an LSI is to lower the power supply voltage in order to achieve a low leakage current. Design rule from 0.35μm to 0.5
In the generation up to μm, the conventional power supply voltage of 5 V to 3 V has been adopted, but it is predicted that the voltage will be further reduced. However, since the reduction in the power supply voltage lowers the driving capability of the transistor, the scaling of the transistor must be performed in order to compensate for the reduction and to maintain the conventional high-speed trend.

In the scaling of the transistor, the reduction of the gate length has long been the most important parameter for speeding up. However, the scaling of the threshold voltage has become a major issue due to the reduction of the power supply voltage. come. Conventionally, the threshold voltage of a silicon-based MOS transistor has been set to about 0.6V. This value is
Since it is relatively small compared to the power supply voltage, it hardly changes in each generation. However, for example, dry cell 1
When the power supply voltage is reduced to the proper level, that is, about 1.5 V, the ratio of the threshold voltage to the power supply voltage becomes very large. Since the saturation current value of the transistor is proportional to the square of the difference between the power supply voltage and the threshold voltage,
Threshold voltage scaling is essential.

The threshold voltage is an important parameter representing the sub-threshold characteristic of a MOS transistor, and has a strong correlation with the off-leak current.
As shown in FIG. 3, it can be seen that the off-leak current increases drastically as the threshold voltage decreases. This is a fatal injury in portable equipment and means that the threshold voltage cannot be simply reduced. Thus, there is a demand for a technique in which the off-leak current does not increase even if the threshold voltage is lowered for speeding up.

A promising technique for solving this problem is SOI (= Silicon on Insu).
later).

[0007] SOI has a feature that by forming a buried layer made of an oxide film in a silicon substrate, the spread of a depletion layer from a drain diffusion layer can be suppressed. Therefore, the impurity concentration of the channel region immediately below the gate electrode in the semiconductor substrate can be reduced, and as a result, the slope of the sub-threshold characteristic can be increased. For example, normal MOS
In the type transistor, the subthreshold coefficient which is the reciprocal of the subthreshold characteristic is 80 mV / dec to 90 mV / dec.
In contrast to mV / dec, the SOI transistor is reduced to about 65 mV / dec, so that the threshold voltage can be reduced without increasing off-leakage current.

[0008]

The conventional SOI substrate manufacturing method includes a SIMOX method in which oxygen is injected into the substrate to directly form a buried oxide film in the substrate, and a method using a silicon substrate and an oxide film substrate. A wafer bonding method or the like formed by bonding is used.

However, the SIMOX method has a problem that oxygen implanted remains in the upper silicon layer (SOI) or damage such as lattice defects occurs in the crystal due to the implanted oxygen. The wafer bonding method
There is a problem that it is difficult to control the thickness of the SOI film. In addition, both the SIMOX method and the wafer bonding method
There is a problem that a leak current occurs between the source and the drain due to an interface state generated at the interface between the buried oxide film and the SOI, and the electrical characteristics of the transistor deteriorate.

Further, a transistor using an SOI substrate has a problem that a potential breakdown occurs between a source diffusion layer and a channel region due to injected holes, and a kink phenomenon easily occurs. Further, the SOI substrate itself is very expensive.

Thus, it can be seen that realizing an LSI using an SOI substrate has many problems.

The present invention has been made in view of the above problems, and has as its object
MO having SOI structure without using SOI substrate
An object is to realize an S-type transistor.

[0013]

In order to achieve the above-mentioned object, the present invention is to form an under-channel insulating layer serving as a buried oxide film only in a region below a channel region in a semiconductor substrate.

A semiconductor device according to the present invention includes a semiconductor substrate having a source region and a drain region formed at an interval from each other, and a gate electrode formed between the source region and the drain region on the semiconductor substrate. A lower channel insulating layer formed below a channel region formed below the gate electrode, wherein the lower channel insulating layer is spaced apart from element isolation regions located on both sides in the gate length direction. Is formed.

[0015] According to the semiconductor device of the present invention, the under-channel insulating layer formed below the channel region formed below the gate electrode is spaced apart from the element isolation regions located on both sides in the gate length direction. Because it is formed to put
When a gate bias is applied, the expansion of the depletion layer in the channel region from the drain region side is suppressed, so that the time for forming a channel in the channel region is reduced.

In the semiconductor device of the present invention, it is preferable that the lower channel insulating layer is formed so as to connect the channel region to a region below the lower channel insulating layer in the semiconductor substrate.

In this case, the insulating layer below the channel is
Since the channel region is formed so as to connect to a region below the channel lower insulating layer in the semiconductor substrate,
Even if an interface state is formed at the interface between the semiconductor layer forming the semiconductor substrate and the insulating layer below the channel, no leak current flows between the source and the drain. Further, since the injected holes can flow to the lower part of the semiconductor substrate, a potential breakdown is less likely to occur between the source or drain region and the channel region.

A semiconductor integrated device according to the present invention includes a first semiconductor device and a second semiconductor device formed on one semiconductor substrate, and the first semiconductor device is mounted on one semiconductor substrate. A first gate electrode formed on a semiconductor substrate, and a first channel formation region formed under the first gate electrode and narrowed in a gate width direction, and a first channel electrode extending in a gate length direction. An interval is provided between a first element active region including one source region and a first drain region and element isolation regions located on both sides in the gate length direction in a region below the first channel formation region. And a lower semiconductor layer formed as described above.
A second gate electrode formed on one semiconductor substrate;
A second channel forming region formed on one semiconductor substrate and extending in the gate length direction below the second gate electrode and having a length in the gate width direction larger than the first channel forming region; And a second element active region composed of a source region and a second drain region.

According to the semiconductor integrated device of the present invention, in the first semiconductor device, an interval is provided between the element isolation regions located on both sides in the gate length direction in a region below the first channel formation region. In this case, the time required for forming a channel in the channel region is reduced. On the other hand, the second semiconductor device has a second channel formation region whose length in the gate width direction is larger than the first channel formation region, so that the current driving capability is higher than that of the first semiconductor device. growing.

According to the method of manufacturing a semiconductor device of the present invention, there is provided a mask for masking, on a semiconductor substrate, a channel forming region constricted in a gate width direction and an element active region including a source region and a drain region extending in a gate length direction, respectively. Forming a pattern, and performing etching so that the semiconductor substrate is largely removed toward the lower portion of the semiconductor substrate using the mask pattern, so that a region below the channel formation region in the semiconductor substrate is formed. Forming an opening that opens in the gate width direction;
Forming an insulating film below the channel by filling the opening in the semiconductor substrate with an insulating film, and forming an element isolation region made of an insulating film around the element active region; Forming a gate electrode.

According to the method of manufacturing a semiconductor device of the present invention,
In order to provide an under-channel insulating layer by filling an insulating film in an opening formed by etching in a region below a channel forming region below a gate electrode inside a semiconductor substrate,
When a gate bias is applied, the insulating layer below the channel suppresses the spread of the depletion layer from the drain region side generated in the channel region, so that the time for forming a channel in the channel region is reduced.

In the method for manufacturing a semiconductor device according to the present invention,
Preferably, the plane orientation of the semiconductor substrate is (100), and the etching is wet etching.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view of an N-channel MOS transistor of a semiconductor device according to a first embodiment of the present invention. On a semiconductor substrate 11 made of P-type silicon, the periphery is made of an insulating oxide film. A channel forming region 13 surrounded by the element isolation region 12 and narrowed in the gate width direction.
a and an element active region 13 including a source region 13b and a drain region 13c extending in respective regions in the gate length direction. A gate electrode 15 is formed on the element isolation region 12 and the channel formation region 13 a of the element active region 13 on the semiconductor substrate 11 via a gate insulating oxide film 14.

FIG. 2A shows a mask pattern of the semiconductor device according to this embodiment. Reference numeral 50 denotes a channel forming region 50a and a source region 50b which are narrowed in the gate width direction.
And a drain region 50c, and a mask pattern 51 for a gate electrode.

FIGS. 3A to 3C show a cross-sectional structure of the semiconductor device according to the present embodiment. FIG. 3A shows a cross-sectional structure taken along line II of FIG. 1, that is, a cross-sectional structure in the gate length direction. 1B shows the cross-sectional configuration along the line II-II in FIG. 1, that is, the cross-sectional configuration of the source region 13b in the gate width direction, and FIG. 3C shows the cross-sectional configuration along the line III-III in FIG. 4 shows a cross-sectional configuration in a gate width direction of a channel forming region 13a below an electrode 15. Here, in FIGS. 3A to 3C, the same members as those shown in FIG.

As shown in FIG. 3A, the semiconductor substrate 11
The element active region 13 is formed in a so-called reverse tapered shape in which the lower side of the semiconductor substrate 11 is narrowed, and the region below the channel forming region 13a located below the gate electrode 15 is formed on both sides in the gate length direction. The element isolation region 1 is formed with a space between the element isolation region 12 and the element isolation region 1.
Insulating layer under channel 1 made of insulating oxide film of the same material as 2
2a is formed. On the other hand, as shown in FIG. 3B, the source region 13b in the element active region 13 has
Element isolation regions 12 are integrally formed at both ends on the gate width direction side, and a channel lower insulating layer is not formed below the source region 13b. Further, as shown in FIG. 3C, the cross-sectional shape of the channel forming region 13a in the element active region 13 in the gate width direction has an inverted triangular shape having an apex on the lower side of the semiconductor substrate 11, The lower channel insulating layer 12a is filled between the semiconductor substrate 11 and the inverted triangular top of the channel forming region 13a.

Here, the channel forming region 50 in the element active region mask pattern 50 shown in FIG.
The length a in the gate length direction is reflected in the length in the gate length direction of the insulating layer 12a below the channel in the element isolation region 12 shown in FIG.

In the present application, a region in the MOS transistor in which the gate electrode 15 and the element active region 13 (13a in this embodiment) overlap each other is referred to as a channel region.

As described above, according to the present embodiment, only the region under the channel formation region 13a located under the gate electrode 15 in the element active region 13 of the semiconductor substrate 11 has a channel-under-insulation layer made of an insulation oxide film. Since the gate 12a is formed, when a gate bias is applied,
Since the spread of the depletion layer generated in the channel region is suppressed, the time for forming a channel in the channel region is shortened, so that the impurity concentration in the channel region can be set to be low. Therefore, when the impurity concentration of the channel region is set low, the capacitance of the depletion layer is reduced, and the slope of the subthreshold characteristic can be increased.
Since the threshold voltage can be reduced without increasing the off-leakage current, low-voltage driving can be realized without using an SOI substrate, and low power consumption can be achieved.

Hereinafter, a method for manufacturing the semiconductor device configured as described above will be described with reference to the drawings.

FIGS. 4, 5 and 6 are cross-sectional views in the order of steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS. FIGS. 5A to 5C show cross-sectional configurations in the order of steps of the manufacturing method along the line II.
FIG. 6D is a sectional view of the manufacturing method taken along the line II-II of FIG. 1 in the order of steps, and FIGS. 6A to 6D are sectional views of FIG.
3 shows a cross-sectional configuration in the order of steps of a manufacturing method for a line.

First, FIG. 4A, FIG. 5A and FIG.
As shown in FIG. 2A, a semiconductor substrate 11 having a plane orientation of (100) and made of P-type silicon has a thickness of, for example, 1 μm.
After forming the silicon oxide film 16 having a thickness of 00 nm, the silicon oxide film 16 is etched using photolithography to perform patterning to become the device active region mask pattern 50 shown in FIG. After that, using the patterned silicon oxide film 16 as a mask, wet etching is performed on the semiconductor substrate 11 using an aqueous solution of potassium hydroxide or ethylenediamine. Since the etching of the semiconductor substrate 11 made of silicon is performed selectively with respect to the crystal orientation plane (111), the cross-sectional shape of the channel forming region 13a in the gate width direction is changed as shown in FIG. Semiconductor substrate 11
Of the channel forming region 13a, which is narrowed in the gate width direction, and the etching surface from one side and the etching surface from the other side. And will intersect.
This wet etching is further continued, and the semiconductor substrate 11
The wet etching is performed until an opening 11a opening in the gate width direction is formed between the lower portion of the semiconductor substrate 11 and the channel forming region 13a, and the semiconductor substrate 11 and the channel forming region 13a are separated. Here, as shown in FIG. 5A, since the length of the source region 13b in the element active region 13 in the gate width direction is larger than the channel formation region 13a, the lower part of the source region 13b is connected to the lower part of the semiconductor substrate 11. It has been done. Although not shown, the lower part of the drain region 13c is similarly connected to the lower part of the semiconductor substrate 11. The etching of the semiconductor substrate 11 may be performed by using a dry etching method.

Next, FIG. 4B, FIG. 5B and FIG.
As shown in (b), after removing the silicon oxide film 16, an insulating oxide film is deposited on the entire surface of the semiconductor substrate 11, and the upper surface of the semiconductor substrate 11 is flattened by the CMP method or the etch back method. The opening 11a formed between the lower portion of the semiconductor substrate 11 and the channel forming region 13a of the element active region 13 and the periphery of the opening 11a are filled to form the insulating layer 12a under the channel. At the same time, the element isolation region 12 surrounding the periphery of the element active region 13 is formed. Note that thermal oxidation may be performed before depositing the insulating oxide film.

Next, FIG. 4 (c), FIG. 5 (c) and FIG.
As shown in (c), after boron ions for controlling the threshold voltage having an implantation energy of 10 keV and a dose of 1 × 10 ¹² cm ⁻² are implanted into the semiconductor substrate 11, An insulating oxide film having a thickness of 6 nm and a conductor film made of N-type polycrystalline silicon having a thickness of 200 nm are sequentially deposited over the entire surface. After that, the insulating oxide film and the conductor film are etched using the gate electrode mask pattern 51 shown in FIG. 2A to form the gate insulating oxide film 14 and the gate electrode 15.

Next, FIG. 4D, FIG. 5D and FIG.
As shown in (d), using the gate electrode 15 as a mask,
The implantation energy is 10 keV and the dose is 3 × 10 ¹⁵ c
After implanting arsenic ions of m ⁻² , the temperature was 850 ° C. and 30
The heat treatment is performed for a minute to form the source region 13b and the drain region 13c.

As shown in FIG. 4D, the semiconductor device manufactured as described above is formed below the channel formation region 13a of the element active region 13 in the semiconductor substrate 11.
Since a lower insulating layer 12a made of the same material as the element isolation region 12 is provided at intervals between the element isolation regions 12 on both sides in the gate length direction, the semiconductor substrate 11 has a lower portion below the channel formation region 13a. The SOI structure has a buried oxide film formed only in the region. Therefore, as described above, since the expansion of the depletion layer from the drain region 13c can be suppressed without using the SOI substrate, the impurity concentration of the channel formation region 13a can be reduced, and the gate depletion layer capacitance immediately below the gate electrode 15 can be reduced. Can be reduced. As a result, the slope of the sub-threshold characteristic increases, so that the threshold voltage can be reduced without increasing the off-leak current.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 7A is a perspective view of an N-channel MOS transistor of the semiconductor device according to the second embodiment of the present invention, and FIG. 7B is a sectional view taken along line IV-IV of FIG. Is shown. The semiconductor device according to the present embodiment is formed through the same steps as in the first embodiment, and FIG.
In FIG. 7A, the same members as those shown in FIG. As shown in FIG. 7A, the element active region 23 in the semiconductor substrate 11
Represents a channel forming region 23 which is narrowed in the gate width direction.
a and source regions 23 extending in the gate length direction, respectively.
b and the drain region 23c.
3 is formed using a device active region mask pattern 60 composed of a channel forming region 60a, a source region 60b, and a drain region 60c which is narrowed in the gate width direction shown in FIG. 2B.

As a feature of this embodiment, FIG.
As shown in (b), the device active region mask pattern 6
Since the source region 60b and the gate electrode mask pattern 61 overlap each other, a channel region is formed in a region where the element active region mask pattern 60 and the gate electrode mask pattern 61 overlap each other. The channel region is formed as the source region 60
The channel width increases at the end on the b side. Therefore, FIG.
As shown in (b), the end of the lower channel insulating layer 12a formed at the same time as the element isolation region 12 on the source region 23b side under the channel formation region 23a of the element active region 23 in the semiconductor substrate 11 is interrupted. Semiconductor substrate 1
1 and the region below the lower channel insulating layer 12a are the channel forming region connecting portions 11b.
Will be connected.

Generally, in a MOS transistor, a channel is formed at the interface between the gate electrode and the channel region, electrons flow from the source region to the drain region, and holes are injected below the gate electrode in the channel region. Further, the potential of the channel region rises due to the injected holes, and a potential breakdown occurs between the source region and the channel region. As a result, a kink phenomenon or the like occurs.

However, according to the present embodiment, the holes injected into the channel forming region 23a in the element active region 23 flow to the lower portion of the semiconductor substrate 11 through the channel forming region connecting portion 11b of the semiconductor substrate 11, Since the potential of the channel formation region 23a does not rise, potential breakdown does not easily occur at the interface between the source region 23b and the channel region. As a result, the same effects as those of the first embodiment can be obtained, and a MOS transistor with stable operation can be realized.

Hereinafter, a modified example of the second embodiment of the present invention will be described with reference to the drawings.

FIG. 8A is a perspective view of a MOS transistor of a semiconductor device according to a modification of the second embodiment, and FIG. 8B is a sectional view taken along line V-V of FIG. Is shown. The semiconductor device according to this modification is formed through the same steps as the manufacturing method described in the first embodiment. In FIG. 8A, the same members as those shown in FIG. The description is omitted by attaching the reference numerals. As shown in FIG. 8A, the element active region 33 in the semiconductor substrate 11 includes a channel forming region 33a narrowed in the gate width direction, and a source region 33b and a drain region 33c extending in the gate length direction, respectively. The active region 33 includes a channel forming region 70a and a source region 70 that are narrowed in the gate width direction shown in FIG.
It is formed by using a device active region mask pattern 70 composed of b and the drain region 70c.

As a feature of this modification, as shown in FIG. 2C, the source region 70b and the drain region 70c of the element active region mask pattern 70 and the gate electrode mask pattern 71 overlap each other. As a result, the channel region is formed in a region where the element active region mask pattern 70 and the gate electrode mask pattern 71 overlap with each other, so that the channel region is formed on the side of the source region 70b and the drain region. The channel width increases at both ends on the 70c side. Therefore, as shown in FIG. 8B, the element active region 33 in the semiconductor substrate 11 is formed.
The lower end of the channel lower insulating layer 12a formed at the same time as the element isolation region 12 below the channel forming region 33a is interrupted at both ends on the source region 33b side and the drain region 33c side.
3a and a region below the lower channel insulating layer 12a are connected at a first channel forming region connecting portion 11b and a second channel forming region connecting portion 11c.

As described above, also in the present modification, the holes injected into the channel formation region 33 a in the element active region 33 are connected to the first channel formation region connection portion 11 b of the semiconductor substrate 11 or the second channel formation region. Since the current flows to the lower portion of the semiconductor substrate 11 through the connection portion 11c, the potential of the channel formation region 33a does not increase, so that the potential breakdown does not occur between the source region and the channel region. Therefore, the same effect as that of the first embodiment can be obtained, and the MOS transistor with stable operation can be reliably realized.

The first channel forming region connecting portion 11
In the case where any one of b and the second channel formation region connection portion 11c is provided, in the case of an N-channel MOS transistor, holes are generated in the source region 3 by a drain bias.
Since the first channel formation region connecting portion 11b is provided to the side 3b, it is more effective to provide the first channel forming region connection portion 11b.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 9 shows a semiconductor integrated device according to a third embodiment of the present invention. FIG. 9A shows a mask pattern 80 for an element active region and a mask pattern 81 for a gate electrode.
(B) is a semiconductor integrated device formed using each of the mask patterns shown in (a), and shows a cross-sectional configuration taken along line VI-VI of (a). As shown in FIG. 9A, the element active region mask pattern 80 has an opening in the center and is narrowed in the gate width direction, and has a channel width of W1. And a second channel having a channel width W2 larger than the channel width W1.
And a common source region 80c and a common drain region 80d formed so as to sandwich the first channel formation region 80a and the second channel formation region 80b.

In the semiconductor integrated device shown in FIG. 9B, a semiconductor substrate 41 made of P-type silicon is surrounded by an isolation region 42 made of an insulating oxide film, and is narrowed in the gate width direction. And an element isolation region 42 at the center.
Are sandwiched, a first channel formation region 43a for the first semiconductor device, a second channel formation region 43b for the second semiconductor device, and a common source region (not shown) extending in the gate length direction. ) And a common drain region (not shown), an element active region (not shown) is formed. First channel formation region 4 of device isolation region and device active region on semiconductor substrate 41
A common gate electrode 45 is formed on 3a and the second channel formation region 43b via a gate insulating oxide film 44.

The semiconductor integrated device according to the present embodiment is manufactured by using the same manufacturing method as that of the above-described first embodiment, and therefore, as shown in FIG. Since the channel width W1 of the first channel formation region 43a is smaller than the channel width W2 of the second channel formation region 43b, the film thickness L1 in the direction perpendicular to the substrate surface of the first channel formation region 43a is smaller than the substrate surface of the second channel formation region 43b. Is smaller than the film thickness L2 in the vertical direction with respect to.

FIG. 10 shows the relationship between the thickness of the channel formation region and the gate voltage with respect to the drain current for each thickness in the MOS transistor, that is, M
10 illustrates a sub-threshold characteristic of an OS transistor. As shown in FIG. 10, since the drain current increases as the SOI film thickness decreases, it can be seen that the threshold voltage decreases. Accordingly, the threshold voltages of the first semiconductor device on the first channel formation region 43a side and the second semiconductor device on the second channel formation region 43b side according to the present embodiment are different from those of the channel formation region. Since the thicknesses are different from each other, they are set to different values.

As described above, according to this embodiment, the channel width W1 of the first channel formation region 80a and the channel width W2 of the second channel formation region 80b in the element active region mask pattern 80 are different from each other. , The film thickness L of each channel formation region
1 and L2 are formed differently. This allows
First channel formation region 80a and second channel formation region 80 in element active region mask pattern 80
If the channel widths of b are formed to be different from each other, transistors having different threshold voltages can be formed simultaneously.

As in the second embodiment, if the end of the source region or the drain region on the side of the gate electrode 45 overlaps with the gate electrode 45, the channel formation regions 43a and 43b in the semiconductor substrate 41 are formed. Is connected to the semiconductor substrate 41, the potential breakdown is less likely to occur in the channel region.

Hereinafter, a modified example of the third embodiment of the present invention will be described with reference to the drawings.

FIG. 11 shows a semiconductor integrated device according to a modification of the third embodiment of the present invention. ((A) shows an upper surface thereof, and (b) shows a cross section taken along line VII-VII of (a). 11C shows a sub-threshold characteristic, and as shown in FIGS. 11A and 11B, an element made of an insulating oxide film on a semiconductor substrate 41 made of P-type silicon. A conventional semiconductor device includes a first element active region 43A for a first semiconductor device having a first channel formation region 43a surrounded by an isolation region 42 and narrowed in a gate width direction, and a second channel formation region 43b. A second element active region 43B for the second semiconductor device is formed in the same rectangular shape as that of the first element active region 43A. The channel forming region 43a and the A gate insulating oxide film 44 is formed on the second channel formation region 43b of the second element active region 43B.
, A common gate electrode 45 as a first gate electrode and a second gate electrode is formed.

The semiconductor integrated device according to this modification is manufactured by using the same manufacturing method as that of the third embodiment. Further, as shown in FIG. 11B, the first element active region 4
The first channel formation region 43a in FIG.
Is an SOI transistor in which the channel width W1 is set so that the lower side of the channel formation region 43a is surrounded by the element isolation region 42. On the other hand, the second channel formation region 43b in the second element active region 43B is The bulk transistor has a channel width W2 set such that the lower side of the second channel formation region 43b is connected to the lower portion of the semiconductor substrate 41.

Therefore, as shown in the sub-threshold characteristic of FIG. 11C, the characteristic curve 1 of the SOI transistor having the first element active region 43A is the characteristic curve 1 of the bulk transistor having the second element active region 43B. Since the rising characteristic is improved as compared with the characteristic curve 2, the threshold voltage can be reduced without increasing the leakage current, and thus a lower voltage can be realized. On the other hand, SO
Since the channel width W1 of the I-type transistor is smaller than the channel width W2 of the bulk-type transistor, the driving current of the SOI-type transistor is smaller than that of the bulk-type transistor.

FIG. 12 shows a circuit configured using a semiconductor integrated device according to the present modification. The gate electrode is connected to the input terminal, and the drain electrode is connected to the power supply voltage Vdd.
A channel SOI transistor 3 and an N-channel bulk transistor 4 having a gate electrode connected to the input terminal, a drain electrode connected to the source electrode of the N-channel SOI transistor 3 and a source electrode connected to the output terminal
And a P-channel bulk transistor 5 whose gate electrode is connected to the input terminal, whose source electrode is connected to the output terminal, and whose drain electrode is grounded.

As described above, the SOI transistor 3 having a small off-leakage current and a low threshold voltage is used as a load transistor, and the bulk type transistors 4 and 5 having a high current driving capability are combined as a driving transistor. Thus, a circuit having only the advantages of the SOI transistor 3 and the bulk transistors 4 and 5 can be easily realized.

As in the second embodiment, the SO
In the I-type transistor 3, if the end of the source region or the drain region on the gate electrode 45 side is formed so as to overlap with the gate electrode 45, the region below the first channel formation region 43a in the first semiconductor device is formed. And the semiconductor substrate 41 are connected to each other, so that potential breakdown does not easily occur in the channel region.

[0062]

According to the semiconductor device of the present invention, the under-channel insulating layer formed below the channel region formed below the gate electrode is located between the element isolation regions located on both sides in the gate length direction. , The spread of the depletion layer generated in the channel region when a gate bias is applied is suppressed, and the time for forming a channel in the channel region is reduced. . Accordingly, the impurity concentration in the channel region can be reduced, the capacity of the depletion layer can be reduced, and the slope of the subthreshold characteristic can be increased. Therefore, the threshold voltage can be reduced without increasing off-leak current. As a result, low-voltage driving can be realized without using an SOI substrate, and low power consumption can be achieved.

In the semiconductor device according to the present invention, if the channel lower insulating layer is formed so as to connect the channel region to a region below the channel lower insulating layer in the semiconductor substrate, the semiconductor constituting the semiconductor substrate is formed. Even if an interface state is formed at the interface between the layer and the insulating layer below the channel, the source
No leak current flows between the drains. Further, since the injected holes can flow to the lower side of the semiconductor substrate, a potential breakdown is less likely to occur between the source or drain region and the channel region. As a result, a kink phenomenon or the like is less likely to occur, so that electrical characteristics can be improved.

According to the semiconductor integrated device of the present invention, the first semiconductor device has a space between the element isolation regions located on both sides in the gate length direction in a region below the first channel formation region. Since the channel lower insulating layer is formed as described above, the time for forming the channel in the channel region is reduced. Accordingly, the impurity concentration in the first channel formation region can be reduced, so that the capacitance of the depletion layer can be reduced and the slope of the subthreshold characteristic can be increased. Therefore, the threshold voltage can be reduced without increasing the off-leak current. be able to. Therefore, low-voltage driving can be realized without using an SOI substrate. On the other hand, the second semiconductor device formed on the same semiconductor substrate as the first semiconductor device and having the second element active region has a larger gate width than the first semiconductor device, and thus has a higher drive current.
Further, similarly to the first semiconductor device, when the second channel formation region is narrowed in the gate width direction, and a lower channel insulating layer is also formed in a region below the second channel formation region, Is that the second semiconductor device has a different gate width than the first semiconductor device, so that the thickness of each channel formation region is different. As a result, each threshold voltage of the first and second semiconductor devices is different. Will be different.

Therefore, the first and second semiconductor devices having different threshold voltages from each other can be combined on one semiconductor substrate, or the first and second semiconductor devices capable of low-voltage driving can be combined with the first and second semiconductor devices having large driving currents. By appropriately combining the two semiconductor devices, the advantages of the first and second semiconductor devices can be effectively obtained.

According to the method of manufacturing a semiconductor device according to the present invention, an insulating film is filled in an opening formed by etching in a region below a channel formation region below a gate electrode inside a semiconductor substrate to fill an insulating film under a channel. Since the layer is provided, when a gate bias is applied, the insulating layer below the channel suppresses the spread of a depletion layer generated in the channel region, so that the time for forming a channel in the channel region is reduced. As a result, the impurity concentration in the channel formation region can be reduced, so that the capacitance of the depletion layer can be reduced and the slope of the subthreshold characteristic can be increased.
The threshold voltage can be reduced without increasing the off-leak current. As a result, low-voltage driving can be realized without using an SOI substrate, and low power consumption can be realized.

In the method of manufacturing a semiconductor device according to the present invention,
When the plane orientation of the semiconductor substrate is (100) and the etching is wet etching, the opening that opens in the gate width direction is reliably formed only in the region below the channel formation region in the semiconductor substrate that is narrowed in the gate width direction. Therefore, the under-channel insulating layer can be reliably provided only in a region below the channel formation region.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2A is a plan view illustrating a mask pattern of the semiconductor device according to the first embodiment of the present invention. (B) is a plan view showing a mask pattern of the semiconductor device according to the second embodiment of the present invention. (C) is a plan view showing a mask pattern of a semiconductor device according to a modification of the second embodiment of the present invention.

3A and 3B show a cross-sectional configuration of the semiconductor device according to the first embodiment of the present invention, in which FIG. 3A is a cross-sectional configuration view taken along line II of FIG. 1, and FIG. FIG. 3 is a cross-sectional configuration diagram taken along a line, and FIG. 3C is a cross-sectional configuration diagram taken along a line III-III in FIG. 1.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention along the line II of FIG. 1 in the order of steps;

FIG. 5 is a sectional view taken along line II-II of FIG. 1 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention, taken along line III-III of FIG.

FIG. 7A is a perspective view showing a semiconductor device according to a second embodiment of the present invention. 4B is a cross-sectional configuration view taken along line IV-IV in FIG.

FIG. 8A is a perspective view showing a semiconductor device according to a modification of the second embodiment of the present invention. 5B is a cross-sectional configuration view taken along line VV in FIG.

9A and 9B show a semiconductor integrated device according to a third embodiment of the present invention, in which FIG. 9A shows a mask pattern for an active region and a mask pattern for a gate electrode, and FIG. FIG. 6 is a sectional view taken along line VI-VI of FIG.

FIG. 10 is a diagram showing a subthreshold characteristic of a MOS transistor for each SOI film thickness in a semiconductor integrated device according to a third embodiment of the present invention.

11A and 11B show a semiconductor integrated device according to a modified example of the third embodiment of the present invention, wherein FIG. 11A is a plan view, and FIG. 11B is a cross-sectional configuration view taken along line VII-VII of FIG. Yes,
(C) is a diagram showing a sub-threshold characteristic.

FIG. 12 is a circuit diagram configured using a semiconductor integrated device according to a modification of the third embodiment of the present invention.

FIG. 13 is a graph showing a relationship between a threshold voltage and an off-leak current in a MOS transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Characteristic curve of SOI type transistor 2 Characteristic curve of N channel bulk type transistor 3 SOI type transistor 4 N channel bulk type transistor 5 P channel bulk type transistor 11 Semiconductor substrate 11b Channel formation region connection part 11b First channel formation region connection part 11c Second channel formation region connection part 12 Element isolation region 12a Insulating layer under channel 13 Element active region 13a Channel formation region 13b Source region 13c Drain region 14 Gate insulating oxide film 15 Gate electrode 16 Silicon oxide film 23 Element active region 23a Channel Formation region 23b source region 23c drain region 33 device active region 33a channel formation region 33b source region 33c drain region 41 semiconductor substrate 42 device isolation region 43a first channel type Region 43b Second channel formation region 44 Gate insulating oxide film 45 Common gate electrode 50 Element active region mask pattern 50a Channel formation region 50b Source region 50c Drain region 51 Gate electrode mask pattern 60 Element active region mask pattern Reference Signs List 60a Channel formation region 60b Source region 60c Drain region 61 Gate electrode mask pattern 70 Element active region mask pattern 70a Channel formation region 70b Source region 70c Drain region 71 Gate electrode mask pattern 80 Element active region Mask pattern 80a First channel forming region 80b Second channel forming region 80c Common source region 80d Common drain region 81 Mask pattern for gate electrode

Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication H01L 29/78 626B

Claims (5)

[Claims] A semiconductor substrate having a source region and a drain region formed at intervals from each other; a gate electrode formed between the source region and the drain region on the semiconductor substrate; A lower channel insulating layer formed below a channel region formed below the electrode, wherein the lower channel insulating layer is between an element isolation region located on both sides in a gate length direction. A semiconductor device characterized by being formed so as to be spaced apart from each other. 2. The semiconductor device according to claim 1, wherein the lower channel insulating layer is formed such that the channel region is connected to a region of the semiconductor substrate below the lower channel insulating layer. 13. The semiconductor device according to claim 1. 3. A semiconductor integrated device comprising a first semiconductor device and a second semiconductor device formed on one semiconductor substrate, wherein the first semiconductor device is a semiconductor integrated device. A first gate electrode formed thereon, and a first channel formation surrounded by the element isolation region in the one semiconductor substrate, and formed under the first gate electrode and narrowed in a gate width direction. A first element active region consisting of a first source region and a first drain region extending in the region and the gate length direction, and a region below the first channel formation region, located on both sides in the gate length direction. A second gate electrode formed on the one semiconductor substrate, comprising: a channel lower insulating layer formed so as to be spaced from the element isolation region; The one semiconductor A second channel forming region formed under the second gate electrode and having a length in the gate width direction larger than the first channel forming region and a second channel extending in the gate length direction. A semiconductor integrated device having a second element active region including a source region and a second drain region. 4. A step of forming, on a semiconductor substrate, a mask pattern for masking a channel formation region constricted in a gate width direction and an element active region including a source region and a drain region extending in a gate length direction, respectively; The semiconductor substrate is etched using a pattern so that the semiconductor substrate is largely removed toward the lower part of the semiconductor substrate, so that an opening is formed in a region below the channel formation region in the semiconductor substrate in a gate width direction. Forming an opening to be formed, filling the opening in the semiconductor substrate with an insulating film to form an under-channel insulating layer, and forming an element isolation region made of an insulating film around the element active region. And forming a gate electrode in the channel formation region on the semiconductor substrate. A method of manufacturing a semiconductor device. 5. The method according to claim 4, wherein a plane orientation of the semiconductor substrate is (100), and the etching is wet etching.