JPH1065179A - Transistor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor device of SOI structure, in which an inter- source/drain withstand voltage can be enhanced and source/drain regions are restrained from increasing in sheet resistance. SOLUTION: A transistor device is equipped with a channel 45, sources and drains which are provided inside a semiconductor layer 30 formed on an insulating layer 21, wherein the sources are composed of a first source 46A and a second source 46B which is higher than the first source 46A in impurity concentration, and the drains are composed of a first drain 47A and a second drain 47B which is higher than the first drain 47A in impurity concentration. A first conductive region 51 and a second conductive region 52 are provided to the semiconductor layer 30 outside the source 46B and the drain region 47B respectively, and the insulating layer 21 is formed of material which do not react on metal elements which form the conductive regions 51 and 52.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a transistor element and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, the dimensional rules of semiconductor manufacturing processes are also becoming finer. For this reason, in the element isolation technology, the conventional LOCOS method cannot deal with miniaturization due to the influence of bird's peak. Therefore, SOI (Semiconductor O)
n Insulator) technology is attracting attention. A transistor element using this SOI technology has high resistance to α rays.
Further, since there is no generation of parasitic capacitance between the source / drain portion and the semiconductor substrate, which is a problem in a transistor element manufactured using a bulk semiconductor substrate, high-speed operation of the transistor element can be obtained. As described above, in the transistor element using the SOI technology, high reliability and high-speed operation can be obtained.

Hereinafter, a method of manufacturing a MOS transistor using a conventional SOI technique will be briefly described with reference to FIGS.

[Step-10] First, a groove 20 is formed on one surface 10A of a first semiconductor substrate 10 made of silicon (see FIG. 23A).

[Step-20] Next, the inside of the groove 20 and the first
After an insulating layer 121 made of silicon oxide is deposited on one surface 10A of the semiconductor substrate 10 and a polysilicon layer 23 is further deposited on the insulating layer 121, the surface of the polysilicon layer 23 is planarized. (See FIG. 23B).

[Step-30] Thereafter, the polysilicon layer 23 formed above one surface 10A of the first semiconductor substrate 10 is bonded to the second semiconductor substrate 11 made of silicon (FIG. 23). (C)).

[Step-40] Next, the back surface 10B of the first semiconductor substrate 10 is polished to remove the bottom surface 20A of the groove 20.
Is exposed (see FIG. 23D). by this,
Semiconductor layer 30 made of silicon between adjacent trenches 20
Is exposed. Each of the semiconductor layers 30 is electrically separated by the groove 20 and the insulating layer 121. Note that the semiconductor layer 30 is constituted by the first semiconductor substrate 10.

[Step-50] Thereafter, a gate electrode portion 41, a gate sidewall 44, a channel portion 45, a source portion 46 and a drain portion 4 are formed on the semiconductor layer 30 by a conventional method.
7 (see FIG. 24A). Thus, MO
An S-type transistor is manufactured.

[Step-60] Next, the interlayer insulating layer 6 is formed on the entire surface.
Then, an opening 61 is provided in the interlayer insulating layer 60 above the source part 46 and the drain part 47, and a metal wiring material layer 62 is formed on the interlayer insulating layer 60 including the inside of the opening 61.
Is formed (see FIG. 24B). As a result, a contact hole is formed. Then, the metal wiring material layer 6
2 is patterned to form a wiring.

[0010]

SUMMARY OF THE INVENTION M having an SOI structure
The OS transistor includes a source section 46, a channel section 4
5. The drain portion 47 is formed on the insulating layer 121. Therefore, when holes or electrons move in the semiconductor layer 30 in a state where the transistor element is turned on, silicon atoms in a region where the holes or electrons move are ionized, and the silicon atoms in the semiconductor layer 30 (particularly, in the channel portion 45). Deposited on For this reason, the breakdown voltage between the source part and the drain part is deteriorated, or a problem such as a short channel effect is generated. In a normal MOS transistor, the well is grounded via a semiconductor substrate.
Such a problem does not occur.

As one means for solving this problem, the surfaces of a source portion and a drain portion (hereinafter sometimes collectively referred to as a source / drain portion) have a salicide structure, and ions accumulated in a channel portion have a salicide structure. The technology of grounding via the
SOI MOSFETs BY SILICIDATION OF SOURCE ", LJMcDA
ID, et al., ELECTRONICS LETTERS, 23rd May 1991, vo
l. 27 No. 11, pp1003-1005. This salicide structure is formed by depositing a metal layer on the entire surface after forming the source part 46 and the drain part 47 in the above [Step-50]. Then, the heat treatment of the metal layer causes a reaction between an element forming the metal layer and Si forming the source / drain portion, thereby forming a silicide layer on the surface of the source / drain portion. However, even when such a salicide structure is formed, the ions accumulated in the channel portion are not completely grounded, and the improvement in the breakdown voltage between the source portion and the drain portion is insufficient.

When the dimensional rule is 0.5 μm, the required thickness of the semiconductor layer 30 is about 100 nm,
If the size rule is 0.35 μm, the required thickness of the semiconductor layer 30 is about 70 nm. As described above, as the thickness of the semiconductor layer 30 becomes thinner, there is also a problem that the sheet resistance of the source part 46 and the drain part 47 increases. For example, when the thickness of the semiconductor layer 30 is about 100 nm, the sheet resistance is about 70 Ω / □, but when the thickness of the semiconductor layer 30 is about 70 nm, the sheet resistance increases to 100 Ω / □ or more. In the future, as the thickness of the semiconductor layer 30 is further reduced, there is a problem that the sheet resistance of the source part 46 and the drain part 47 increases more and more. Due to such an increase in the sheet resistance, the parasitic resistance of the transistor element increases, and the element characteristics deteriorate.

By forming the silicide layer constituting the salicide structure in the source / drain portion, the resistance of the source / drain portion can be reduced. However, when titanium silicide is used, the size rule is 0.5 μm
In the following, there is a problem that aggregation tends to occur during the formation of titanium silicide, and the resistance value of the formed titanium silicide layer increases. If aggregation occurs during the formation of titanium silicide, for example, the bulk resistivity of titanium silicide rises to about 16 μΩ · cm. Such a phenomenon occurs even when the thickness of the silicide layer is reduced. That is,
As the thickness of the semiconductor layer 30 decreases, the thickness of the silicide layer to be formed also decreases. Accordingly, there is a problem that the sheet resistance of the silicide layer increases.

Further, when forming cobalt silicide,
In order to promote a stable reaction between Si and Co constituting the source / drain portion, Ti (titanium) and Co (cobalt) are sequentially deposited from below on the source / drain portion, and the Co / Ti layer is heat-treated. There is also known a technique in which Co and Si constituting a source / drain portion react with each other via a Ti layer as a reducing material to form a cobalt silicide layer on the surface of the source / drain portion.
However, for example, in an SOI structure, Si / Si
When the O ₂ layer structure is formed and the silicon semiconductor layer on the SiO ₂ layer and the Co / Ti are all reacted to form a silicide layer, the silicide layer also reacts with the underlying SiO ₂ layer, and as a result, a high-resistance silicide layer is formed. Is formed, or voids are partially generated.

The present applicant has disclosed in Japanese Patent Application No. 6-18991 (see Japanese Patent Application Laid-Open No. 7-2111916) a transistor in which a channel portion, a source portion and a drain portion are formed in a semiconductor layer formed on an insulating layer. Element (a)
A gate electrode portion, (b) a channel portion formed below the gate electrode portion, (c) a source portion formed in contact with one side of the channel portion, and (d) an outside of the source portion. A first conductive region formed of a metal or a metal compound, a drain portion formed in contact with the other side of the channel portion, and a semiconductor outside the drain portion. A transistor element formed in a layer and including a second conductive region made of a metal or a metal compound and a method for manufacturing the same are proposed.

In such a transistor element, since the first and second conductive regions are formed outside the source portion and the drain portion, it is possible to avoid the problem that the breakdown voltage between the source portion and the drain portion is deteriorated. it can. In addition, since the first and second conductive regions are formed, the sheet resistance of the source and drain portions is reduced by two to four digits as compared with a conventional transistor element even when the semiconductor layer is thinned. And the response speed of the transistor element can be improved.

However, when forming the first and second conductive regions, the elements forming the first and second conductive regions react with the elements forming the insulating layer, and as a result, the first conductive region is formed. Alternatively, it has been found that voids may occur in the second conductive region. When a void is generated in the first conductive region or the second conductive region in this manner, the resistance value varies, which causes a reduction in the reliability of the transistor element.

Further, the region corresponding to the source / drain region is only a so-called LDD (lightly doped drain) portion, and a PN junction is formed between the LDD portion and the channel portion. On the outside, a low-resistance metal silicide layer is formed. Therefore, there is a problem that the PN junction breakdown voltage at the time of reverse bias of the diode is deteriorated.

Accordingly, it is an object of the present invention to improve the breakdown voltage between the source and drain portions, and to reduce the size of the semiconductor layer on which the channel, source and drain portions are to be formed with the miniaturization of the dimensional rules. Even if the thickness is reduced, it is possible to suppress an increase in the sheet resistance of the source portion and the drain portion, furthermore, it is possible to suppress the occurrence of variation in the resistance value, and furthermore, it is possible to suppress the difference between the source / drain region and the channel portion. It is an object of the present invention to provide a transistor element having an SOI structure capable of improving a PN junction breakdown voltage between the transistors and a method for manufacturing the same.

[0020]

According to the present invention, there is provided a transistor device comprising a semiconductor layer formed on an insulating layer, wherein a channel portion, a source portion, and a drain portion are formed. (A) a gate electrode portion; (b) a channel portion formed below the gate electrode portion; (c) a source portion formed in contact with one side of the channel portion; A first conductive region formed in the semiconductor layer outside the source portion and made of a metal or a metal compound, (e) a drain portion formed in contact with the other side of the channel portion, and (f) the drain portion. A second conductive region formed of a metal or a metal compound and formed in the semiconductor layer outside the portion, the source portion being, from the channel portion side, a first source portion and a first source portion higher than the first source portion; The concentration of impurities Consists of a source portion, a drain portion, the channel portion side, the first drain portion, and the first
And the insulating layer is made of a material that does not react with the metal elements forming the first and second conductive regions.

In the transistor element of the present invention, the insulating layer is preferably made of, for example, silicon nitride (SiN) or silicon oxynitride (SiON). Further, the metal compound is preferably composed of cobalt silicide, titanium silicide, tungsten silicide, nickel silicide, platinum silicide, zirconium silicide, hafnium silicide, etc. Among them, the silicide is preferably composed mainly of cobalt silicide. Here, that the silicide is mainly composed of cobalt silicide may include another silicide (for example, titanium silicide) in cobalt silicide,
Alternatively, it means that other metal compounds may be included. Alternatively, tungsten can be cited as a metal constituting the first and second conductive regions.

The transistor element of the present invention has a so-called bond SOI structure (a substrate-bonded SOI structure) in which a first semiconductor substrate and a second semiconductor substrate are bonded, and the semiconductor layer is formed of the first semiconductor. The insulating layer may be provided on the first semiconductor substrate in the vicinity of a portion where the insulating layer is bonded to the second semiconductor substrate.

Alternatively, in the transistor element of the present invention, an insulating layer made of silicon nitride (SiN) or silicon oxynitride (SiON) is formed by ion-implanting impurities into a semiconductor substrate. A structure in which the portion of the semiconductor substrate above the layer corresponds to the semiconductor layer may be employed. In this case, a so-called SIMOX structure in which a second insulating layer made of, for example, SiO ₂ is formed below the insulating layer by an ion implantation method is preferable.

In the transistor element of the present invention, the first side made of an insulating material is on the side wall of the gate electrode part and above each of the first source part and the first drain part.
Is preferably formed, and a second gate sidewall made of an insulating material is formed above each of the second source portion and the second drain portion.

The first object of the present invention for achieving the above object is as follows.
The method for manufacturing a transistor element according to the above aspect is a method for manufacturing a transistor element in which a gate electrode portion, a channel portion, a source portion, and a drain portion are formed in a semiconductor layer formed over an insulating layer. Forming an insulating layer on one surface of the layer, (b) forming a gate electrode portion on the other surface of the semiconductor layer, and (c) forming a source portion and a drain portion on the semiconductor layer. Forming a channel portion in the semiconductor layer below the gate electrode portion, and (d) forming a first conductive region made of a metal or a metal compound in the semiconductor layer outside the source portion, Forming a second conductive region made of a metal or a metal compound in the semiconductor layer outside the drain portion;
(C-1) a step of forming a first source portion and a first drain portion containing impurities in the semiconductor layer by an ion implantation method, and (c-2) an insulating material on a side wall of the gate electrode portion. Forming a first gate sidewall comprising:
(C-3) forming a second source portion and a second drain portion containing impurities at a higher concentration than the first source portion and the first drain portion in the semiconductor layer by ion implantation; And (c-4) a step of forming a second gate sidewall on the side surface of the first gate sidewall. The material forming the insulating layer is used to form the first and second conductive regions. The material is selected from materials that do not react with the metal element.

In the method for manufacturing a transistor element according to the first aspect of the present invention, the insulating layer is formed of silicon nitride (S
iN) or silicon oxynitride (SiON).

In the step (d), a metal layer made of an element reacting with an element constituting the semiconductor layer is deposited on at least the other surface of the semiconductor layer outside the source portion and the semiconductor layer outside the drain portion. After that, subjected to a heat treatment, to react the element constituting the metal layer and the element constituting the semiconductor layer,
Thus, the method preferably includes a step of forming the first conductive region and the second conductive region made of a metal compound.

Alternatively, in the step (d), at least the semiconductor layer in the region outside the source portion and the semiconductor layer in the region outside the drain portion are replaced with a metal layer by a CVD method. The method may also include a step of forming a first conductive region and a second conductive region.

In the method for manufacturing a transistor element according to the first aspect of the present invention, the steps (c-2) and (c-2)
3) depositing a metal layer made of an element that reacts with an element constituting the semiconductor layer on at least the other surface of the semiconductor layer outside the source portion and the semiconductor layer outside the drain portion; To cause an element constituting the metal layer and an element constituting the semiconductor layer to react with each other, whereby the first conductive region and the second conductive region made of a metal compound are partially formed in the thickness direction of the semiconductor layer. (E).

The second object of the present invention for achieving the above object is as follows.
The method for manufacturing a transistor element according to the above aspect is a method for manufacturing a transistor element in which a gate electrode portion, a channel portion, a source portion, and a drain portion are formed in a semiconductor layer formed over an insulating layer. Forming a first conductive region made of a metal or a metal compound in a region outside the region of the semiconductor layer in which a drain portion is to be formed, and forming a metal or metal in a region outside the region of the semiconductor layer in which a drain portion is to be formed; Forming a second conductive region of a compound;
(B) forming an insulating layer on one surface of the semiconductor layer; (c) forming a gate electrode portion on the other surface of the semiconductor layer; and (iv) forming a source portion on the semiconductor layer. And forming a drain portion, and forming a channel portion in the semiconductor layer below the gate electrode portion.
(D-1) forming a first source portion and a first drain portion containing impurities in the semiconductor layer by ion implantation, and (d-2) forming a side wall of the gate electrode portion from an insulating material. A step of forming a first gate sidewall; and (d-3) a second step of containing a higher concentration of impurities than the first source section and the first drain section by ion implantation into the semiconductor layer. Forming a source portion and a second drain portion,
And the material constituting the insulating layer is a first material and a second material.
And a material that does not react with the metal element constituting the conductive region.

In the method for fabricating a transistor element according to the second aspect of the present invention, the insulating layer is made of silicon nitride (S
iN) or silicon oxynitride (SiON). Further, the step (a) includes forming a metal layer made of an element reacting with an element constituting the semiconductor layer on one surface of the semiconductor layer in a region outside a region of the semiconductor layer where a source portion and a drain portion are to be formed. After forming, heat treatment is applied,
It is preferable that the method comprises a step of reacting an element constituting the metal layer with an element constituting the semiconductor layer, thereby forming a first conductive region and a second conductive region made of a metal compound. Alternatively, in the step (a), the semiconductor layer in a region outside the region of the semiconductor layer in which the source and drain portions are to be formed is replaced with a metal layer by a CVD method, thereby forming the first metal layer. The method may also include a step of forming a conductive region and a second conductive region.

In the method for fabricating a transistor element according to the second aspect of the present invention, in the step (a), instead of forming the first and second conductive regions in the entire thickness direction of the semiconductor layer, Forming the first and second conductive regions in the semiconductor layer from one surface of the semiconductor layer to a certain depth, and further forming a source portion between steps (b) and (c). The remaining portion (in the thickness direction) of the first conductive region made of a metal compound is formed in a region outside the region of the semiconductor layer, and the region outside the region of the semiconductor layer where the drain portion is to be formed is formed. The remaining portion (in the thickness direction) of the second conductive region made of a metal compound may be formed. Also in this step, a heat treatment is performed after depositing a metal layer made of an element that reacts with an element constituting the semiconductor layer on at least the other surface of the semiconductor layer outside the source portion and the semiconductor layer outside the drain portion. It is preferable that the element forming the metal layer react with the element forming the semiconductor layer, thereby forming the remaining portions of the first conductive region and the second conductive region made of a metal compound. Alternatively, the first conductive region and the second conductive region made of a metal may be formed by replacing a semiconductor layer in a region outside the source and drain portions with a metal layer by a CVD method.

In the method for manufacturing a transistor element according to the second aspect of the present invention, after the step (d), a first conductive region made of a metal or a metal compound is formed in a semiconductor layer outside a source portion. In addition, a step (e) of forming a second conductive region made of a metal or a metal compound in the semiconductor layer outside the drain portion can be included. In this case, instead of forming the first and second conductive regions in the entire thickness direction of the semiconductor layer in the step (a), the semiconductor layer extends from one surface of the semiconductor layer to a certain depth. The first and second conductive regions are formed on the semiconductor substrate, and after the step (d), in the step (e), a semiconductor is formed on at least the other surface of the semiconductor layer outside the source portion and the semiconductor layer outside the drain portion. After depositing a metal layer made of an element that reacts with the element constituting the layer, heat treatment is performed, and the element constituting the metal layer reacts with the element constituting the semiconductor layer,
Thus, it is preferable to form the first conductive region and the second conductive region made of a metal compound. Alternatively, CVD
The first and second conductive regions made of metal may be formed by replacing the semiconductor layer in the region outside the source and drain portions with a metal layer by a method.

In the method for manufacturing a transistor element according to the first or second aspect of the present invention, the method has a structure in which a first semiconductor substrate and a second semiconductor substrate are bonded to each other,
The semiconductor layer is composed of a first semiconductor substrate, and the insulating layer is
A so-called bond SOI structure provided on the first semiconductor substrate in the vicinity of a portion to be bonded to the second semiconductor substrate can be formed.

The third object of the present invention for achieving the above object.
The method for manufacturing a transistor element according to the above aspect is a method for manufacturing a transistor element in which a gate electrode portion, a channel portion, a source portion, and a drain portion are formed in a semiconductor layer formed over an insulating layer. Forming an insulating layer by ion-implanting impurities into the inside of the substrate, thereby obtaining a semiconductor layer on a portion of the semiconductor substrate above the insulating layer; and (b) forming a gate electrode portion on the semiconductor layer. Forming a source part and a drain part in the semiconductor layer and forming a channel part in a semiconductor layer below the gate electrode part; and (d) forming a semiconductor part outside the source part. Forming a first conductive region made of a metal or a metal compound in the layer, and simultaneously forming a second conductive region made of a metal or a metal compound in the semiconductor layer outside the drain portion. (C): (C-1) a step of forming a first source portion and a first drain portion containing impurities in the semiconductor layer by an ion implantation method; and (C-2): sidewalls of a gate electrode portion Forming a first gate side wall made of an insulating material, and (c-3) ion-implanting an impurity having a higher concentration than the first source portion and the first drain portion into the semiconductor layer. Forming a second source portion and a second drain portion, and (c-4) forming a second gate side wall on the side surface of the first gate side wall, by ion implantation. The formed insulating layer is made of a material that does not react with a metal element forming the first and second conductive regions.

In the method for manufacturing a transistor element according to the third aspect of the present invention, the insulating layer is made of silicon nitride (Si).
N) or silicon oxynitride (SiON). Further, prior to the step (a), a second insulating layer made of, for example, SiO ₂ is formed inside the semiconductor substrate by an ion implantation method. Is preferably formed.

In the method for fabricating a transistor element according to the third aspect of the present invention, the step (d) includes forming a semiconductor layer on at least a semiconductor layer outside a source portion and a semiconductor layer outside a drain portion. After depositing a metal layer made of an element that reacts with the element to be formed, a heat treatment is performed to cause the element that forms the metal layer to react with the element that forms the semiconductor layer. Area and second
It is preferable that the method comprises a step of forming the conductive region.

Alternatively, in the step (d), at least the semiconductor layer in the region outside the source portion and the semiconductor layer in the region outside the drain portion are replaced with a metal layer by a CVD method. The method may also include a step of forming a first conductive region and a second conductive region.

In the method for fabricating a transistor element according to the third aspect of the present invention, the steps (c-2) and (c-2)
3) depositing a metal layer made of an element that reacts with an element constituting the semiconductor layer on at least the other surface of the semiconductor layer outside the source portion and the semiconductor layer outside the drain portion; To cause an element constituting the metal layer and an element constituting the semiconductor layer to react with each other, whereby the first conductive region and the second conductive region made of a metal compound are partially formed in the thickness direction of the semiconductor layer. A step of forming the same.

In the method of manufacturing a transistor element according to the first to third aspects of the present invention, all of the semiconductor layers outside the source and drain portions are made of the first and second semiconductor layers made of metal or metal compound. Is preferably replaced by the conductive region. In the present invention, the first
The conductive region and the second conductive region may have not only a single-layer structure but also a two-layer structure. In this case, the metal or metal compound in each layer constituting each conductive region may be the same or different.

In the method for manufacturing a transistor element according to the first to third aspects of the present invention, the metal layer is made of a transition metal or a noble metal, and the method for manufacturing a transistor element according to the first or third aspect of the present invention is provided. The step of (d),
Step (a) of the method for manufacturing a transistor element according to the second aspect of the present invention, or step (e) of the method for manufacturing a transistor element according to the first aspect of the present invention, as the case may be; The step (e) or the step between steps (b) and (c) of the method for manufacturing a transistor element according to the second aspect of the present invention comprises the steps of (A) forming a metal layer with an element constituting a semiconductor layer. Reacts with the transition metal or precious metal
And a first heat treatment for reacting the element forming the metal layer with the element forming the semiconductor layer at a temperature at which the oxide formed of the element forming the semiconductor layer does not react with the transition metal or the noble metal forming the metal layer. (B) removing the unreacted metal layer, and (C) performing a second heat treatment in order to further react the element constituting the metal layer with the element constituting the semiconductor layer. It can be. Also,
The metal compound is preferably composed of cobalt silicide, titanium silicide, tungsten silicide, nickel silicide, platinum silicide, zirconium silicide, hafnium silicide, etc. It is preferable to be composed of silicide. here,
When the metal layer is mainly composed of cobalt or the silicide is mainly composed of cobalt silicide, another metal or a metal compound may be contained in the metal layer, or another silicide may be contained in the cobalt silicide. (E.g., titanium silicide) and other metal compounds may be included.

In the present invention, since the insulating layer made of a material that does not react with the metal elements forming the first and second conductive regions is formed, the element forming the metal layer and the element forming the semiconductor layer are separated from each other. To effectively suppress generation of voids in the formed first and second conductive regions when the first and second conductive regions made of a metal or a metal compound are formed. Can be. In addition, the source portion and the drain portion are, from the channel portion side, a first source portion, a first drain portion, and a second source containing impurities at a higher concentration than the second source portion and the drain portion. Since it is constituted by the portion and the second drain portion, the PN junction breakdown voltage between the source portion or the drain portion and the channel portion can be improved.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on embodiments with reference to the drawings. In each embodiment, a MOS transistor will be described as an example of a transistor element. still,
Examples 1 to 3 relate to a method for manufacturing a transistor element according to the first embodiment of the present invention. That is, the first and second conductive regions are formed from the surface of the semiconductor layer on the side where the gate electrode portion is formed. Example 4 relates to a method for manufacturing a transistor element according to the second embodiment of the present invention. That is, the first and second conductive regions are formed from the surface of the semiconductor layer opposite to the side on which the gate electrode portion is formed. Example 5 and Example 6
Relates to a modification of the method for manufacturing a transistor element according to the second embodiment of the present invention. Further, Example 7 and Example 8
The present invention relates to a method for manufacturing a transistor element according to a third aspect. Example 9 Example 9 relates to a method for manufacturing a transistor element according to the first embodiment of the present invention.

Example 1 The transistor element of Example 1 has an insulating layer 2 as shown in FIG.
The channel portion 45 and the first
Is a MOS transistor having an SOI structure in which the source part 46A, the second source part 46B, the first drain part 47A, and the second drain part 47B are formed.
The gate electrode portion 41 is formed on the semiconductor layer 30.
That is, it has a so-called bond SOI structure in which the first semiconductor substrate 10 and the second semiconductor substrate 11 are bonded to each other, the semiconductor layer 30 is composed of the first semiconductor substrate 10, and the insulating layer 21 Is provided on the first semiconductor substrate 10 in the vicinity of the portion to be bonded to the semiconductor substrate 11. The channel part 45 is formed below the gate electrode part 41. The first source part 46A is formed in contact with one side of the channel part 45, and the first drain part 47A is formed in contact with the other side of the channel part 45.

Elements that characterize the transistor element of the present invention include a first conductive region 51 made of a metal compound and formed in the semiconductor layer 30 outside the second source portion 46B.
The second conductive region 52 made of a metal compound is formed in the semiconductor layer 30 outside the second drain portion 47B.
These first and second conductive regions 5 in the first embodiment
Reference numerals 1 and 52 are metal compounds made of silicide, more specifically, cobalt silicide (CoSi ₂ ). Further, the insulating layer 21 is made of a material that does not react with the metal element (Co) forming the first and second conductive regions, specifically, silicon nitride (SiN). First conductive region 51
Is surrounded by the insulating layer 21 and the second source portion 46B. On the other hand, the second conductive region 52 is surrounded by the insulating layer 21 and the second drain portion 47B.

In the first embodiment, the source section further includes:
The channel portion 45 includes a first source portion 46A and a second source portion 46B containing a higher concentration of impurities than the first source portion 46A, and the drain portion includes a first source portion 46A from the channel portion 45 side. And a second drain portion 47B containing a higher concentration of impurities than the first drain portion 47A.

In the first embodiment, furthermore, on the side wall of the gate electrode portion 41 and above each of the first source portion 46A and the first drain portion 47A, a _second insulating material (for example, SiO ₂ ) is formed. 1 gate side wall 44
A is formed. A second gate sidewall 44B made of an insulating material (for example, SiO ₂ ) is formed above each of the second source portion 46B and the second drain portion 47B.

The first conductive region 51 and the second conductive region 51 made of a metal compound (specifically, cobalt silicide, CoSi ₂ )
Is formed on the other surface 30B of the semiconductor layer 30 on which the first and second conductive regions are to be formed, by an element (specifically, Si) that reacts with the element (specifically, Si) constituting the semiconductor layer 30. After depositing a metal layer 50 made of Co), heat treatment is performed to cause an element forming the metal layer (specifically, Co) and an element forming the semiconductor layer (specifically, Si) to react. Formed by

Hereinafter, a method for manufacturing the transistor element of Example 1 will be described with reference to FIGS.

[Step-100] The insulating layer 21 is formed on one surface of the semiconductor layer 30. Specifically, first, Si
A first semiconductor substrate 10 made of (100) is prepared.
Then, one surface 10A of the first semiconductor substrate 10
After applying and drying a resist, the resist is patterned using a photolithography technique. Next, the first semiconductor substrate 10 is dry-etched using the patterned resist as a mask to form a first semiconductor substrate 1.
After the grooves 20 are formed on the one surface 10A of the “0”, the resist is removed. The etching conditions of the first semiconductor substrate 10 are exemplified below. Working gas: SiCl ₄ / N ₂ = 10/10 sccm Pressure: 1.3 Pa Microwave power: 850 W RF power: 200 W

Thereafter, an insulating layer 21 made of silicon nitride (SiN) is deposited by LP-CVD on one surface 10A of the first semiconductor substrate 10 including the inside of the groove 20. Thus, the structure shown in FIG. 2A can be obtained. The deposition conditions of the insulating layer 21 are exemplified below. This insulating layer 21
Means that the first and second conductive regions 51 and 5 are used in the first and second heat treatments in [Step-160] described later.
2 is made of a material (specifically, SiN) that does not react with a metal element (specifically, Co). Therefore, generation of voids in the first conductive region 51 and the second conductive region 52 can be reliably prevented. Working gas: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 90/600 /
1000 sccm Pressure: 53 Pa Temperature: 700 ° C. Film thickness: 50 nm

[Step-110] Then, a second insulating layer 22 made of silicon oxide (SiO ₂ ) is formed on the insulating layer 21 by CV.
Deposit by method D. The CVD conditions for the second insulating layer 22 are exemplified below. The second insulating layer 22 embedded in the groove 20 functions as an element isolation region.

Alternatively, the bias ECR under the following conditions
Silicon oxide (SiO ₂ ) is formed on the insulating layer 21 by CVD.
May be deposited. Working gas: SiH ₄ / N ₂ O / Ar = 14/35/72 sc
cm Pressure: 0.093 Pa Temperature: 400 ° C Microwave: 1000 W Film thickness: 0.4 μm

[Step-120] Next, the second insulating layer 2
2 on the polysilicon layer 23, for example, under the following conditions:
It is deposited by a P-CVD method. This polysilicon layer 23
Is an interface when the second semiconductor substrate 11 is bonded to the first semiconductor substrate 10 in a later step, and serves as an adhesive layer for bonding the first semiconductor substrate 10 and the second semiconductor substrate 11. Has functions. Gas used: SiH ₄ / H ₂ / N ₂ = 100/400/2
00 sccm Temperature: 610 ° C. Pressure: 70 Pa Film thickness: 0.2 μm

Thereafter, a resist is applied to the surface of the polysilicon layer 23 and the entire surface is etched back,
The polysilicon layer 23 is flattened. This state is shown in a schematic partial cross-sectional view in FIG. The conditions of the etch back are exemplified below. Working gas: C ₂ Cl ₃ F ₃ / SF ₆ = 60/10 sccm Pressure: 1.3 Pa Microwave power: 850 W RF power: 150 W

Next, the surface of the polysilicon layer 23 is polished, and the surface of the polysilicon layer 23 is bonded to the second semiconductor substrate 11 made of silicon (see FIG. 2C). The bonding can be performed by performing a heat treatment at, for example, 1100 ° C. × 30 minutes while the first and second semiconductor substrates 10 and 11 are overlapped.

[Step-130] Thereafter, the first semiconductor substrate 10 is polished from the back side 10B of the first semiconductor substrate 10, and silicon (more specifically, the first semiconductor substrate 10) is interposed between adjacent grooves 20. The semiconductor layer 30 made of silicon constituting the semiconductor layer 10 is exposed (see FIG. 3A). When the polishing proceeds to the bottom surface 20A of the groove 20, the insulating layer 21 made of SiN formed in the groove 20 is exposed. SiN
Is harder than Si, so SiN becomes a polishing stopper,
The semiconductor layer 30 can be prevented from being polished too much. Thus, a substrate having an SOI structure in which the insulating layer 21 is formed on one surface 30A of the semiconductor layer 30 is manufactured.

[Step-140] Next, a gate electrode portion 41 having a polycide structure is formed on the other surface 30B of the semiconductor layer 30. For this purpose, a gate oxide film 40 made of SiO ₂ is first formed on the other surface 30B of the semiconductor layer 30 by using a conventional method. Thereafter, an impurity-doped polysilicon film (DOPO) is formed on the gate oxide film 40.
S) 42 is deposited by a CVD method. Polysilicon film 4
2 can be formed, for example, under the following conditions. Gas used: SiH ₄ / PH ₃ /He=500/0.35
/ 50 sccm Temperature: 580 ° C Pressure: 80 Pa Film thickness: 0.15 μm

Next, WSi _{2 is} deposited on the polysilicon film 42.
The layer 43 is formed by a CVD method. The WSi ₂ layer 43 can be formed, for example, under the following conditions. Gas used: WF ₆ / SiH ₄ / He = 10/1000 /
360 sccm Temperature: 360 ° C Pressure: 27 Pa Film thickness: 0.15 μm

Thereafter, a resist is applied on the WSi ₂ layer 43, the resist is patterned, and the WSi ₂ layer 43 and the polysilicon film 42 are etched by dry etching under, for example, the following conditions to remove the resist. Thus, a gate electrode portion 41 composed of the gate oxide film 40, the polysilicon film 42, and the WSi ₂ layer 43 is formed (see FIG. 3B). Working gas: C ₂ Cl ₃ F ₃ / SF ₆ = 65/5 sccm Pressure: 1.3 Pa Microwave power: 700 W RF power: 100 W

[Step-150] Thereafter, a source portion and a drain portion are formed in the semiconductor layer 30, and a channel portion 45 is formed in the semiconductor layer 30 below the gate electrode portion 41.

[Step-150A] Specifically, a resist mask is formed on the semiconductor layer 30, and the first source portion 46A and the first source portion 46A containing impurities are formed by ion implantation under the following conditions. Is formed. n-type first source part 46A and first drain part 47A
Ion: As Dose: 5 × 10 ¹³ / cm ² Acceleration voltage: 30 keV P-type first source part 46A and first drain part 47A
Formation of ions: BF ₂ dose amount: 1 × 10 ¹³ / cm ² acceleration voltage: 30 keV

[Step-150B] Next, the gate electrode part 4
A first gate sidewall 44A made of SiO _{2 as an} insulating material is formed on one side wall. Specifically, a SiO ₂ layer is formed on the entire surface by the CVD method exemplified below, and thereafter, the first gate sidewall 44A is formed by performing anisotropic dry etching exemplified below (FIG. 4). (A)). CVD conditions Gas used: SiH ₄ / O ₂ / N ₂ = 250/250/1
00 sccm Temperature: 420 ° C. Film thickness: 0.35 μm Conditions for anisotropic dry etching Gas used: C ₄ F ₈ = 50 sccm Pressure: 2 Pa RF power: 1200 W

[Step-150C] Thereafter, a resist mask is formed, and the first source portion 46A and the first source portion 46A are formed in the semiconductor layer 30 by an ion implantation method under the following conditions.
After forming the second source part 46B and the second drain part 47B containing impurities at a higher concentration than the drain part 47A, RTA (Rapid Ther
(Mal Annealing) treatment to activate the ion-implanted impurities. The region to be ion-implanted may extend outside the region of the semiconductor layer 30 where the second source portion 46B and the second drain portion 47B are to be formed. n-type second source part 46B and second drain part 47B
Ion: As Dose: 3 × 10 ¹⁵ / cm ² Accelerating voltage: 50 keV P-type second source part 46B and second drain part 47B
Formation of ions: BF ₂ dose: 3 × 10 ¹⁵ / cm ² Accelerating voltage: 30 keV

[Step-150D] Next, a second gate sidewall 44B is formed on the side surface of the first gate sidewall 44A (see FIG. 4B). The method for forming the second gate sidewall 44B is described in [Step-15].
0B].

As described above, in the first embodiment, the first source section 46A and the second source section 46B containing a higher concentration of impurities than the first source section 46A are formed from the channel section 45 side. A source part is formed. On the other hand, from the channel portion 45 side, a source portion including a first drain portion 47A and a second drain portion 47B containing an impurity at a higher concentration than the first drain portion 47A is formed. A first gate sidewall 44A made of an insulating material (SiO ₂ ) is formed on the side wall of the gate electrode portion and above each of the first source portion 46A and the first drain portion 47A. A second gate sidewall 44B made of an insulating material (SiO ₂ ) is formed above each of the second source portion 46B and the second drain portion 47B. In this state, the exposed region of the semiconductor layer 30 is a region sandwiched between the second gate sidewall 44B and the groove 20. The first and second conductive regions are formed in this region in the next step.

[Step-160] That is, the first conductive region 51 made of a metal compound is formed in the semiconductor layer 30 outside the source portion (specifically, the second source portion 46B), and at the same time, the drain Section (specifically, the second drain section 47
A second conductive region 52 made of a metal compound is formed in the semiconductor layer 30 outside B). In the first embodiment, for this purpose, the semiconductor layer 3 on which the first and second conductive regions are to be formed is formed.
After the metal layer 50 is formed on the other surface 30B of 0, cobalt (Co), which is an element forming the metal layer 50, and Si, which is an element forming the semiconductor layer 30, are reacted. That is, the metal layer 50 is made of cobalt (Co), and the first and second conductive regions 51 and 52 are made of cobalt silicide (Co).
Si ₂ ).

Specifically, first, a metal layer 50 made of cobalt is deposited on the entire surface by sputtering (see FIG. 5A). The thickness of the metal layer 50 is set to a thickness equal to or greater than a thickness necessary for reacting all of Si corresponding to the thickness of the semiconductor layer 30 made of Si. For example, conditions for forming the metal layer 50 made of Co having a thickness of 0.1 μm are described below. Gas used: Ar = 100 sccm Pressure: 0.47 Pa DC power: 8 kW Film thickness: 0.1 μm

Next, C, which is an element constituting the metal layer 50, is used.
o and Si, which is an element constituting the semiconductor layer 30, are reacted to form a metal compound (specifically, cobalt silicide, C
oSi ₂ ). The region of the semiconductor layer 30 that reacts with the metal layer 50 is a region sandwiched between the second gate sidewall 44B and the groove 20, and the first and second conductive regions are formed in this region. The reaction between the element forming the metal layer 50 and the element forming the semiconductor layer 30 is preferably performed in the following process, but the conditions are not limited to the following examples.

First, the element (specifically, Si) forming the semiconductor layer 30 reacts with the transition metal (specifically, Co) forming the metal layer 50, and the element (specifically, Co) forming the semiconductor layer 30 is reacted. Specifically, an oxide composed of Si) (specifically, S
It is desirable that the element forming the metal layer 50 and the element forming the semiconductor layer 30 react at a temperature at which the iO ₂ ) does not react with the transition metal (specifically, Co) forming the metal layer 50. This process is called a first heat treatment. Specifically, a heat treatment is performed in nitrogen gas (flow rate: 5 liters / minute) at, for example, 500 ° C. for 30 seconds. This gives C
oSi _X is generated.

Next, the unreacted metal layer is removed by immersing it in, for example, ammonia peroxide (a mixed aqueous solution of NH ₄ OH and H ₂ O ₂ ) for about 10 minutes. The unreacted metal layer is formed on the groove 20 and the gate sidewalls 44A, 44B.
It is a metal layer deposited on the top and the gate electrode portion 41. Thus, the first conductive region 51 made of the metal compound is formed in the semiconductor layer 30 outside the second source portion 46B, and the first conductive region 51 made of the metal compound is formed in the semiconductor layer 30 outside the second drain portion 47B. Two conductive regions 52 are formed.

After that, a second heat treatment, for example, at 750 ° C. × 30 seconds is performed in an argon gas atmosphere to obtain CoSi _x
Is CoSi ₂ . In the first and second heat treatments, the first and second conductive regions 51 and 52 are made of a material (specifically, SiN) that does not react with a metal element (specifically, Co). Since the insulating layer 21 is formed, generation of voids in the first conductive region 51 and the second conductive region 52 can be reliably prevented. As a result, the resistance values of the first and second conductive regions 51 and 52 do not vary, and a highly reliable transistor element can be manufactured. Thus, the transistor element shown in FIG. 1 is manufactured.

[Step-170] Next, an interlayer insulating layer 60 made of SiO ₂ is deposited on the entire surface by, eg, CVD under the following conditions. Gas used: TEOS = 50 sccm Temperature: 720 ° C. Pressure: 40 Pa Film thickness: 0.6 μm

Thereafter, if necessary, an opening 61 is formed in the interlayer insulating layer 60 above the first and second conductive regions 51 and 52.
To form The conditions for anisotropic etching of the interlayer insulating layer 60 are exemplified below. Working gas: C ₄ F ₈ = 50 sccm Pressure: 2 Pa RF power: 1200 W

[Step-180] Next, a metal wiring material layer 62 is deposited on the interlayer insulating layer 60 including the opening 61. (See FIG. 5B). In the first embodiment,
In the opening 61, a so-called blanket tungsten CVD is used.
Embedding tungsten by the method. Further, a metal wiring material made of an aluminum-based alloy is deposited on the interlayer insulating layer 60. In FIG. 5B, illustration of various layers constituting the wiring layer is omitted.

Specifically, prior to embedding tungsten in the opening 61, first, a contact layer made of Ti and a TiN
Is formed by, for example, a sputtering method. The contact layer is formed for the purpose of reducing the contact resistance between the tungsten buried in the opening 61 and the first and second conductive regions 51 and 52. Also,
The barrier metal layer is formed for the purpose of preventing the tungsten embedded in the opening 61 from reacting with the first and second conductive regions 51 and 52. Thereafter, tungsten is deposited on the entire surface by blanket tungsten CVD, and then the tungsten deposited on the interlayer insulating layer 60 is removed by etching back. Conditions for forming contact layer Gas used: Ar = 100 sccm Temperature: 150 ° C. Film thickness: 30 nm Pressure: 0.47 Pa Power: 4 kW Conditions for forming barrier metal layer Gas used: N ₂ / Ar = 70/40 sccm Temperature: 150 ° C. Film thickness: 70 nm Pressure: 0.47 Pa Power: 5 kW Conditions of blanket tungsten CVD method Gas used: WF ₆ / H ₂ / N ₂ / Ar = 75/500 /
300/2200 sccm Temperature: 450 ° C. Pressure: 1.1 × 10 ⁴ Pa Film thickness: 0.4 μm Tungsten etch-back condition Gas used: SF ₆ = 50 sccm Pressure: 1.3 Pa RF power: 150 W

Next, a Ti layer is formed on the entire surface by sputtering, and a metal wiring material made of, for example, Al—Si (1%) is deposited thereon by sputtering. The Ti layer is
It is formed for the purpose of improving the adhesion and wettability between the metal wiring material and the interlayer insulating layer 60. After that, the metal wiring material and the Ti layer are etched. Thus, a wiring having a desired pattern is formed on the interlayer insulating layer 60. The wiring made of the metal wiring material and the Ti layer, the source portion and the drain portion are connected to the opening 61 (that is, the contact hole) in which tungsten is buried and the first and second openings.
Are electrically connected via the conductive regions 51 and 52. Conditions for forming Ti layer Gas used: Ar = 100 sccm Temperature: 150 ° C. Film thickness: 30 nm Pressure: 0.47 Pa Power: 4 kW Film forming conditions for Al—Si metal wiring material Gas used: Ar = 40 sccm Temperature: 300 ° C. film Thickness: 0.5 μm Pressure: 0.47 Pa Power: 22.5 kW Al-Si / Ti layer etching conditions Gas used: BCl ₃ / Cl ₂ = 60/90 sccm Pressure: 0.016 Pa Microwave power: 1000 W RF power: 50 W

The following is a summary of the method for manufacturing the transistor element of Example 1 described above. A groove 20 is formed in the first semiconductor substrate 10 and a groove 2 is formed.
The insulating layer 21 is formed on the surface of the first semiconductor substrate 10 including zero. This step corresponds to a step of forming an insulating layer on one surface 30A of the semiconductor layer 30. The insulating layer 21 has a first
And a material that does not react with the metal element forming the second conductive region, and is made of silicon nitride (SiN) or silicon oxynitride (S
iON). After the second insulating layer 22 and the polysilicon layer 23 are formed on the insulating layer 21 and the polysilicon layer 23 is planarized, the first semiconductor substrate 1 is interposed via the polysilicon layer 23.
0 and the second semiconductor substrate 11 are bonded together. afterwards,
Polishing is performed from the back surface of the first semiconductor substrate 10 to expose the bottom of the groove 20 formed in the first semiconductor substrate 10. Thus, a substrate having a so-called SOI structure is manufactured. A gate electrode portion 41 is formed on the exposed region of the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30). In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), a first source portion 46A and a first drain portion 47A containing impurities are formed by an ion implantation method. A first gate sidewall 44A made of an insulating material is formed on the side wall of the gate electrode portion 41. In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), the second region containing a higher concentration of impurities than the first source portion 46A and the first drain portion 47A by an ion implantation method. The source part 46B and the second drain part 47B are formed. A second gate sidewall 44B is formed on a side surface of the first gate sidewall 44A. After forming the metal layer 50 on the entire surface, the elements constituting the metal layer 50 and the elements constituting the semiconductor layer 30 are reacted by performing a heat treatment, and then the unreacted metal layer is removed.
Further, heat treatment is performed to cause an element constituting the metal layer 50 to react with an element constituting the semiconductor layer 30. Thereby, the source section (more specifically, the second source section 46)
A first conductive region 51 made of a metal compound is formed in the semiconductor layer 30 outside the semiconductor layer 3B, and the semiconductor layer 3 outside the drain portion (more specifically, the second drain portion 47B) is formed.
At 0, a second conductive region 52 made of a metal compound is formed.

Example 2 In Example 1, the first conductive region 51 and the second conductive region 52 were made of cobalt silicide. On the other hand, in the second embodiment, the first conductive region 51 and the second conductive region 52 are mainly made of cobalt silicide and include titanium silicide and TiO _X. In addition, the metal layer is made of cobalt (C
o) and a titanium (Ti) layer. Specifically, Example 2 differs from Example 1 in [Step-160]. Hereinafter, only such differences will be described.

Instead of [Step-160] in Example 1,
In the second embodiment, the first conductive region 51 made of a metal compound is formed in the semiconductor layer 30 outside the source portion (specifically, the second source portion 46B), and the drain portion (specifically, the second conductive portion 46B) is formed. In order to form the second conductive region 52 made of a metal compound in the semiconductor layer 30 outside the second drain portion 47B), the other of the semiconductor layer 30 where the first and second conductive regions are to be formed Ti and Co on the surface 30B of
After the formation of the metal layer 50 made of, the elements constituting the metal layer 50 and the elements constituting the semiconductor layer 30 are reacted.
The first and second conductive regions 51 and 52 are mainly made of cobalt silicide (CoSi ₂ ), and include titanium silicide (TiSi ₂ ) and TiO _X. Note that titanium is a natural oxide film SiO ₂ existing on the surface of the semiconductor layer 30.
Reacts with oxygen atoms in the first and second conductive regions 51,
TiO _x is formed on the surface (top surface) of the substrate 52.

Specifically, first, a Ti layer is deposited on the entire surface by a sputtering method under the conditions exemplified below.
A cobalt layer is deposited thereon. The thickness of the cobalt layer is equal to or greater than the thickness required to react all of the Si for the thickness of the semiconductor layer 30 made of Si. (Film formation of Ti layer) Gas used: Ar = 100 sccm Pressure: 0.47 Pa Temperature: 150 ° C. DC power: 4 kW Film thickness: 10 μm (Co layer film formation conditions) Gas used: Ar = 100 sccm Pressure: 0.47 Pa Temperature: 150 ° C DC power: 8 kW Film thickness: 0.1 μm

Next, Co / Ti forming the metal layer 50 and Si forming the semiconductor layer 30 are reacted to form a metal compound (specifically, mainly cobalt silicide, CoS
i ₂ , other, titanium silicide, TiSi ₂ and TiO
_X ). This step is specifically described in Example 1.
Since the step can be the same as the first heat treatment step, the unreacted metal layer removing step, and the second heat treatment step in [Step-160], detailed description thereof will be omitted.

(Embodiment 3) Embodiment 3 is a modification of Embodiment 1. Hereinafter, a method for manufacturing a transistor element in Example 3 will be described with reference to FIGS.

[Step-300] First, the insulating layer 21 is formed on one surface of the semiconductor layer 30 in the same manner as in [Step-100] of the first embodiment. Thereafter, a second insulating layer 22 made of silicon oxide (SiO ₂ ) is deposited on the insulating layer 21 by the CVD method in the same manner as in [Step-110], and further by the method of [Step-120]. The polysilicon layer 23 is formed on the second insulating layer 22 by, for example, LP-C under the following conditions.
It is deposited by the VD method. Thereafter, the polysilicon layer 23 is flattened, and the surface of the polysilicon layer 23 and the second semiconductor substrate 11 made of silicon are bonded. Next, in the same manner as in [Step-130], the first semiconductor substrate 10 is polished from the back surface side 10B of the first semiconductor substrate 10, and silicon (more specifically, the first The semiconductor layer 30 made of silicon (which constitutes the semiconductor substrate 10) is exposed. Thus, the semiconductor layer 30
SOI having an insulating layer 21 formed on one surface 30A of the SOI
A substrate having a structure is manufactured.

[Step-310] Next, similarly to [Step-140] of the first embodiment, a gate electrode portion 41 having a polycide structure is formed on the other surface 30B of the semiconductor layer 30.

[Step-320] Then, in the same manner as in [Step-150A] and [Step-150B] of the first embodiment, the first source portion containing impurities by ion implantation is added to the semiconductor layer 30. 46A and a first drain portion 47A are formed, and a first gate sidewall 44A made of SiO ₂ which is an insulating material is formed on the side wall of the gate electrode portion 41.
Is formed (see FIG. 6A).

[Step-330] Then, the semiconductor layer 30 outside the source portion (specifically, the first source portion 46A) is formed.
To form a first conductive region 51A made of a metal compound,
At the same time, the drain portion (specifically, the first drain portion 4
7A) the second semiconductor layer 30 made of a metal compound
Is formed. In the third embodiment, a metal layer 50A is formed on the other surface 30B of the semiconductor layer 30 on which the first and second conductive regions are to be formed (see FIG. 6B). Cobalt (Co), which is an element forming 50A, and Si, which is an element forming the semiconductor layer 30, are reacted in the same manner as in [Step-160] of Example 1. That is, the metal layer 50A is made of cobalt (C
o), the first and second conductive regions 51A, 52A
Is made of cobalt silicide (CoSi ₂ ). Note that, unlike the first embodiment, at this stage, the first and second conductive regions 51A and 52A are formed near the surface of the semiconductor layer 30 (see FIG. 7A). The metal layer 5 made of Co
It is necessary to form a TiN layer on the surface of 0A in [Step-
160] is preferable in preventing oxidation of the surface of the metal layer 50A. Incidentally, when the surface of the metal layer 50A is oxidized, the resistance increases.

[Step-340] Thereafter, through [Step-150C] and [Step-150D] of the first embodiment, the second source portion 46B, the second drain portion 47B and the second gate sidewall 44B are removed. (See FIG. 7B).

Thus, also in the third embodiment, from the channel portion 45 side, the first source portion 46A and the second source portion 46B containing an impurity at a higher concentration than the first source portion 46A are formed. A source part is formed. On the other hand, from the channel portion 45 side, a source portion including a first drain portion 47A and a second drain portion 47B containing an impurity at a higher concentration than the first drain portion 47A is formed. A first gate sidewall 44A made of an insulating material (SiO ₂ ) is formed on the side wall of the gate electrode portion and above each of the first source portion 46A and the first drain portion 47A. A second gate sidewall 44B made of an insulating material (SiO ₂ ) is formed above each of the second source portion 46B and the second drain portion 47B. In this state, the exposed region of the semiconductor layer 30 is a region sandwiched between the second gate sidewall 44B and the groove 20. In this region, the first and second conductive regions are further formed in the next step.

[Step-350] Thereafter, the semiconductor layer 30 outside the source portion (specifically, the second source portion 46B) is formed.
A first conductive region 51 made of a metal compound is further formed, and a second conductive region made of a metal compound is formed on the semiconductor layer 30 outside the drain portion (specifically, the second drain portion 47B). 52 are further formed. In the third embodiment, for this purpose, after a metal layer 50B made of Co is again formed on the entire surface by the sputtering method (see FIG. 8A), the same steps as [Step-160] of the first embodiment are performed. To form a first conductive region 51 in the semiconductor layer 30 surrounded by the second source portion 46B and the device isolation region 120, and the semiconductor surrounded by the second drain portion 47B and the device isolation region 120. A second conductive region 52 can be formed in the layer 30 (see FIG. 8B).

[Step-360] Next, by performing [Step-170] and [Step-180] of the first embodiment, a transistor element substantially similar to that shown in FIG. 5B is manufactured. Can be.

The following is a summary of the method for manufacturing the transistor element of Example 3 described above. A groove 20 is formed in the first semiconductor substrate 10 and a groove 2 is formed.
The insulating layer 21 is formed on the surface of the first semiconductor substrate 10 including zero. This step corresponds to a step of forming an insulating layer on one surface 30A of the semiconductor layer 30. The insulating layer 21 has a first
And a material that does not react with the metal element forming the second conductive region, and is made of silicon nitride (SiN) or silicon oxynitride (S
iON). After the second insulating layer 22 and the polysilicon layer 23 are formed on the insulating layer 21 and the polysilicon layer 23 is planarized, the first semiconductor substrate 1 is interposed via the polysilicon layer 23.
0 and the second semiconductor substrate 11 are bonded together. afterwards,
Polishing is performed from the back surface of the first semiconductor substrate 10 to expose the bottom of the groove 20 formed in the first semiconductor substrate 10. Thus, a substrate having a so-called SOI structure is manufactured. A gate electrode portion 41 is formed on the exposed region of the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30). In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), a first source portion 46A and a first drain portion 47A containing impurities are formed by an ion implantation method. A first gate sidewall 44A made of an insulating material is formed on the side wall of the gate electrode portion 41. After the metal layer 50A is formed on the entire surface, the elements constituting the metal layer 50A and the elements constituting the semiconductor layer 30 are reacted by heat treatment, and then the unreacted metal layer is removed. Is heat-treated in order to cause the element constituting the semiconductor layer 30 to react with the element constituting the semiconductor layer 30. Thus, the first conductive region 51A made of a metal compound is formed in the semiconductor layer 30 outside the source portion (more specifically, the first source portion 46A), and the drain portion (more specifically, the first conductive region 51A). A second conductive region 52A made of a metal compound is formed on the semiconductor layer 30 outside the first drain portion 47A).
Is formed. However, the first and second conductive regions 51A,
52A is formed near the surface of the semiconductor layer 30 and does not reach the insulating layer 21. In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), the second region containing a higher concentration of impurities than the first source portion 46A and the first drain portion 47A by an ion implantation method. The source part 46B and the second drain part 47B are formed. A second gate sidewall 44B is formed on a side surface of the first gate sidewall 44A. After forming the metal layer 50B on the entire surface, the elements constituting the metal layer 50B and the elements constituting the semiconductor layer 30 are reacted by heat treatment, and then the unreacted metal layer is removed. Is heat-treated in order to cause the element constituting the semiconductor layer 30 to react with the element constituting the semiconductor layer 30. As a result, the first conductive region 51 made of a metal compound is formed in the semiconductor layer 30 outside the source portion (more specifically, the second source portion 46B), and the drain portion (more specifically, the first conductive region 51). A second conductive region 52 made of a metal compound is formed in the semiconductor layer 30 outside the second drain portion 47B).

(Embodiment 4) The structure of the transistor element of Embodiment 4 is basically the same as that of Embodiment 1 shown in FIG. That is, in the fourth embodiment, the first conductive region 51 and the second conductive region 52 are mainly made of cobalt silicide. The first conductive region 51 and the second conductive region 52 include titanium silicide (TiSi ₂ ) and Ti
O _X is included. The transistor element of Example 4 differs from Example 1 or Example 2 and is manufactured by the method for manufacturing a transistor element according to the second aspect of the present invention.

The first conductive region 51 and the second conductive region 52 made of a metal compound (specifically, mainly cobalt silicide, CoSi ₂ ) are used for forming the source and drain regions of the semiconductor layer. On one surface 30A of the semiconductor layer 30 in the outer region, a metal layer 50 (specifically, a cobalt layer and a titanium layer) containing an element that reacts with an element (specifically, Si) constituting the semiconductor layer 30 is provided. After formation, heat treatment is performed, and the element (specifically, cobalt and titanium) forming the metal layer 50 is reacted with the element (specifically, Si) forming the semiconductor layer 30.

Hereinafter, the fourth embodiment will be described with reference to FIGS.
A transistor element and a method for manufacturing the same will be described.

First, a first conductive region 51 made of a metal compound is formed in a region of the semiconductor layer 30 outside the region where the source portion is to be formed, and the first conductive region 51 of the semiconductor layer 30 where the drain portion is to be formed is formed. A second metal compound in the outer region
Is formed. The metal compound is mainly composed of cobalt silicide (CoSi ₂ ), and further includes titanium silicide (TiSi ₂ ) and TiO _X.

[Step-400] For this purpose, first, on the one surface 30A of the semiconductor layer 30 (specifically, the first semiconductor substrate A groove 20 is formed on one surface 10A of the groove 10).

[Step-410] Then, a silicon nitride (SiN) layer 100 and a silicon oxide (SiO ₂ ) layer 10 are formed on one surface 10A of the first semiconductor substrate 10 including the inside of the trench 20.
1 in the order of LP-CVD and bias ECR-CV
D is deposited by a method D, and thereafter, a flattening process is performed.
The silicon oxide layer 101 and the silicon nitride layer 100 are left only inside. As a result, an element isolation region is formed. This state is shown in a schematic partial cross-sectional view in FIG. (Deposition conditions of silicon nitride layer) Gas used: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 90/600 /
1000 sccm Pressure: 53 Pa Temperature: 700 ° C. Film thickness: 50 nm (Silicon oxide layer deposition conditions) Gas used: SiH ₄ / N ₂ O / Ar = 14/35/72
sccm Microwave: 1000 W Temperature: 400 ° C. Pressure: 0.093 Pa Film thickness: 0.4 μm

[Step-420] Next, after forming the metal layer 50 on one surface 30A of the semiconductor layer 30 (specifically, on one surface 10A of the first semiconductor substrate 10), After patterning the metal layer 50 and leaving the metal layer 50 on one surface 30A of the semiconductor layer 30 on which the first and second conductive regions are to be formed, Co / Ti which is an element constituting the metal layer 50 is used.
And Si, which is an element constituting the semiconductor layer 30, are reacted. The metal layer 50 is made of Co / Ti as in the second embodiment, and the first and second conductive regions 51 and 52 are mainly made of cobalt silicide (CoSi ₂ ). In addition, titanium silicide (TiSi ₂ ) and TiO _X is included.

More specifically, first, titanium and cobalt are sequentially deposited on the entire surface of one surface 30A of the semiconductor layer 30 by the sputtering method under the same conditions as in Embodiment 2 to form the metal layer 50 (FIG. 9 (B)). The thickness of the Co layer constituting the metal layer 50 may be set to a thickness equal to or greater than a thickness necessary for reacting all of Si corresponding to the thickness of the semiconductor layer 30 made of Si, for example, 0.1 μm. In FIGS. 9B and 9C, the first semiconductor substrate 10 is hatched roughly to clearly show the semiconductor layer 30. FIG.

Next, the metal layer 50 made of Co / Ti is patterned to leave the metal layer 50 on one surface 30A of the semiconductor layer 30 on which the first and second conductive regions are to be formed (FIG. 9). (C)). Note that the metal layer on the groove 20 does not have to be removed. That is, the metal layer 50 above the region of the semiconductor layer where the channel portion, the source portion, and the drain portion are to be formed is removed. The dry etching conditions for the metal layer 50 are exemplified below. Working gas: BCl ₃ / Cl ₂ = 60/90 sccm Pressure: 0.016 Pa Microwave power: 1000 W RF power: 50 W

Thereafter, the Co / Ti constituting the metal layer 50 is formed.
And Si constituting the semiconductor layer 30 are reacted with each other to form a metal compound (specifically, mainly cobalt silicide,
(Including titanium silicide and TiO _x ). The regions of the semiconductor layer 30 that react with the metal layer 50 are a region sandwiched between the region where the source portion is to be formed and the trench 20, and a region sandwiched between the region where the drain portion is to be formed and the trench 20. The second conductive regions 51 and 52 are formed (see FIG. 9D). The reaction between the element constituting the metal layer 50 and the element constituting the semiconductor layer 30 can be carried out in the same process as in [Step-160] of the first embodiment, and a detailed description thereof will be omitted.

[Step-430] Thereafter, for example, SiH ₂
An insulating layer 21 made of silicon oxynitride (SiON) is entirely formed by LP-CVD using a CVD method using Cl ₂ / N ₂ O / N _2.
It is deposited by the method. This insulating layer 21 is formed by [Step-42]
0] formed in the first and second conductive regions 51, 52
Is composed of a material (specifically, SiON) that does not react with the metal element (specifically, Co) that constitutes. The insulating layer 21 is formed of silicon oxide (SiO ₂ ) formed in the next step.
A second insulating layer made of the first and second conductive regions 5
1 and 52 have a function of preventing the reaction. Therefore, generation of voids in the first conductive region 51 and the second conductive region 52 can be reliably prevented. (Film formation conditions of insulating layer 21 made of silicon oxynitride) Gas used: SiH ₂ Cl ₂ / NH ₃ / N ₂ / O ₂ = 50/2
00/200/50 sccm Pressure: 600 Pa Temperature: 400 ° C. Film thickness: 100 nm

[Step-440] Thereafter, a second insulating layer 22 made of, for example, silicon oxide (SiO ₂ ) having a thickness of 0.4 μm is formed on the insulating layer 21 in the same manner as illustrated in [Step-410]. Is deposited by the bias ECR-CVD method under the following conditions.

[Step-450] Then, a polysilicon layer 23 is formed on the second insulating layer 22 under the same conditions as in [Step-120] of the first embodiment, and then the polysilicon layer 23 is etched back. 23 (see FIG. 10A),
The surface of the polysilicon layer 23 is bonded to the second semiconductor substrate 11 made of silicon (see FIG. 10B). Thereafter, the first semiconductor substrate 10 is polished from the back surface 10B of the first semiconductor substrate 10 in the same manner as in [Step-130] of the first embodiment, and silicon (more specifically, Exposes a semiconductor layer 30 made of silicon (which constitutes the first semiconductor substrate 10) (FIG. 1).
1 (A)). Thus, the insulating layer 21 is formed on one surface 30A of the semiconductor layer 30, and a substrate having an SOI structure is manufactured. The semiconductor layer 30 of this substrate has a first
And second conductive regions 51 and 52 are formed. still,
When the first semiconductor substrate 10 is polished from the back surface 10B of the first semiconductor substrate 10, the first and second conductive regions 5 are polished.
1, 52 and silicon nitride (SiN) present on the bottom surface of the groove 20 serve as a polishing stopper, so that excessive removal of the semiconductor layer 30 can be reliably prevented.

[Step-460] Thereafter, [Step-140] to [Step-150D] of Example 1 are executed (this state is shown in FIG. 11B), and further, [Step-170]
And [Step-180], to complete the MOS transistor having the SOI structure shown in FIG. Note that the second gate sidewall 44B need not be formed. First conductive regions 51A and 51B are surrounded by insulating layer 21, silicon nitride layer 100, and second source portion 46B. On the other hand, the second conductive regions 52A and 52B are formed by the insulating layer 21, the silicon nitride layer 100, and the second drain portion 47.
It is surrounded by B. FIG. 12 shows a state where a metal wiring material layer 62 is deposited on the interlayer insulating layer 60 including the opening 61. Note that the width of the second source part 46A and the second drain part 47B to be formed in the semiconductor layer 30 is determined by the critical misalignment amount in the exposure apparatus used for patterning the metal layer 50 and patterning the gate electrode part 41, respectively. Is preferably designed to have a width of at least twice the sum of If the width is not set, the region of the semiconductor layer on which the second source portion 46B or the second drain portion 47B is to be formed becomes too narrow due to misalignment in the exposure apparatus. This is because there is no longer any region of the semiconductor layer where the portion 46B or the second drain portion 47B is to be formed.

The following is a summary of the method for manufacturing the transistor element of Example 4 described above. A groove 20 is formed in the first semiconductor substrate 10 and a groove 2 is formed.
0 is filled with an insulating material to form an element isolation region. A metal layer 50 is formed on a region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30) where the first and second conductive regions 51 and 52 are to be formed. That is, after the metal layer 50 is formed on the first semiconductor substrate 10, the metal layer above the region of the semiconductor layer where the channel, source, and drain portions are to be formed is removed. Then, the elements constituting the metal layer 50 and the elements constituting the semiconductor layer 30 (the first semiconductor substrate 10) are reacted by heat treatment, and then the unreacted metal layer is removed. Is heat-treated in order to cause the element constituting the semiconductor layer 30 to react with the element constituting the semiconductor layer 30. Thereby, the source section (the first source section 46)
A and the semiconductor layer 3 on which the second source portion 46B) is to be formed
A first conductive region 51 made of a metal compound is formed in a region outside the region 0, and at the same time, a semiconductor layer 30 on which a drain portion (a first drain portion 47A and a second drain portion 47B) is to be formed is formed. A second conductive region 52 made of a metal compound is formed in a region outside the region. An insulating layer 21 is formed on the entire surface. This step corresponds to a step of forming the insulating layer 21 on one surface 30A of the semiconductor layer 30. The insulating layer 21 is made of a material that does not react with the metal elements forming the first and second conductive regions 51 and 52, and is made of silicon nitride (SiN) or silicon oxynitride (S
iON). After the second insulating layer 22 and the polysilicon layer 23 are formed on the insulating layer 21 and the polysilicon layer 23 is flattened, the polysilicon layer 23 and the second semiconductor substrate 11 are bonded. Thereafter, polishing is performed from the back surface of the first semiconductor substrate 10 to expose the bottom of the groove 20 formed in the first semiconductor substrate 10. Thus, a substrate having a so-called SOI structure is manufactured. A gate electrode portion 41 is formed on the exposed region of the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30). In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), a first source portion 46A and a first drain portion 47A containing impurities are formed by an ion implantation method. A first gate sidewall 44A made of an insulating material is formed on the side wall of the gate electrode portion 41. In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), the second region containing a higher concentration of impurities than the first source portion 46A and the first drain portion 47A by an ion implantation method. The source part 46B and the second drain part 47B are formed. If necessary, the first gate side wall 44A
A second gate side wall 44B is formed on the side surface of.

Fifth Embodiment A fifth embodiment is a modification of the fourth embodiment. That is, in the fifth embodiment, first, [step-400] to [step-450] of the fourth embodiment are executed. still,
FIGS. 13 and 14 are schematic partial cross-sectional views of a semiconductor substrate and the like obtained in these steps. It should be noted that FIG.
(D) and (A) and (B) of FIG. 14 are (A) of FIG.
(D) and (A) and (B) of FIG.
The fifth embodiment differs from the fourth embodiment in that the semiconductor layer 30
In the thickness direction of the first layer based on the metal layer 50A.
It is not necessary to form the conductive region 51A and the second conductive region 52A. That is, the thickness of the metal layer 50A can be smaller than that of the fourth embodiment.

Thereafter, the first conductive region 5 of the semiconductor layer 30
The portion above 1A and the second conductive region 52A (the remaining portion in the thickness direction) is silicided. Specifically, the same steps as those in [Step-420] of the fourth embodiment may be performed. That is, after the metal layer 50B is formed on the other surface 30B of the semiconductor layer 30 (see FIG. 15A), the metal layer 5B is formed.
0B is patterned to form a metal layer 50B on the other surface 30B of the semiconductor layer 30 where the first and second conductive regions are to be formed.
Is left, Co /, which is an element constituting the metal layer 50B,
The Ti is reacted with Si which is an element constituting the semiconductor layer 30. The metal layer 50B is made of Co / Ti as in the fourth embodiment, and the first and second conductive regions 51 and 52 are mainly made of cobalt silicide, and further include titanium silicide and TiO _X. FIG. 15B shows a state where the first conductive region 51B and the second conductive region 52B are formed.

Thereafter, [Step-140] of Example 1
By performing [Step-150D], the SOI structure shown in FIG. 16A can be obtained. The second
The gate side wall 44B need not be formed.
Further, [Step-170] and [Step-180] of Example 1
Is executed, the SOI shown in FIG.
A MOS transistor having a structure is completed. In the fifth embodiment, the first and second layers are formed from both surfaces of the semiconductor layer 30.
Since the conductive regions 51A, 51B, 52A, and 52B are formed, all of the semiconductor layer 30 in the thickness direction can be reliably formed as the conductive regions. In the fifth embodiment, even if the metal layer 50A and the metal layer 50B are made of the same kind of metal,
It may be composed of different kinds of metals.

The following is a summary of the method for manufacturing the transistor element of the fifth embodiment. A groove 20 is formed in the first semiconductor substrate 10 and a groove 2 is formed.
0 is filled with an insulating material to form an element isolation region. A metal layer 50A is formed on a region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30) where the first and second conductive regions 51A and 52A are to be formed. That is, after forming the metal layer 50A on the first semiconductor substrate 10, the metal layer above the region of the semiconductor layer where the channel portion, the source portion, and the drain portion are to be formed is removed. Then, the elements constituting the metal layer 50A and the semiconductor layer 30 (the first semiconductor substrate 10)
Are reacted by applying a heat treatment to the elements constituting the semiconductor layer 30. Then, a heat treatment is performed to remove the unreacted metal layer and to further react the elements constituting the metal layer 50A with the elements constituting the semiconductor layer 30. Apply. Thereby, the source section (specifically, the first source section 46A and the second source section 46A)
A first conductive region 51A partially made of a metal compound is formed in a region (in the thickness direction of the semiconductor layer 30) outside the region of the semiconductor layer 30 where B) is to be formed. Specifically, the first drain portion 47A and the second drain portion 47B) are formed of a metal compound partially (in the thickness direction of the semiconductor layer 30) outside the region of the semiconductor layer 30 where the semiconductor layer 30 is to be formed. Two conductive regions 52A are formed. An insulating layer 21 is formed on the entire surface. This step corresponds to a step of forming the insulating layer 21 on one surface 30A of the semiconductor layer 30. The insulating layer 21 is made of a material that does not react with the metal elements forming the first and second conductive regions 51 and 52, and is made of silicon nitride (SiN) or silicon oxynitride (S
iON). After the second insulating layer 22 and the polysilicon layer 23 are formed on the insulating layer 21 and the polysilicon layer 23 is flattened, the polysilicon layer 23 and the second semiconductor substrate 11 are bonded. Thereafter, polishing is performed from the back surface of the first semiconductor substrate 10 to expose the bottom of the groove 20 formed in the first semiconductor substrate 10. Thus, a substrate having a so-called SOI structure is manufactured. A metal layer 50B is formed on a region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30) where the first and second conductive regions 51B and 52B are to be formed. That is, after the metal layer 50B is formed on the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30), the channel portion, the source portion, and the drain portion are formed above the semiconductor layer region. The metal layer is removed. Then, the elements constituting the metal layer 50B and the elements constituting the semiconductor layer 30 (the first semiconductor substrate 10) are reacted by heat treatment, and then the unreacted metal layer 50B is removed. Heat treatment is performed to cause an element constituting 50B and an element constituting the semiconductor layer 30 to react with each other. Thereby, the source section (specifically, the first source section 46A and the second source section 46A)
A first conductive region 51B made of a metal compound is formed in the remaining portion in the thickness direction of the region outside the region of the semiconductor layer 30 where B) is to be formed, and the drain portion (specifically, The first drain portion 47A and the second drain portion 47
A second conductive region 52B made of a metal compound is formed in the remaining portion in the thickness direction of the region outside the region of the semiconductor layer 30 where B) is to be formed. A gate electrode portion 41 is formed on the exposed region of the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30). In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), a first source portion 46A and a first drain portion 47A containing impurities are formed by an ion implantation method. Next, a first gate sidewall 44A made of an insulating material is formed on the side wall of the gate electrode portion 41. In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), the second region containing a higher concentration of impurities than the first source portion 46A and the first drain portion 47A by an ion implantation method. The source part 46B and the second drain part 47B are formed. Next, as necessary, a second gate sidewall 44B is formed on the side surface of the first gate sidewall 44A.

(Embodiment 6) Embodiment 6 is a modification of Embodiment 4. That is, in the sixth embodiment, first, [Step-400] to [Step-450] of the fourth embodiment are executed (FIG. 1).
17 (A)). However, also in the sixth embodiment, unlike the fourth embodiment, it is not necessary to form the first conductive region 51A and the second conductive region 52A based on the metal layer 50A in the entire thickness direction of the semiconductor layer 30. That is, the thickness of the metal layer 50A can be smaller than that of the fourth embodiment.

In the fifth embodiment, the semiconductor layer 3
The portion above the first conductive region 51A and the second conductive region 52A (the remaining portion in the thickness direction) was silicided. On the other hand, in the sixth embodiment, by executing [Step-140] to [Step-150D] of the first embodiment, the SOI structure shown in FIG. 17B can be obtained.

Thereafter, the first conductive region 5 of the semiconductor layer 30
The portion above 1A and the second conductive region 52A (the remaining portion in the thickness direction) is silicided. Specifically, the same steps as those in [Step-420] of the fourth embodiment may be performed. That is, after the metal layer 50B is formed on the entire surface of the semiconductor layer 30 (see FIG. 18A), Co / Ti as an element forming the metal layer 50B and Si as an element forming the semiconductor layer 30 are formed. Is reacted. Example 4 of the metal layer 50B
Similarly, the first and second conductive regions 51 and 52 are mainly made of cobalt silicide, and further include titanium silicide and TiO _X. First
FIG. 18B shows a state in which the conductive region 51B and the second conductive region 52B are formed.

Thereafter, [Step-17] of Example 1 was further performed.
0] and [Step-180], the SO
A MOS transistor having an I structure is completed. Also in the sixth embodiment, since the first and second conductive regions 51A, 51B, 52A, and 52B are formed from both surfaces of the semiconductor layer 30, it is ensured that the entire semiconductor layer 30 in the thickness direction is a conductive region. it can. In the sixth embodiment, the metal layer 50A and the metal layer 50B may be made of the same metal or different metals.

The following is a summary of the method for manufacturing the transistor element of Example 6 described above. A groove 20 is formed in the first semiconductor substrate 10 and a groove 2 is formed.
0 is filled with an insulating material to form an element isolation region. A metal layer 50A is formed on a region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30) where the first and second conductive regions 51A and 52A are to be formed. That is, after forming the metal layer 50A on the first semiconductor substrate 10, the metal layer above the region of the semiconductor layer where the channel portion, the source portion, and the drain portion are to be formed is removed. Then, the elements constituting the metal layer 50A and the semiconductor layer 30 (the first semiconductor substrate 10)
Are reacted by applying a heat treatment to the elements constituting the semiconductor layer 30. Then, a heat treatment is performed to remove the unreacted metal layer and to further react the elements constituting the metal layer 50A with the elements constituting the semiconductor layer 30. Apply. Thereby, the source section (specifically, the first source section 46A and the second source section 46A)
A first conductive region 51A partially made of a metal compound is formed in a region (in the thickness direction of the semiconductor layer 30) outside the region of the semiconductor layer 30 where B) is to be formed. Specifically, the first drain portion 47A and the second drain portion 47B) are formed of a metal compound partially (in the thickness direction of the semiconductor layer 30) outside the region of the semiconductor layer 30 where the semiconductor layer 30 is to be formed. Two conductive regions 52A are formed. An insulating layer 21 is formed on the entire surface. This step corresponds to a step of forming the insulating layer 21 on one surface 30A of the semiconductor layer 30. The insulating layer 21 is made of a material that does not react with the metal elements forming the first and second conductive regions 51 and 52, and is made of silicon nitride (SiN) or silicon oxynitride (S
iON). After the second insulating layer 22 and the polysilicon layer 23 are formed on the insulating layer 21 and the polysilicon layer 23 is flattened, the polysilicon layer 23 and the second semiconductor substrate 11 are bonded. Thereafter, polishing is performed from the back surface of the first semiconductor substrate 10 to expose the bottom of the groove 20 formed in the first semiconductor substrate 10. Thus, a substrate having a so-called SOI structure is manufactured. A gate electrode portion 41 is formed on the exposed region of the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30). In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), a first source portion 46A and a first drain portion 47A containing impurities are formed by an ion implantation method. Next, a first gate sidewall 44A made of an insulating material is formed on the side wall of the gate electrode portion 41. In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), the second region containing a higher concentration of impurities than the first source portion 46A and the first drain portion 47A by an ion implantation method. The source part 46B and the second drain part 47B are formed. Next, a second gate sidewall 44B is provided on the side surface of the first gate sidewall 44A.
To form After forming the metal layer 50B on the entire surface, the elements constituting the metal layer 50B and the elements constituting the semiconductor layer 30 are reacted by heat treatment, and then the unreacted metal layer is removed. Is heat-treated in order to cause the element constituting the semiconductor layer 30 to react with the element constituting the semiconductor layer 30. Thereby, the source unit (specifically, the second source unit 4
6B), a first conductive region 51B made of a metal compound is formed in the remaining portion in the thickness direction of the region of the semiconductor layer 30 outside the drain region (specifically, the second drain region 47B). A second conductive region 52B made of a metal compound is formed in the remaining portion in the thickness direction of the region outside the region of the semiconductor layer 30 outside the region (1).

Example 7 Example 7 relates to a method for manufacturing a transistor element according to the third aspect of the present invention. The structure of the transistor element described in Embodiments 1 to 6 is basically a bond SOI structure (substrate bonded SOI structure).
I structure). On the other hand, the transistor element of Example 7 has a so-called SIMOX structure.
This is the same as the structure of the transistor element described in the first to sixth embodiments. Also in the seventh embodiment, the first conductive region 51 and the second conductive region 52 are made of cobalt silicide.

FIG. 19 shows the structure of the semiconductor device of the seventh embodiment. In the semiconductor device of the seventh embodiment, the insulating layer 21A
Is made of a material that does not react with the metal element forming the first and second conductive regions, specifically, silicon nitride (SiN). The insulating layer 21A is formed by implanting ions into the inside of the semiconductor substrate 10A. The portion of the semiconductor substrate above the insulating layer 21A corresponds to the semiconductor layer 30. Note that a second insulating layer 22A made of SiO ₂ is formed below the insulating layer 21A by an ion implantation method. That is, the semiconductor element in the seventh embodiment is a so-called S
It has an IMOX structure.

Except for the above points, the semiconductor device of Example 7 can be substantially the same as the method of manufacturing the semiconductor device of Example 1.

Hereinafter, a transistor element of Example 7 and a method of manufacturing the same will be described with reference to FIG.

[Step-700] First, a second insulating layer 22A made of SiO ₂ is formed by implanting oxygen ions into the inside of the semiconductor substrate 10 by a known method. Note that the depth of the second insulating layer 22A is 0.1 μm.
It should be about the degree.

[Step-710] Next, nitrogen ions are implanted into the insulating layer 21A inside the semiconductor substrate 10A.
Thus, the insulating layer 21 made of silicon nitride (SiN)
A is formed, and a semiconductor layer 30 can be obtained in a portion of the semiconductor substrate 10A above the A (see FIG. 20A). The ion implantation conditions for nitrogen ions are exemplified below.
Incidentally, the average range R _p in the ion implantation is the semiconductor substrate 1
The depth may be about the depth from the surface of 0A to the upper surface of the second insulating layer 22A. Ion: N Dose: 5 × 10 ¹⁷ / cm ² Acceleration voltage: 500 keV

Next, after a device isolation region 120 having, for example, a LOCOS structure is formed by a known method, a gate electrode portion 41 is formed on the semiconductor layer 30, and then a source portion and a drain portion are formed on the semiconductor layer 30. Is formed, and a channel portion 45 is formed in the semiconductor layer 30 below the gate electrode portion 41.

[Step-720] Specifically, [Step-140] to [Step-150D] of Example 1 are executed (see FIG. 20 (B)).

[Step-730] Thereafter, the semiconductor layer 30 outside the source portion (specifically, the second source portion 46B) is formed.
A first conductive region 51 made of a metal compound is formed at the same time, and a drain portion (specifically, a second drain portion 47) is formed.
A second conductive region 52 made of a metal compound is formed in the semiconductor layer 30 outside (B) (see FIG. 19). That is, in the seventh embodiment, for this purpose, after forming the metal layer 50 on the semiconductor layer 30 where the first and second conductive regions are to be formed,
Cobalt (Co), which is an element forming the metal layer 50, and Si, which is an element forming the semiconductor layer 30, are reacted.
That is, the metal layer 50 is made of cobalt (Co), and the first and second conductive regions 51 and 52 are made of cobalt silicide (C
oSi ₂ ).

Specifically, first, a metal layer 50 made of cobalt is deposited on the entire surface by sputtering (see FIG. 20C). The thickness of the metal layer 50 is set to a thickness equal to or greater than a thickness necessary for reacting all of Si corresponding to the thickness of the semiconductor layer 30 made of Si. For example, the conditions for forming the metal layer 50 made of Co with a thickness of 50 nm are exemplified below. Gas used: Ar = 100 sccm Pressure: 0.47 Pa DC power: 1 kW Film thickness: 50 nm

Next, C, which is an element constituting the metal layer 50, is used.
o and Si, which is an element constituting the semiconductor layer 30, are reacted to form a metal compound (specifically, cobalt silicide, C
oSi ₂ ). The region of the semiconductor layer 30 that reacts with the metal layer 50 is a region sandwiched between the second gate sidewall 44B and the groove 20, and the first and second conductive regions 51 and 52 are formed in this region. The reaction between the element constituting the metal layer 50 and the element constituting the semiconductor layer 30 is as follows.
It is desirable to carry out the following steps, but the conditions are not limited to the following examples.

First, the element (specifically, Si) forming the semiconductor layer 30 reacts with the transition metal (specifically, Co) forming the metal layer 50, and the element (specifically, Co) forming the semiconductor layer 30 reacts. Specifically, an oxide composed of Si) (specifically, S
It is desirable that the element forming the metal layer 50 and the element forming the semiconductor layer 30 react at a temperature at which the iO ₂ ) does not react with the transition metal (specifically, Co) forming the metal layer 50. Specifically, nitrogen gas (flow rate: 5 liters /
), A heat treatment (first heat treatment) of, for example, 500 ° C. × 30 seconds is performed. Thus, CoSi _X is generated.

Next, the unreacted metal layer is removed by immersing it in, for example, ammonia peroxide (a mixed aqueous solution of NH ₄ OH and H ₂ O ₂ ) for about 10 minutes. The unreacted metal layer is a metal layer deposited on the element isolation region 120 having the LOCOS structure, on the gate sidewalls 44A and 44B, and on the gate electrode portion 41. Thus, the first conductive region 51 made of a metal compound is formed in the semiconductor layer 30 outside the source portion (specifically, the second source portion 46B), and the drain portion (specifically, the second conductive portion 46B) is formed. A second conductive region 52 made of a metal compound is formed in the semiconductor layer 30 outside the second drain portion 47B).

Thereafter, in a nitrogen gas atmosphere (flow rate: 5 liter / min), a second heat treatment is performed, for example, at 700 ° C. for 30 seconds to change CoSi _X to CoSi ₂ . Note that, in these first and second heat treatments, the metal element (specifically, Co) forming the first and second conductive regions 51 and 52 is used.
The insulating layer 21 made of a material (specifically, SiN) that does not react with the first conductive region 51 or the second conductive layer 51 is formed.
Generation of voids in the conductive region 52 can be reliably prevented. As a result, the resistance values of the first and second conductive regions 51 and 52 do not vary, and a highly reliable transistor element can be manufactured. Thus, the transistor element shown in FIG. 17 is manufactured.

[Step-740] Thereafter, [Step-170] and [Step-180] of the first embodiment are executed, and SIMOX is performed.
A MOS transistor having a structure is completed.

(Eighth Embodiment) An eighth embodiment is a modification of the seventh embodiment. Hereinafter, a method for manufacturing a transistor element in Example 8 will be described with reference to FIGS.

[Step-800] First, a second insulating layer 22A made of SiO ₂ is formed by ion implantation of oxygen ions into the semiconductor substrate 10 by a known method. Note that the depth of the second insulating layer 22A is 0.1 μm.
It should be about the degree.

[Step-810] Next, nitrogen ions of the insulating layer 21A are implanted into the semiconductor substrate 10A under the same conditions as in [Step-710] of the seventh embodiment. As a result, the insulating layer 21A made of silicon nitride (SiN) is formed, and the semiconductor layer 30 can be obtained above the semiconductor substrate 10A. Next, after forming an element isolation region 120 having a LOCOS structure, for example, by a known method, the semiconductor layer 30 is formed in the same manner as in [Step-140] of the first embodiment.
The gate electrode part 41 is formed thereon.

[Step-820] After that, a first source part 46A and a first drain part 47A are formed in the semiconductor layer 30. Specifically, [Step-150A] and [Step-150B] of the first embodiment are executed.

[Step-830] After that, a metal layer made of Co is formed on the entire surface by a sputtering method, and then the same steps as in [Step-160] of the first embodiment are performed. The first conductive region 51A can be formed in a region near the surface of the semiconductor layer 30 surrounded by 46A and the element isolation region 120. On the other hand, the second conductive region 52A can be formed in a region near the surface of the semiconductor layer 30 surrounded by the first drain portion 47A and the element isolation region 120. This state is shown in FIG. Note that the first and second conductive regions 51A and 52A do not reach the insulating layer 21A.

[Step-840] Next, by executing [Step-150C] and [Step-150D] of the first embodiment, the second source portion 46B and the second drain portion 4 are formed.
7B and the second gate sidewall 44B are formed.

[Step-850] Thereafter, the semiconductor layer 30 outside the source portion (specifically, the second source portion 46B) is formed.
A first conductive region 51 made of a metal compound is further formed, and a second conductive region made of a metal compound is formed on the semiconductor layer 30 outside the drain portion (specifically, the second drain portion 47B). 52 are further formed. In Example 8, for this purpose, after a metal layer 50B made of Co was formed again by sputtering on the entire surface (see FIG. 21B).
The first conductive region 51 is formed in the semiconductor layer 30 surrounded by the second source portion 46B and the element isolation region 120 by going through the same step as [Step-160] of the first embodiment. The second conductive region 52 can be formed in the semiconductor layer 30 surrounded by the drain portion 47B and the element isolation region 120.

[Step-860] After that, [Step-170] and [Step-180] of Example 1 are executed, and SIMOX is performed.
A MOS transistor having a structure is completed.

Ninth Embodiment A ninth embodiment is a modification of the first embodiment. In Example 9, [Step-16] of Example 1 was used.
0] instead of the selected tungsten CV exemplified below.
Method D is performed to replace the semiconductor layer 30 with a metal layer made of tungsten. Thereby, the first conductive region made of metal is formed in the semiconductor layer outside the source portion, and the second conductive region made of metal is formed in the semiconductor layer outside the drain portion. Gas used: WF ₆ / H ₂ / SiH ₄ = 10/500/1
0 sccm Temperature: 260 ° C Pressure: 26.6 Pa

Note that a selective tungsten CVD method was performed,
The operation of replacing the semiconductor layer 30 with a metal layer made of tungsten includes steps corresponding to [Step-420] in Example 4, two steps [Step-420] in Examples 5 and 6,
It can be applied to [Step-730] in the seventh embodiment.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The various conditions described in the embodiments are merely examples, and can be changed as appropriate.

As shown in a schematic partial cross-sectional view of FIG. 22A, the thickness of the semiconductor layer 30 on which the channel portion 45 is formed is changed by the thickness of the semiconductor layer on which the source portion 46 and the drain portion 47 are formed. The thickness may be smaller than 30. Thus, even when the semiconductor layer 30 is thinned, it is possible to prevent the conductive region from being lost by dry etching when the contact hole is formed, and to prevent an increase in contact resistance. In order to fabricate such a structure, first, as in [Step-100] of Example 1, the first
A groove 20 is formed on one surface 10A of the semiconductor substrate 10 (see FIG. 22B), and then a resist is applied and dried again on the one surface 10A of the first semiconductor substrate 10.
The resist is patterned using a photolithography technique. Next, using the patterned resist as a mask, the first semiconductor substrate 10 is etched to form a recess in the semiconductor layer 30 in a region where a channel portion is to be formed (see FIG. 22C). The etching conditions can be the same as the conditions for forming the groove. As a result, the channel portion 45 is finally formed above the concave portion (below the concave portion in FIG. 22C).
5 can be made thinner than the thickness of the semiconductor layer 30 on which the source part 46 and the drain part 47 are formed.

In the embodiments, the MOS transistor has been described as an example of the transistor element, but the other transistor element may be a bipolar transistor, a TFT, or a CCD. As a transition metal constituting the metal layer, in addition to cobalt, Ti, N
i, Mo, W, Cu, Zr and Hf. As the metal compound, in addition to silicide, Ti
W, TiN, TiB, and WB can be exemplified. On the other hand, examples of the noble metal forming the metal layer include Pt and Au. The second insulating layer, in addition to _{SiO 2, BPSG, PSG, BSG} , AsSG, PbSG,
It can be composed of a known insulating material such as SbSG or SOG, or a laminate of these insulating layers. The structure of the wiring layer is also an example, and can be changed as appropriate.

[0145]

Since the insulating layer made of a material that does not react with the metal element constituting the first and second conductive regions is formed, voids are generated in the formed first and second conductive regions. Can be effectively suppressed.

In addition, the source and drain portions, from the channel portion side, include a first source portion, a first drain portion, and a second source and drain portion containing impurities at a higher concentration than the second source and drain portions. Since it is composed of the second source part and the second drain part, the PN junction breakdown voltage between the source or drain part and the channel part can be improved.

Further, in the transistor element according to the present invention, since the first and second conductive regions are formed outside the source part and the drain part, when the transistor element is turned on, holes or electrons are formed in the semiconductor element. When moving in the layer, silicon atoms in a region where holes or electrons move are ionized, but are absorbed from the channel portion into the first and second conductive regions through the source portion and the drain portion, and are absorbed by the channel portion. Does not accumulate. As a result, it is possible to avoid the problem that the breakdown voltage between the source part and the drain part deteriorates. Further, since the first and second conductive regions are formed, even if the semiconductor layer is thinned,
The sheet resistance of the source portion and the drain portion can be reduced by two to four digits as compared with the conventional transistor element, and the response speed of the transistor element can be improved.

Conventionally, as long as the design rules permit, the source / drain portion is made as large as possible, and the resistance value of the source / drain portion is kept low. In the case of forming titanium silicide, it is necessary to make the source and drain portions large enough not to cause the thin wire effect. However, when cobalt silicide is used, the problem of the thin wire effect can be avoided, so that the size of the source / drain portion can be reduced. As a result, the resistance value of the source / drain portion can be reduced and M
The driving capability of the OS transistor can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a transistor element of Example 1.

FIGS. 2A and 2B are schematic partial cross-sectional views of a semiconductor substrate and the like in each step for describing a method for manufacturing a transistor element of Example 1. FIGS.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element of Example 1 following FIG. 2;

FIG. 4 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining the method for manufacturing the transistor element of Example 1 following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining the method for manufacturing the transistor element of Example 1 following FIG. 4;

FIGS. 6A to 6C are schematic partial cross-sectional views of a semiconductor substrate and the like in each step for describing a method for manufacturing a transistor element of Example 3. FIGS.

FIGS. 7A and 7B are schematic partial cross-sectional views of a semiconductor substrate and the like in each step for describing a method for manufacturing the transistor element of Example 3 following FIGS.

FIG. 8 is a schematic partial cross-sectional view of the semiconductor substrate and the like in each step for explaining the method for manufacturing the transistor element of Example 3 following FIG. 7;

FIG. 9 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing a transistor element of Example 4.

FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining the method for manufacturing the transistor element of Example 4 following FIG. 9;

11 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining the method for manufacturing the transistor element of Example 4 following FIG. 10; FIG.

FIG. 12 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining the method for manufacturing the transistor element of Example 4 following FIG. 11;

FIG. 13 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for illustrating a method for manufacturing a transistor element of Example 5.

14 is a schematic partial cross-sectional view of a semiconductor substrate or the like in each step for describing a method for manufacturing a transistor element of Example 5 following FIG. 13; FIG.

FIG. 15 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for describing a method for manufacturing a transistor element of Example 5 following FIG. 13;

FIG. 16 is a schematic partial cross-sectional view of the semiconductor substrate and the like in each step for explaining the method for manufacturing the transistor element of Example 5 following FIG.

FIGS. 17A and 17B are schematic partial cross-sectional views of a semiconductor substrate and the like in each step for explaining a method for manufacturing a transistor element of Example 6. FIGS.

FIG. 18 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining the method for manufacturing the transistor element of Example 6 following FIG. 17;

FIG. 19 is a schematic partial cross-sectional view of a transistor element of Example 7.

FIG. 20 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for illustrating a method for manufacturing a transistor element of Example 7.

FIG. 21 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for describing a method for manufacturing a transistor element in Example 8.

FIG. 22 is a schematic partial cross-sectional view of a modified example of the transistor element of Example 1.

FIG. 23 is a schematic partial cross-sectional view of a semiconductor substrate or the like for describing a method for manufacturing a MOS transistor using a conventional SOI technique.

24 is a schematic partial cross-sectional view of a semiconductor substrate or the like for illustrating a method for manufacturing a MOS transistor using a conventional SOI technique, following FIG. 23;

[Explanation of symbols]

10, 11: silicon semiconductor substrate, 20: groove, 21, 21A: insulating layer, 22, 22A: second insulating layer, 23: polysilicon layer, 30: semiconductor Layer, 40 gate oxide film, 41 gate electrode portion, 42 polysilicon film, 43 WSi ₂
Layer, 44A... First gate side wall, 44B
... Second gate side wall, 45... Channel part, 46A... First source part, 46B.
Source part, 47A... First drain part, 47B
..Second drain portion, 50, 50A, 50B... Metal layer, 51, 51A, 51B, 52, 52A, 52B
..Conductive region, 60 ... interlayer insulating layer, 61 ... opening, 62 ... metal wiring material layer, 120 ... element isolation region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/78 627D

Claims (34)

[Claims] 1. A transistor element in which a channel portion, a source portion, and a drain portion are formed in a semiconductor layer formed on an insulating layer, wherein (a) a gate electrode portion; and (b) a portion below the gate electrode portion. (C) a source portion formed in contact with one side of the channel portion; and (d) a metal portion or a metal compound formed in the semiconductor layer outside the source portion. (E) a drain portion formed in contact with the other side of the channel portion; and (f) a second portion formed of a metal or a metal compound and formed in a semiconductor layer outside the drain portion. A source region, from a channel portion side, a first source portion, and a second source portion containing a higher concentration of impurities than the first source portion.
A drain portion, a first drain portion from a channel portion side,
And a second drain portion containing an impurity at a higher concentration than the first drain portion, wherein the insulating layer is made of a material that does not react with a metal element forming the first and second conductive regions. Characteristic transistor element. 2. The transistor element according to claim 1, wherein the insulating layer is made of silicon nitride or silicon oxynitride. 3. The transistor device according to claim 2, wherein the metal compound comprises a silicide. 4. The transistor device according to claim 3, wherein the silicide is mainly composed of cobalt silicide. 5. The transistor device according to claim 1, wherein the metal is tungsten. 6. A first gate sidewall made of an insulating material is formed on a side wall of the gate electrode portion and above each of the first source portion and the first drain portion. The transistor element according to claim 1, wherein a second gate sidewall made of an insulating material is formed above each of the source section and the second drain section. 7. A semiconductor device having a structure in which a first semiconductor substrate and a second semiconductor substrate are bonded to each other, wherein a semiconductor layer is formed of the first semiconductor substrate, and an insulating layer is bonded to the second semiconductor substrate. 2. The transistor element according to claim 1, wherein the transistor element is provided on the first semiconductor substrate near the mating portion. 8. The semiconductor device according to claim 1, wherein the insulating layer is formed by ion-implanting an impurity into a semiconductor substrate, and a portion of the semiconductor substrate above the insulating layer corresponds to the semiconductor layer. The transistor element as described in the above. 9. A method for manufacturing a transistor element in which a gate electrode portion, a channel portion, a source portion, and a drain portion are formed in a semiconductor layer formed on an insulating layer, wherein (a) one side of the semiconductor layer (B) forming a gate electrode portion on the other surface of the semiconductor layer; (c) forming a source portion and a drain portion in the semiconductor layer;
Forming a channel portion in the semiconductor layer below the gate electrode portion; and (d) forming a first conductive region made of a metal or a metal compound in the semiconductor layer outside the source portion; Forming a second conductive region made of a metal or a metal compound in the semiconductor layer outside the portion. The step (c) includes: (c-1) the semiconductor layer contains impurities by ion implantation. Forming a first source portion and a first drain portion, and (c-2) forming a first portion made of an insulating material on a side wall of the gate electrode portion.
(C-3) a second source portion containing a higher concentration of impurities than the first source portion and the first drain portion by ion implantation in the semiconductor layer. And (c-4) a step of forming a second gate sidewall on the side surface of the first gate sidewall. A method for manufacturing a transistor element, which is selected from materials which do not react with a metal element forming the first and second conductive regions. 10. The method according to claim 9, wherein the insulating layer is made of silicon nitride or silicon oxynitride. 11. The step (d) includes forming a metal layer made of an element reacting with an element constituting the semiconductor layer on at least the other surface of the semiconductor layer outside the source portion and the semiconductor layer outside the drain portion. After the deposition, a heat treatment is performed to cause an element forming the metal layer to react with an element forming the semiconductor layer, thereby forming the first conductive region and the second conductive region made of a metal compound.
10. The method for manufacturing a transistor element according to claim 9, comprising the step of forming the conductive region of (1). 12. The metal layer is made of a transition metal or a noble metal. In the step (d), (A) the element constituting the semiconductor layer and the transition metal or the noble metal constituting the metal layer react with each other, and At a temperature at which the oxide composed of the element constituting the layer and the transition metal or the noble metal constituting the metal layer do not react, a first heat treatment for reacting the element constituting the metal layer with the element constituting the semiconductor layer is performed. (B) removing the unreacted metal layer, and (C) performing a second heat treatment in order to further react the element constituting the metal layer with the element constituting the semiconductor layer. The method for manufacturing a transistor element according to claim 11. 13. The method according to claim 12, wherein the metal compound comprises silicide. 14. The method according to claim 13, wherein the metal layer is mainly made of cobalt, and the silicide is mainly made of cobalt silicide. 15. The step (d) is performed by a CVD method.
At least replacing the semiconductor layer in the region outside the source portion and the semiconductor layer in the region outside the drain portion with a metal layer,
10. The method for manufacturing a transistor element according to claim 9, comprising a step of forming a first conductive region and a second conductive region made of a metal. 16. A semiconductor device having a structure in which a first semiconductor substrate and a second semiconductor substrate are bonded to each other, wherein the semiconductor layer is formed of the first semiconductor substrate, and the insulating layer is bonded to the second semiconductor substrate. The method for manufacturing a transistor element according to claim 9, wherein the method is provided on the first semiconductor substrate in the vicinity of the joining portion. 17. A semiconductor layer is formed between the steps (c-2) and (c-3) at least on the other surface of the semiconductor layer outside the source portion and the semiconductor layer outside the drain portion. After depositing a metal layer consisting of elements that react with the elements,
Heat treatment is performed to cause an element forming the metal layer to react with an element forming the semiconductor layer, so that the first conductive region and the second conductive region made of a metal compound are partially formed in the thickness direction of the semiconductor layer. The method for manufacturing a transistor element according to claim 9, further comprising a step of forming the transistor element. 18. A method for manufacturing a transistor element in which a gate electrode portion, a channel portion, a source portion, and a drain portion are formed in a semiconductor layer formed on an insulating layer, wherein (a) a semiconductor in which a source portion is to be formed. A first conductive region made of a metal or a metal compound is formed in a region outside the region of the layer, and a second conductive region made of the metal or the metal compound is formed in a region outside the region of the semiconductor layer where the drain portion is to be formed.
(B) forming an insulating layer on one surface of the semiconductor layer; and (c) forming a gate electrode portion on the other surface of the semiconductor layer. (D) forming a source portion and a drain portion in the semiconductor layer;
Forming a channel portion in the semiconductor layer below the gate electrode portion; and (d) the first source portion containing impurities in the semiconductor layer by an ion implantation method. And (d-2) forming a first drain portion made of an insulating material on a side wall of the gate electrode portion.
(D-3) a second source portion containing a higher concentration of impurities than the first source portion and the first drain portion in the semiconductor layer by ion implantation. And forming a second drain portion, wherein the material forming the insulating layer is selected from materials that do not react with metal elements forming the first and second conductive regions. Method of manufacturing. 19. The method according to claim 18, wherein the insulating layer is made of silicon nitride or silicon oxynitride. 20. The method according to claim 11, wherein the step (a) includes the step of forming, on one surface of the semiconductor layer in a region outside the region of the semiconductor layer where the source portion and the drain portion are to be formed, an element reacting with an element constituting the semiconductor layer. After the formation of the metal layer formed, a heat treatment is performed to cause an element forming the metal layer to react with an element forming the semiconductor layer, so that the first conductive region and the second conductive region made of a metal compound are formed. The method for manufacturing a transistor element according to claim 19, comprising a step of forming. 21. The metal layer is made of a transition metal or a noble metal. In the step (A), (A) the element constituting the semiconductor layer reacts with the transition metal or the noble metal constituting the metal layer, and At a temperature at which the oxide composed of the element constituting the layer and the transition metal or the noble metal constituting the metal layer do not react, a first heat treatment for reacting the element constituting the metal layer with the element constituting the semiconductor layer is performed. (B) removing the unreacted metal layer, and (C) performing a second heat treatment in order to further react the element constituting the metal layer with the element constituting the semiconductor layer. The method for manufacturing a transistor element according to claim 20. 22. The method according to claim 20, wherein the metal compound comprises silicide. 23. The method according to claim 22, wherein the metal layer is mainly made of cobalt, and the silicide is mainly made of cobalt silicide. 24. The step (a) is performed by a CVD method.
Forming a first conductive region and a second conductive region made of metal by replacing the semiconductor layer in a region outside the region of the semiconductor layer in which the source portion and the drain portion are to be formed with a metal layer. The method for manufacturing a transistor element according to claim 18, wherein: 25. A semiconductor device having a structure in which a first semiconductor substrate and a second semiconductor substrate are bonded to each other, wherein a semiconductor layer is formed of the first semiconductor substrate, and an insulating layer is bonded to the second semiconductor substrate. 19. The method for manufacturing a transistor element according to claim 18, wherein the method is provided on the first semiconductor substrate in the vicinity of the joining portion. 26. A method for manufacturing a transistor element in which a gate electrode portion, a channel portion, a source portion, and a drain portion are formed in a semiconductor layer formed on an insulating layer, wherein (a) impurities are contained in the semiconductor substrate. Forming an insulating layer by ion implantation, thereby obtaining a semiconductor layer on a portion of the semiconductor substrate above the insulating layer; (b) forming a gate electrode portion on the semiconductor layer; (C) forming a source portion and a drain portion in the semiconductor layer;
Forming a channel portion in the semiconductor layer below the gate electrode portion; and (d) forming a first conductive region made of a metal or a metal compound in the semiconductor layer outside the source portion; Forming a second conductive region made of a metal or a metal compound in the semiconductor layer outside the portion. The step (c) includes: (c-1) the semiconductor layer contains impurities by ion implantation. Forming a first source portion and a first drain portion, and (c-2) forming a first portion made of an insulating material on a side wall of the gate electrode portion.
(C-3) a second source portion containing a higher concentration of impurities than the first source portion and the first drain portion by ion implantation in the semiconductor layer. And (c-4) a step of forming a second gate sidewall on a side surface of the first gate sidewall. The insulating layer formed by ion implantation is , A method of manufacturing a transistor element, comprising a material that does not react with a metal element forming the first and second conductive regions. 27. The method according to claim 26, wherein the insulating layer is made of silicon nitride or silicon oxynitride. 28. Prior to the step (a), a second insulating layer is formed inside the semiconductor substrate by an ion implantation method. In the step (a), an insulating layer is formed on the second insulating layer. The method for manufacturing a transistor element according to claim 26, wherein: 29. In the step (d), a metal layer made of an element reacting with an element constituting the semiconductor layer is deposited on at least the semiconductor layer outside the source portion and the semiconductor layer outside the drain portion. Heat treatment is performed to cause the element constituting the metal layer and the element constituting the semiconductor layer to react with each other,
27. The method according to claim 26, comprising forming a first conductive region and a second conductive region made of a metal compound. 30. The metal layer is made of a transition metal or a noble metal, and in the step (d), (A) the element constituting the semiconductor layer reacts with the transition metal or the noble metal constituting the metal layer, and At a temperature at which the oxide composed of the element constituting the layer and the transition metal or the noble metal constituting the metal layer do not react, a first heat treatment for reacting the element constituting the metal layer with the element constituting the semiconductor layer is performed. (B) removing the unreacted metal layer, and (C) performing a second heat treatment in order to further react the element constituting the metal layer with the element constituting the semiconductor layer. A method for manufacturing a transistor element according to claim 29. 31. The method according to claim 30, wherein the metal compound comprises a silicide. 32. The method according to claim 31, wherein the metal layer is mainly composed of cobalt, and the silicide is mainly composed of cobalt silicide. 33. The step (d) is performed by a CVD method.
At least replacing the semiconductor layer in the region outside the source portion and the semiconductor layer in the region outside the drain portion with a metal layer,
27. The method according to claim 26, further comprising the step of forming a first conductive region and a second conductive region made of a metal. 34. Between the steps (c-2) and (c-3), a semiconductor layer is formed on at least the other surface of the semiconductor layer outside the source portion and the semiconductor layer outside the drain portion. After depositing a metal layer consisting of elements that react with the elements,
Heat treatment is performed to cause an element forming the metal layer to react with an element forming the semiconductor layer, so that the first conductive region and the second conductive region made of a metal compound are partially formed in the thickness direction of the semiconductor layer. 27. The method for manufacturing a transistor element according to claim 26, further comprising a step of forming the transistor element.