JPH1065092A - Substrate for multi-chip module and its manufacturing method - Google Patents

Substrate for multi-chip module and its manufacturing method

Info

Publication number
JPH1065092A
JPH1065092A JP21897196A JP21897196A JPH1065092A JP H1065092 A JPH1065092 A JP H1065092A JP 21897196 A JP21897196 A JP 21897196A JP 21897196 A JP21897196 A JP 21897196A JP H1065092 A JPH1065092 A JP H1065092A
Authority
JP
Japan
Prior art keywords
substrate
dielectric substrates
substrates
firing
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21897196A
Other languages
Japanese (ja)
Other versions
JP2871613B2 (en
Inventor
Makoto Akaishi
誠 赤石
Tomoya Kaneko
友哉 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21897196A priority Critical patent/JP2871613B2/en
Publication of JPH1065092A publication Critical patent/JPH1065092A/en
Application granted granted Critical
Publication of JP2871613B2 publication Critical patent/JP2871613B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Abstract

PROBLEM TO BE SOLVED: To obtain a pattern width precision that can be used fully even if the pattern width precision is millimeter wave band and at the same time achieve a low-loss circuit. SOLUTION: Holes 8a and 8b for via holes are drilled to alumina substrates 2-1 and 2-2 individually one by one at the stage of a green sheet, a required machining such as filling of such conductive material as tungsten is made to the holes, and then the alumina substrates are baked simultaneously at a baking temperature exceeding 1,300 deg.C. Thin-film strip lines 5 and 6 are formed on the conductor surfaces of the baked alumina substrates 2-1 and 2-2 by the thin- film conductor forming technology. A non-baked low-temperature baking glass substrate 3 that is subjected to the machining of the via hole for connecting the thin-film strip lines 5 and 6 is pinched between the alumina substrates 2-1 and 2-2, thus performing low-temperature baking.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はマルチチップモジュ
ール用基板及びその製造方法に関し、特にマイクロ波通
信装置用のマイクロ波集積回路に用いられる多層基板に
おけるマルチチップモジュールの構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for a multichip module and a method for manufacturing the same, and more particularly to a structure of a multichip module in a multilayer substrate used for a microwave integrated circuit for a microwave communication device.

【0002】[0002]

【従来の技術】従来、この種のマルチチップモジュール
においては、図4に示すように、少なくとも2層以上の
多層誘電体基板と3層以上の導体層とを有し、内層にマ
イクロ波信号を伝送するストリップラインを有してい
る。
2. Description of the Related Art Conventionally, as shown in FIG. 4, a multi-chip module of this type has at least two or more multilayer dielectric substrates and three or more conductor layers, and transmits a microwave signal to an inner layer. It has a stripline for transmission.

【0003】図4において、20はマルチチップモジュ
ールのヒートシンク兼キャリア(金属製)、21は内層
キャパシタ、22は放熱用バイアホール、23は内層抵
抗、24は半導体チップ、25は高周波シールド用のバ
イアホール、26は半導体チップ24を実装しているキ
ャビティの気密封止用のキャップ、27は厚膜印刷によ
り形成されたマイクロストリップラインである。
In FIG. 4, reference numeral 20 denotes a heat sink and carrier (made of metal) of a multi-chip module, 21 denotes an inner layer capacitor, 22 denotes a heat dissipation via hole, 23 denotes an inner layer resistor, 24 denotes a semiconductor chip, and 25 denotes a high frequency shield via. A hole 26 is a cap for hermetically sealing a cavity in which the semiconductor chip 24 is mounted, and 27 is a microstrip line formed by thick film printing.

【0004】半導体チップ24を実装する部位はストリ
ップラインを有する層の上層の誘電体に空孔を有するキ
ャビティ構造となっている。このキャビティ内では上記
のストリップラインがマイクロストリップライン27と
なっている。また、キャビティ内にロウ付けまたは接着
剤等で固定された半導体チップ24とマイクロストリッ
プライン27とはワイヤボンディングによって接続され
ている。
[0004] The portion on which the semiconductor chip 24 is mounted has a cavity structure having holes in a dielectric layer above a layer having a strip line. In this cavity, the above-mentioned strip line is a microstrip line 27. Further, the semiconductor chip 24 fixed in the cavity by brazing or an adhesive or the like and the microstrip line 27 are connected by wire bonding.

【0005】このマルチチップモジュール用の多層基板
は厚膜印刷によって電極が印刷された焼成前のグリーン
シートを積層し、これら積層されたグリーンシートを同
時焼成(Co.Fire)することで製造されている。
[0005] The multi-layer substrate for a multi-chip module is manufactured by laminating unfired green sheets on which electrodes are printed by thick-film printing, and simultaneously firing (Co. Fire) these laminated green sheets. I have.

【0006】[0006]

【発明が解決しようとする課題】上述した従来のマルチ
チップモジュールでは、マイクロ波を伝送するストリッ
プライン、マイクロストリップラインが厚膜印刷によっ
て内層に電極形成されているため、パタン幅で±50μ
m〜±100μm程度の精度しか得られない。この程度
の精度ではミリ波にとって不十分である。
In the above-mentioned conventional multi-chip module, since the strip lines for transmitting microwaves and the microstrip lines are formed on the inner layer by thick film printing, the pattern width is ± 50 μm.
An accuracy of only about m to ± 100 μm can be obtained. This level of accuracy is insufficient for millimeter waves.

【0007】また、グリーンシートを同時焼成する時の
焼成温度が1300℃以上の高温の場合、導体パターン
の材料をタングステンとしなければならない。しかしな
がら、タングステンは金や銀、あるいは銅と比べると電
気抵抗が約3倍大きいので、伝送される信号の損失が大
きい。
Further, when the firing temperature at the time of simultaneous firing of the green sheets is as high as 1300 ° C. or more, the material of the conductor pattern must be tungsten. However, tungsten has an electrical resistance that is about three times greater than that of gold, silver or copper, so that the loss of a transmitted signal is large.

【0008】そこで、本発明の目的は上記の問題点を解
消し、パタン幅の精度がミリ波帯でも十分使用可能なパ
タン幅の精度を得ることができ、低損失な回路を実現す
ることができるマルチチップモジュール用基板及びその
製造方法を提供することにある。
Accordingly, an object of the present invention is to solve the above-mentioned problems, to obtain a pattern width with a pattern width accuracy that can be sufficiently used even in a millimeter wave band, and to realize a low-loss circuit. It is an object of the present invention to provide a multi-chip module substrate and a method of manufacturing the same.

【0009】[0009]

【課題を解決するための手段】本発明によるマルチチッ
プモジュール用基板は、各々グリーンシート段階でバイ
アホールの穴明け及び導体ペーストの充填が行われた後
に独立に高温焼成されてからバイアホールの形成及び導
体面上への薄膜導体の形成が行われる第1及び第2の誘
電体基板と、前記第1及び第2の誘電体基板各々の間に
積層されかつ少なくとも前記第1及び第2の誘電体基板
各々の前記薄膜導体間を接続するバイアホールを含むガ
ラスセラミックス層とを備え、前記第1及び第2の誘電
体基板各々と前記ガラスセラミックス層とを積層した後
にこれらを低温焼成している。
The substrate for a multi-chip module according to the present invention is formed by forming via holes in a green sheet stage and then independently firing at a high temperature after filling with a conductive paste. And a first and second dielectric substrate on which a thin-film conductor is formed on a conductive surface, and laminated between each of the first and second dielectric substrates and at least the first and second dielectric substrates. A glass ceramic layer including via holes connecting the thin film conductors of each of the body substrates, and laminating each of the first and second dielectric substrates and the glass ceramic layer and then firing them at a low temperature. .

【0010】本発明によるマルチチップモジュール用基
板の製造方法は、高温焼成される第1及び第2の誘電体
基板各々をグリーンシート段階でバイアホールの穴明け
及び導体ペーストの充填を行う第1の工程と、前記第1
及び第2の誘電体基板各々を独立に高温焼成する第2の
工程と、前記第1及び第2の誘電体基板各々の導体面上
に薄膜導体形成技術により電極導体を形成する第3の工
程と、前記第1及び第2の誘電体基板各々の間に積層さ
れかつ少なくとも前記第1及び第2の誘電体基板各々の
前記電極導体間を接続するバイアホールを含むガラスセ
ラミックス層を前記第1及び第2の誘電体基板各々の間
に積層する第4の工程と、前記第1及び第2の誘電体基
板各々と前記ガラスセラミックス層とを低温焼成する第
5の工程とを備えている。
In the method of manufacturing a substrate for a multichip module according to the present invention, the first and second dielectric substrates fired at a high temperature are each filled with a conductive paste at the green sheet stage. The step and the first
And a second step of independently baking the second dielectric substrate at a high temperature, and a third step of forming an electrode conductor on the conductor surface of each of the first and second dielectric substrates by a thin-film conductor formation technique A glass ceramic layer laminated between each of the first and second dielectric substrates and including a via hole connecting at least the electrode conductors of each of the first and second dielectric substrates. A fourth step of laminating between the first and second dielectric substrates, and a fifth step of firing each of the first and second dielectric substrates and the glass ceramic layer at a low temperature.

【0011】上記のように、アルミナや窒化アルミ等の
1300℃以上の焼成温度で高温焼成されたn枚(nは
2以上の正の整数)の誘電体基板各々に薄膜導体形成技
術によって導体パターンを形成した後に、それらの間に
焼成していないガラスセラミックス層を挟んで積層して
から低温焼成する。
As described above, each of n (n is a positive integer of 2 or more) dielectric substrates, such as alumina or aluminum nitride, which has been fired at a firing temperature of 1300 ° C. or more at a high temperature, has a conductor pattern formed by a thin film conductor forming technique. Are formed, a non-fired glass ceramic layer is sandwiched between them, and then laminated at low temperature.

【0012】これによって、誘電体基板の導体面がすべ
て薄膜導体形成技術を用いて形成されるので、パターン
幅で±5μmの精度が得られ、ミリ波帯でも使用可能な
精度が得られる。また、誘電体基板間にガラスセラミッ
クス層を挟んで低温焼成しているので、誘電体基板の導
体面の導体材料として金等を使用することができるの
で、低損失な回路を実現することができる。
Thus, since the entire conductor surface of the dielectric substrate is formed using the thin-film conductor formation technique, an accuracy of ± 5 μm in pattern width is obtained, and an accuracy usable in a millimeter wave band is obtained. In addition, since low-temperature baking is performed with the glass ceramic layer interposed between the dielectric substrates, gold or the like can be used as a conductive material of the conductive surface of the dielectric substrate, so that a low-loss circuit can be realized. .

【0013】[0013]

【発明の実施の形態】次に、本発明の実施例について図
面を参照して説明する。図1は本発明の一実施例の断面
図である。図において、1は金属製のキャリア、2はア
ルミナ基板、3は低温焼成ガラス基板、4は薄膜マイク
ロストリップ線、5,6は薄膜ストリップ線路、7は薄
膜マイクロストリップ線路4に金ワイヤで接続された半
導体ベアチップ、8はバイアホール、9は気密封止用の
金属製のキャップ、10は薄膜の接地用導体、11は半
導体ベアチップ7と薄膜マイクロストリップ線路4とを
ワイヤボンディングするための金ワイヤである。
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of one embodiment of the present invention. In the figure, 1 is a metal carrier, 2 is an alumina substrate, 3 is a low-temperature fired glass substrate, 4 is a thin film microstrip line, 5 and 6 are thin film strip lines, and 7 is connected to the thin film microstrip line 4 by gold wires. Semiconductor bare chip, 8 is a via hole, 9 is a metal cap for hermetic sealing, 10 is a thin film grounding conductor, 11 is a gold wire for wire bonding the semiconductor bare chip 7 and the thin film microstrip line 4. is there.

【0014】図2(a)〜(c)は本発明の一実施例に
よるマルチチップモジュール用基板の製造工程を示す断
面図である。これら図1及び図2を用いて本発明の一実
施例によるマルチチップモジュール用基板の製造工程に
ついて説明する。
FIGS. 2A to 2C are cross-sectional views showing a process for manufacturing a substrate for a multichip module according to an embodiment of the present invention. The manufacturing process of the multi-chip module substrate according to one embodiment of the present invention will be described with reference to FIGS.

【0015】アルミナ基板2−1,2−2は1枚ずつ単
独にグリーンシートの段階でバイアホール用の穴8a,
8b等の穴明けを行い、その穴へのタングステン等の導
体材料の充填等の必要な加工を施した後に、1300℃
以上の焼成温度で同時焼成を行う[図2(a)参照]。
The alumina substrates 2-1 and 2-2 are individually used one by one at the stage of green sheet at the holes 8a and 8a for via holes.
8b, etc., and after performing necessary processing such as filling the hole with a conductive material such as tungsten, 1300 ° C.
Simultaneous firing is performed at the above firing temperature (see FIG. 2A).

【0016】焼成されたアルミナ基板2−1,2−2各
々の導体面に対して薄膜導体形成技術によって導体パタ
ーン(薄膜ストリップ線路5,6等)を形成する[図2
(b)参照]。
A conductor pattern (thin film strip lines 5, 6, etc.) is formed on the conductor surfaces of the fired alumina substrates 2-1 and 2-2 by a thin film conductor formation technique [FIG.
(B)].

【0017】その後、必要に応じて、薄膜ストリップ線
路5,6間を接続するバイアホール8の加工を施した未
焼成の低温焼成ガラス基板3をアルミナ基板2−1,2
−2各々の間に挟んで積層してから低温焼成することで
[図2(c)参照]、導体面が4面でかつ誘電体基板が
3層の多層基板が形成される。これによって、多層基板
の内部及び上下に形成する導体パターンはすべて薄膜に
て形成することができる。
Thereafter, if necessary, the unsintered low-temperature fired glass substrate 3 on which the via holes 8 for connecting the thin film strip lines 5 and 6 have been processed is replaced with the alumina substrates 2-1 and 2-2.
-2 and a low-temperature baking (see FIG. 2 (c)) to form a multilayer substrate having four conductive surfaces and three dielectric substrates. Thus, the conductor patterns formed inside and above and below the multilayer substrate can all be formed of thin films.

【0018】図3は本発明の他の実施例の断面図であ
る。図において、本発明の他の実施例は3枚のアルミナ
基板2と2枚の低温焼成ガラス基板3とを積層して構成
した以外は図1に示す本発明の一実施例と同様の構成と
なっており、同一構成用には同一符号を付してある。
FIG. 3 is a sectional view of another embodiment of the present invention. In the drawing, another embodiment of the present invention has the same configuration as the embodiment of the present invention shown in FIG. 1 except that three alumina substrates 2 and two low-temperature fired glass substrates 3 are laminated. The same reference numerals are used for the same components.

【0019】この場合、焼成された3枚のアルミナ基板
2各々の導体面に対して薄膜導体形成技術によって導体
パターンを形成した後に、未焼成の2枚の低温焼成ガラ
ス基板3を3枚のアルミナ基板2各々の間に挟んで積層
してから低温焼成することで、導体面が6面でかつ誘電
体基板が5層の多層基板が形成される。
In this case, after a conductor pattern is formed on the conductor surface of each of the three fired alumina substrates 2 by a thin-film conductor formation technique, the two unfired low-temperature fired glass substrates 3 are combined with the three alumina substrates. By laminating between each of the substrates 2 and firing at a low temperature, a multilayer substrate having six conductive surfaces and five dielectric substrates is formed.

【0020】すなわち、n枚のアルミナ基板2各々の導
体面に対して薄膜導体形成技術によって導体パターンを
形成した後に、未焼成の(n−1)枚の低温焼成ガラス
基板3をアルミナ基板2各々の間に挟んで積層してから
低温焼成することで、導体面が2n面でかつ誘電体基板
が2n−1層の多層基板が形成される。
That is, after a conductor pattern is formed on the conductor surface of each of the n alumina substrates 2 by the thin film conductor formation technique, the unfired (n-1) low-temperature fired glass substrates 3 are removed from each of the alumina substrates 2. By sintering at a low temperature after laminating between them, a multilayer substrate having a 2n-1 conductor substrate and 2n-1 dielectric substrates is formed.

【0021】このように、高温焼成されるアルミナ基板
2各々をグリーンシート段階でバイアホール8の穴明け
及び導体ペーストの充填を行う工程と、アルミナ基板2
各々を独立に高温焼成する工程と、アルミナ基板2各々
の導体面上に薄膜導体形成技術によりストリップ線路
5,6を形成する工程と、アルミナ基板2各々の間に積
層されかつ少なくともアルミナ基板2各々のストリップ
線路5,6間を接続するバイアホール8を含む低温焼成
ガラス基板3をアルミナ基板2各々の間に積層する工程
と、アルミナ基板2各々と低温焼成ガラス基板3とを低
温焼成する工程とを経て多層基板を製造することによっ
て、アルミナ基板2の導体パターンがすべて薄膜導体形
成技術を用いて形成されるので、パターン幅で±5μm
の精度が得られ、ミリ波帯でも使用可能な精度が得られ
る。
In this way, the steps of drilling the via holes 8 and filling the conductive paste in the green sheet stage for each of the alumina substrates 2 fired at a high temperature,
A step of independently sintering each of them at a high temperature, a step of forming strip lines 5 and 6 on a conductor surface of each of the alumina substrates 2 by a thin film conductor forming technique, and a step of laminating between the alumina substrates 2 and at least each of the alumina substrates 2 Laminating a low-temperature fired glass substrate 3 including via holes 8 connecting the strip lines 5 and 6 between the alumina substrates 2, and firing the low-temperature fired glass substrate 3 and the alumina substrate 2 each at a low temperature. By manufacturing the multilayer substrate through the above, since all the conductor patterns of the alumina substrate 2 are formed using the thin-film conductor formation technology, the pattern width is ± 5 μm.
And an accuracy that can be used even in the millimeter-wave band.

【0022】また、アルミナ基板2間に低温焼成ガラス
基板3を挟んで低温焼成しているので、アルミナ基板2
の導体パターンの導体材料として金や銀、あるいは銅等
の比抵抗の小さい材料を使用することができ、高温同時
焼成の場合の導体材料であるタングステンに比べて低損
失な回路を実現することができる。
Since the low-temperature firing glass substrate 3 is sandwiched between the alumina substrates 2, the low-temperature firing is performed.
A material with low specific resistance, such as gold, silver, or copper, can be used as the conductor material of the conductor pattern, and a circuit with lower loss than tungsten, which is a conductor material in the case of simultaneous firing at high temperatures, can be realized. it can.

【0023】尚、上述した本発明の一実施例及び他の実
施例では誘電体基板としてアルミナ基板2を用いた場合
について説明したが、1300℃以上の焼成温度で高温
焼成される窒化アルミ等の誘電体基板を用いる場合にも
本発明の一実施例及び他の実施例を適用することができ
るのは明白である。
In the above-described embodiment and other embodiments of the present invention, the case where the alumina substrate 2 is used as the dielectric substrate has been described. However, aluminum nitride or the like fired at a high temperature of 1300 ° C. or more is used. It is obvious that the embodiment of the present invention and other embodiments can be applied to the case where a dielectric substrate is used.

【0024】[0024]

【発明の効果】以上説明したように本発明によれば、高
温焼成される第1及び第2の誘電体基板各々をグリーン
シート段階でバイアホールの穴明け及び導体ペーストの
充填を行う工程と、第1及び第2の誘電体基板各々を独
立に高温焼成する工程と、第1及び第2の誘電体基板各
々の導体面上に薄膜導体形成技術により電極導体を形成
する工程と、第1及び第2の誘電体基板各々の間に積層
されかつ少なくとも第1及び第2の誘電体基板各々の電
極導体間を接続するバイアホールを含むガラスセラミッ
クス層を第1及び第2の誘電体基板各々の間に積層する
工程と、第1及び第2の誘電体基板各々とガラスセラミ
ックス層とを低温焼成する工程とを経て多層基板を製造
することによって、パタン幅の精度がミリ波帯でも十分
使用可能なパタン幅の精度を得ることができ、低損失な
回路を実現することができるという効果がある。
As described above, according to the present invention, the first and second dielectric substrates to be fired at a high temperature are each subjected to the step of forming via holes and filling the conductive paste in the green sheet stage; Independently baking the first and second dielectric substrates at a high temperature, forming electrode conductors on the conductor surfaces of the first and second dielectric substrates by a thin-film conductor forming technique, A glass ceramic layer laminated between each of the second dielectric substrates and including a via hole connecting at least the electrode conductors of each of the first and second dielectric substrates is formed on each of the first and second dielectric substrates. By manufacturing a multi-layer substrate through a process of laminating between them and a process of firing each of the first and second dielectric substrates and the glass ceramic layer at a low temperature, the pattern width accuracy can be sufficiently used even in the millimeter wave band. Na pattern Can be obtained accuracy, there is an effect that it is possible to realize a low-loss circuit.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of the present invention.

【図2】(a)〜(c)は本発明の一実施例によるマル
チチップモジュール用基板の製造工程を示す断面図であ
る。
FIGS. 2A to 2C are cross-sectional views illustrating a process for manufacturing a multi-chip module substrate according to an embodiment of the present invention.

【図3】本発明の一実施例の断面図である。FIG. 3 is a sectional view of one embodiment of the present invention.

【図4】従来例の断面図である。FIG. 4 is a sectional view of a conventional example.

【符号の説明】[Explanation of symbols]

1 金属製のキャリア 2 アルミナ基板 3 低温焼成ガラス基板 4 薄膜マイクロストリップ線 5,6 薄膜ストリップ線路 7 半導体ベアチップ 8 バイアホール 9 気密封止用の金属製のキャップ 10 薄膜の接地用導体 11 金ワイヤ DESCRIPTION OF SYMBOLS 1 Metal carrier 2 Alumina substrate 3 Low temperature firing glass substrate 4 Thin film microstrip line 5, 6 Thin film strip line 7 Semiconductor bare chip 8 Via hole 9 Metal cap for hermetic sealing 10 Thin film grounding conductor 11 Gold wire

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 各々グリーンシート段階でバイアホール
の穴明け及び導体ペーストの充填が行われた後に独立に
高温焼成されてからバイアホールの形成及び導体面上へ
の薄膜導体の形成が行われる第1及び第2の誘電体基板
と、前記第1及び第2の誘電体基板各々の間に積層され
かつ少なくとも前記第1及び第2の誘電体基板各々の前
記薄膜導体間を接続するバイアホールを含むガラスセラ
ミックス層とを有し、前記第1及び第2の誘電体基板各
々と前記ガラスセラミックス層とを積層した後にこれら
を低温焼成したことを特徴とするマルチチップモジュー
ル用基板。
1. A method of forming via holes and forming a thin film conductor on a conductor surface after independently performing high-temperature firing after forming via holes and filling a conductive paste in each green sheet stage. A first and a second dielectric substrate, and a via hole laminated between the first and the second dielectric substrates and connecting at least the thin film conductors of the first and the second dielectric substrates, respectively. A substrate for a multi-chip module, comprising: a glass ceramic layer containing the first and second dielectric substrates; and laminating each of the first and second dielectric substrates and the glass ceramic layer and then firing them at a low temperature.
【請求項2】 前記第1及び第2の誘電体基板各々は、
1300℃以上の焼成温度で焼成されることを特徴とす
る請求項1記載のマルチチップモジュール用基板。
2. The first and second dielectric substrates, respectively,
The multi-chip module substrate according to claim 1, wherein the substrate is fired at a firing temperature of 1300 ° C or higher.
【請求項3】 前記第1及び第2の誘電体基板各々は、
少なくともアルミナ及び窒化アルミのいずれかであるこ
とを特徴とする請求項1または請求項2記載のマルチチ
ップモジュール用基板。
3. The first and second dielectric substrates, respectively,
3. The multi-chip module substrate according to claim 1, wherein the substrate is at least one of alumina and aluminum nitride.
【請求項4】 n枚(nは3以上の正の整数)の前記誘
電体基板と(n−1)枚の前記ガラスセラミックス層と
からなることを特徴とする請求項1から請求項3のいず
れか記載のマルチチップモジュール用基板。
4. The semiconductor device according to claim 1, comprising n (n is a positive integer of 3 or more) dielectric substrates and (n-1) glass ceramic layers. The substrate for a multichip module according to any one of the above.
【請求項5】 高温焼成される第1及び第2の誘電体基
板各々をグリーンシート段階でバイアホールの穴明け及
び導体ペーストの充填を行う第1の工程と、前記第1及
び第2の誘電体基板各々を独立に高温焼成する第2の工
程と、前記第1及び第2の誘電体基板各々の導体面上に
薄膜導体形成技術により電極導体を形成する第3の工程
と、前記第1及び第2の誘電体基板各々の間に積層され
かつ少なくとも前記第1及び第2の誘電体基板各々の前
記電極導体間を接続するバイアホールを含むガラスセラ
ミックス層を前記第1及び第2の誘電体基板各々の間に
積層する第4の工程と、前記第1及び第2の誘電体基板
各々と前記ガラスセラミックス層とを低温焼成する第5
の工程とを有することを特徴とするマルチチップモジュ
ール用基板の製造方法。
5. A first step of forming a via hole and filling a conductive paste in each of the first and second dielectric substrates fired at a high temperature in a green sheet stage, and the first and second dielectric substrates. A second step of independently firing each of the body substrates at a high temperature, a third step of forming electrode conductors on a conductor surface of each of the first and second dielectric substrates by a thin-film conductor formation technique, A glass ceramic layer laminated between each of the first and second dielectric substrates and including a via hole connecting at least the electrode conductors of the first and second dielectric substrates. A fourth step of laminating between the body substrates, and a fifth step of firing each of the first and second dielectric substrates and the glass ceramic layer at a low temperature.
And a method for manufacturing a substrate for a multichip module.
【請求項6】 前記第1及び第2の誘電体基板各々は、
1300℃以上の焼成温度で焼成されることを特徴とす
る請求項5記載のマルチチップモジュール用基板の製造
方法。
6. The first and second dielectric substrates, respectively,
The method according to claim 5, wherein the substrate is fired at a firing temperature of 1300 ° C or higher.
【請求項7】 前記第1及び第2の誘電体基板各々は、
少なくともアルミナ及び窒化アルミのいずれかであるこ
とを特徴とする請求項5または請求項6記載のマルチチ
ップモジュール用基板の製造方法。
7. The first and second dielectric substrates, respectively,
The method for manufacturing a substrate for a multichip module according to claim 5, wherein the substrate is at least one of alumina and aluminum nitride.
【請求項8】 n枚(nは3以上の正の整数)の前記誘
電体基板と(n−1)枚の前記ガラスセラミックス層と
からなることを特徴とする請求項5から請求項7のいず
れか記載のマルチチップモジュール用基板。
8. The semiconductor device according to claim 5, comprising n (n is a positive integer of 3 or more) dielectric substrates and (n-1) glass ceramic layers. The substrate for a multichip module according to any one of the above.
JP21897196A 1996-08-21 1996-08-21 Multi-chip module substrate and method of manufacturing the same Expired - Fee Related JP2871613B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21897196A JP2871613B2 (en) 1996-08-21 1996-08-21 Multi-chip module substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21897196A JP2871613B2 (en) 1996-08-21 1996-08-21 Multi-chip module substrate and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH1065092A true JPH1065092A (en) 1998-03-06
JP2871613B2 JP2871613B2 (en) 1999-03-17

Family

ID=16728237

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2871613B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306071A (en) * 2007-06-08 2008-12-18 Nec Corp Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306071A (en) * 2007-06-08 2008-12-18 Nec Corp Semiconductor device and method for manufacturing the same
US8975150B2 (en) 2007-06-08 2015-03-10 Renesas Electronics Corporation Semiconductor device manufacturing method

Also Published As

Publication number Publication date
JP2871613B2 (en) 1999-03-17

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