JPH1063483A - Data arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data arithmetic device which can fast make data alignment and unnecessitates to independently provide memory that holds data in the middle of calculation. SOLUTION: When data is successively supplied as an input IN10, a comparator 101 compares supplied data with data which is held in a register 103, defines a compared result as 1 when the supplied data is larger, and defines a compared result as 0 when the supplied data is smaller. A selector 102 supplies data that is supplied as an input IN20 or data that is supplied as an input IN22 (which is held by the register 103) to the register 103 when the compared result that is supplied as a control signal (IN24) is 1 or 0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data operation circuit used in a digital signal processor or a similar large-scale integrated circuit and performing operations such as data comparison and alignment.

[0002]

2. Description of the Related Art Generally, in a digital signal processor (hereinafter referred to as a DSP) or a similar large-scale integrated circuit (hereinafter referred to as an LSI), etc. (Less than,
As a method of selecting data of maximum m data) and obtaining data in which the maximum data m is sorted in descending order (hereinafter, referred to as maximum sorted data), for example, a document “Encyclopedia of Latest Algorithms in C Language” by Okumura (Technical Review Company) , The 153rd
The algorithm referred to as selection sorting described in item (1) is used.

The following processing is required to obtain the maximum number m of aligned data from the _N data d ₀ , d ₁ ,..., D _{N -1} by such selective sorting.

First, data is selected one by one from N data, the sequentially selected data is compared with the largest data so far to find the largest data, and the largest data is extracted. Store in storage device.

Next, data is selected one by one from the remaining N-1 data in the same manner as described above, and the sequentially selected data is compared with the largest data so far to obtain the largest data. , And the maximum data is extracted and stored in the storage device.

Thereafter, the extraction of the largest data from the remaining data is repeated until m pieces of data are stored in the storage device. By this, the upper m in N data
Pieces of data are extracted and stored in the storage device.

FIG. 2 is a block diagram showing a configuration example of a main part of an arithmetic circuit for implementing the above-described selective sorting in a conventional general DSP or an LSI similar thereto. As shown in the figure, the arithmetic circuit includes a comparator or subtractor 2 for comparing or subtracting two supplied data.
01, a selector 202 for selecting two input data based on the output of the comparator or the subtractor 201, and a register 203 for holding the output of the selector 202.

An output of the register 203 and data from a data operation circuit or a data storage memory (not shown) are supplied to two inputs of the comparator or the subtractor 201, respectively. The comparison result of these two inputs is selected. Vessel 202
Supplied to The selector 202 is also supplied with the output of the register 203 and data from a data operation circuit or a data storage memory (not shown).
And selects the larger one of the two inputs based on the comparison result from. The register 203 holds the data supplied from the selector 202,
The held data is supplied to one input of a comparator or a subtractor 201 and also supplied to a data memory via a bus (not shown). Thereby, the data in the register 203 can be saved or stored in the data memory.

The above-mentioned DSP or LS similar thereto
In I, when an arithmetic circuit as shown in FIG. 2 is used to perform selective sorting for obtaining m maximum alignment data from N data, the following processing is required.

First, N pieces of data are stored in a data memory in advance.

Next, two of the N data are supplied to a comparator or subtractor 201 for comparison, and a larger data is selected by a selector 202 using the comparison result. The selected data is held in the register 203.

One of the remaining N-2 pieces of data is supplied to a comparator or a subtractor 201, and is supplied to a register 2
In comparison with the data held in the data 03, the larger data is selected by the selector 202 and supplied to the register 203.

The above-described processing is repeated for all the remaining data, and after the processing for all the data is completed, the data finally held in the register 203 is the largest among the N data. Data.

Further, the maximum data obtained in the above processing is stored (saved) in the data memory, and the same processing as described above is performed, and the maximum data in the N-1 data excluding the maximum data is processed. Obtain data and store it in data memory.

When the above processing is repeated and the number of data stored in the data memory becomes m, these m data become the maximum alignment data. By performing such processing, N pieces of data can be aligned at the maximum.

[0016]

However, when the maximum alignment data is obtained by the above-described method, the comparison, selection, and holding processes are performed N-1 times to obtain the maximum data from the N data. , And a process of N-1 instruction steps is required in a DSP or LSI capable of comparing, selecting, and holding processing in one instruction step. Similarly, in order to obtain the maximum data among the remaining N-1 data, processing of an N-2 instruction step is required. Therefore,
In order to obtain m maximum alignment data from N data, at least (N−1) + (N−2) +... + (N−m) instruction steps, ie, ｛m × N−m (m + 1) / 2｝ Instruction step processing is required. For this reason, when m becomes large, processing of a large number of instruction steps is required, and there has been a problem that the speed of signal processing is reduced.

In the above-described method, the input N data is used at most m times before the maximum alignment data is obtained. Therefore, it is necessary to store the input N data in the data memory in advance as described above. In addition, since it is necessary to store the remaining data except for the maximum data, there is a problem that a memory for storing these data is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is possible to perform data alignment at high speed, and it is necessary to separately provide a memory for holding data being calculated. It is an object to provide a data processing device that does not have any data.

[0019]

A data operation circuit according to the present invention compares an internal register for holding data with first data supplied from the outside and data held in the internal register, A comparator for outputting a comparison result,
According to the control signal from the outside and the comparison result from the comparator,
A selector that selects any one of the second data supplied from outside, the first data, and the data held in the internal register and supplies the selected data to the internal register.

The comparator sets the comparison result to a first value, for example, 1 when the data supplied from the outside is larger (or smaller) than the data held in the internal register, and the data supplied from the outside is If the data is less than (or greater than) the data held in the internal register, the comparison result is set to a second value, for example, 0. When the comparison result from the comparator is the first value, the selector selects the first value based on the control signal.
And the second data is selected and supplied to the internal register. When the comparison result from the comparator is the second value, the data held in the internal register is determined based on the control signal. Select and supply to internal register.

Also, the data operation circuit according to the present invention compares the internal register for holding data with the first data supplied from the outside and the data held in the internal register, and outputs the comparison result. And selecting one of the second data supplied from the outside, the first data, and the data held in the internal register according to the control signal from the outside and the comparison result from the comparator. And a selector for supplying the selector to the internal register. The outputs of the comparators of the preceding stage are used as control signals for the selector of the next stage. The data held in the internal register of the unit is supplied as a second data to the selector of the operation unit at the next stage and is connected in multiple stages.

Each comparator sets the comparison result to a first value, for example, 1 when the data supplied from the outside is larger (or smaller) than the data held in the internal register.
If the data supplied from the outside is less than (or greater than) the data held in the internal register, the comparison result is set to a second value, for example, 0. When the comparison result from the comparator is the first value, the selector selects one of the first data and the second data based on the control signal and supplies the selected data to the internal register. Is the second value, the data held in the internal register is selected based on the control signal and supplied to the internal register.

[0023]

FIG. 1 is a block diagram showing a configuration of a submodule which is a first embodiment of a data operation circuit according to the present invention. This sub-module comprises a comparator 101 for comparing two inputs, a selector 102, a register 10
3 is provided. In FIG. 1, the power supply to the comparator 101, the selector 102, the register 103, the supply path of the operation clock, and the like are omitted.

The comparator 101 has two data inputs IN1
0, the magnitude of the data supplied to IN11 is compared, and the comparison result is output as 1-bit data. One data input IN10 is supplied with input data from outside the sub-module, and the other data input IN11 is a register 1
03 is supplied. Also,
The comparison result, which is the output of the comparison unit 101,
2 is supplied as one of the control signal inputs (IN24), and is also output outside the submodule.

The selector 102 has three data inputs IN2
0, IN21, IN22 and two control signal inputs IN2
3, IN24. Two of these data inputs (IN20, IN21) are inputs from outside the module, one of which (IN20) is the comparator 101
Is common to the input IN10. Another one data input I
N22 is connected to the output of the register 103. One of the control signal inputs (IN23) is supplied with a 1-bit control signal from outside the submodule, and the other one (IN24) is supplied with the output of the comparator 101 as described above. Have been. The selector 102 selects one of the three input data based on the two control signal inputs IN23 and IN24, and stores the selected data in a register 103.
To supply.

The register 103 holds the data supplied from the selector 102, and stores the held data in the data f input IN22 of the selector 102 and the data input IN of the comparator 101.
11 and supplied outside the submodule.

In the submodule configured as described above, the comparator 101 and the selector 102 operate as follows.

The comparator 101 has two data inputs IN1
Based on 0 and IN11, if IN10> IN11, 1 is output, and if IN10 ≦ IN11, 0 is output.

The selector 102 outputs IN23 = 0 and I based on the two control signal inputs IN23 and IN24.
When N24 = 1, the value of IN20 is selected as the output,
When N23 = 1 and IN24 = 1, the value of IN21 is selected as an output, and when IN23 = 0 and IN24 = 0, the value of IN22 is output.

By sequentially supplying the data in the data series to the data input IN10 of the comparator 101 operating as described above and setting the control signal input IN23 of the selector 102 to the ground potential (0), this sub-module It operates as a maximum value circuit that holds the maximum data in the input data series in the register 103.

That is, the selector 102 sets one control signal input IN23 to the ground potential (0), so that when the control signal input IN24, that is, the output of the comparator 101 is 0, the data input IN22, that is, the register 103
Is supplied to the register 103 again, and when the output of the comparator 101 is 1, the data input I
N20, ie, one of the data series is supplied to the register 103.

The comparator 101 outputs the data (data in the data series) supplied to the data input IN10 as described above.
Is supplied to the data input IN11 (register 1
When the input IN10 is equal to or less than the input IN11, the output is set to 0 when the output is larger than the data held in the input 03).

Therefore, after the register 103 is reset prior to the supply of the above-described data series, if the data in the data series is sequentially supplied, the comparator 101 and the data held in the register 103 are supplied. And the larger data is supplied to the register 103 based on the comparison result. When such an operation is repeated for all data in the data series, the largest data in the data series is held in the register 103.

This sub-module includes a comparator 10
1 can be output to the outside, and the operation of the selector 102 can be controlled based on the control signal supplied to the control signal input IN23 from the outside. The output of the register 103 is supplied to the data input IN20 of the next-stage selector 102, and the output of the comparator 101 of the previous-stage submodule is supplied to the control signal input IN23 of the next-stage selector 102, so that a plurality of submodules Can be connected in series.

In this case, assuming that the comparator 101 and the selector 102 of each sub-module operate in the same manner as described above, these (m) sub-modules as a whole include the upper m An alignment maximum data circuit for obtaining data can be configured.

As shown in FIG. 3, the maximum alignment data circuit according to the second embodiment of the present invention includes three submodules having the above-described configuration shown in FIG. The maximum alignment data circuit having such a configuration is provided in a digital signal processor (DSP) or a similar large-scale integrated circuit (LSI) or the like, and sorts the top three data in an input data sequence. This is for obtaining the maximum alignment data.

This maximum alignment data circuit includes an input register 301 for holding an input data sequence or input data supplied from an external arithmetic circuit, a memory, or the like, and the above-described three sub-modules (first to third sub-modules). ) 302,
303 and 304 are provided.

The input register 301 has a data width of k (k: the number of bits of each input data) bits or more. To the input of the input register 301, data in a data series (a series of N data) is supplied one by one directly or via a bus from an arithmetic circuit or a memory that generates N positive data. The input register 301
The sequentially supplied data is held and supplied to the first to third sub-modules 302 to 304.

As shown in FIG. 3, the data input IN10 of the comparator 101 and the data input IN20 of the selector 102 of the first to third submodules 302 to 304 are provided.
Is supplied with the output of the input register 301. First
The control signal input IN23 of the selector 102 of the submodule 302 is grounded, and the input IN21 is not used. The input IN21 of the selector 102 of the second and third submodules 302 and 303 is supplied with the output of the register 103 of the first or second submodule 302 and 303, and the control of each selector 102 is performed. Signal input IN2
3 is supplied with the output of the comparator 101 of the first or second sub-module 302, 303.

The comparator 101 of each of the sub-modules 302 to 304, based on the two data inputs IN10 and IN11, performs IN10> as in the first embodiment.
If IN11, 1 is output, and if IN10 ≦ IN11, 0 is output. In addition, the selector 10
2 also has two control signal inputs IN as in the first embodiment.
23, based on IN24, IN23 = 0 and IN24
= 1, the value of IN20 is selected as the output, and IN23 is selected.
When IN = 1 and IN24 = 1, the value of IN21 is selected as an output, and when IN23 = 0 and IN24 = 0, the value of IN22 is output.

Such an operation is performed so that when input data from the arithmetic circuit or the like is sequentially supplied to the input register 301 and an operation clock or the like is supplied, the operation can be performed independently of the operation of the arithmetic circuit or the like. Has become.

Hereinafter, the operation of the maximum alignment data circuit configured as described above will be described, for example, as a data sequence from an arithmetic circuit or a memory to the input register 301 by inputting five 2-bit data (00, 01, 10, 11,. The operation when (10) is sequentially supplied will be described.

(Operation 1) First, each sub-module 302
The contents of the registers 103 to 304 are reset by software or hardware, and all are set to 00.

(Operation 2) Next, the first two-bit data 00 is supplied to the input register 301. The comparator 101 of the first sub-module 302 includes the input register 3
Data input from 01 (hereinafter simply referred to as input) IN1
Data 00 supplied as 0 and a first sub-module 302 (hereinafter, other components (comparator 101, selector 102, register 103, etc.) in the same sub-module)
Are simply referred to as “corresponding components”. ) Is compared with the data 00 supplied from the register 103 as the input IN11.
Since both data supplied to 0 and IN11 are 00, that is, IN10 = IN11, 0 is output.

Similarly, the second and third sub-modules 3
03 and 304 are input registers 30 respectively.
A comparison is made between data 00 supplied as input IN10 from 1 and data supplied as input IN11 from the corresponding register 103 (in this case, both 00).
Since 10 = IN11, 0 is output.

The selector 102 of the first sub-module 302 is supplied with the ground potential, that is, 0, as a control signal input IN23, and receives another control signal input IN24.
The output of the corresponding comparator 101 (in this case, 0 as described above) is supplied. As a result, this selector 10
2 is the value of the input IN22, that is, the corresponding register 10
3 to the register 10
3 again.

Similarly, the second and third sub-modules 3
03, 304, the control signal input I
The first or second sub-module 302, 3 as N23
The output of the comparator 101 (in this case, both 0) is supplied to another control signal input IN
24 as a second or third sub-module 303, 30
The outputs of the four comparators 101 (in this case, both are 0) are supplied. As a result, these selectors 102 switch the input IN22
, That is, the data currently held in the corresponding register 103 (in this case, 00 in both cases) is supplied to each register 103 again.

(Operation 3) When the comparison, selection and the like as described above are completed and a clock (the above-mentioned operation clock) for instructing data holding is supplied to each register 103, the register of the first sub-module 302 103 holds the data 00 supplied from the corresponding selector 102. At the same time, the registers 103 of the second and third sub-modules 303 and 304 hold the data (in this case, both 00) supplied via the corresponding selectors 102.

(Operation 4) The second 2-bit data 01 is supplied to the input register 301 at the same time as or after the (operation 3) described above.

The comparator 10 of the first sub-module 302
1 compares the data 01 supplied from the input register 301 as the input IN10 with the data 00 supplied from the corresponding register 103 as the input IN11.
Since 10> IN11, 1 is output.

Similarly, the second and third sub-modules 3
03 and 304 are input registers 30 respectively.
A comparison is made between the data 01 supplied from 1 as the input IN10 and the data supplied as the input IN11 from the corresponding register 103 (in this case, both 00).
Since 10> IN11, 1 is output.

The selector 102 of the first sub-module 302 is supplied with the ground potential, ie, 0, as the control signal input IN23, and outputs the corresponding output (1 in this case) of the comparator 101 as the control signal input IN24. Supplied. As a result, the selector 102 supplies the value of the input IN20, that is, the data 01 from the input register 301, to the register 103.

Similarly, the second and third sub-modules 3
03, 304, the control signal input I
The first or second sub-module 302, 3 as N23
03 (1 in this case) are supplied to the corresponding comparator 10 as a control signal input IN24.
One output (in this case, one) is provided. As a result, these selectors 102 supply the value of the input IN21, that is, the data (in this case, both 00) from the registers 103 of the first or second submodule 302, 303 to the corresponding register 103.

(Operation 5) When the above-described comparison, selection and the like are completed and the above-mentioned operation clock is supplied, the input to the register 103 of the first sub-module 302 via the corresponding selector 102 is performed. The data 01 supplied from the register 301 is held. At the same time, the registers 103 of the second and third sub-modules 303 and 304 are stored in the registers 103 of the first or second sub-modules 302 and 303 via the corresponding selectors 102 (in this case, Are both set to 00).

(Operation 6) The third two-bit data 10 is supplied to the input register 301 at the same time as or after the above (operation 5).

The comparator 10 of the first sub-module 302
1 compares the data 10 supplied from the input register 301 as the input IN10 with the data 01 supplied from the corresponding register 103 as the input IN11.
Since 10> IN11, 1 is output.

Similarly, the second and third sub-modules 3
03 and 304 are input registers 30 respectively.
A comparison is made between data 10 supplied as input IN10 from 1 and data supplied as input IN11 from the corresponding register 103 (in this case, both 00).
Since 10> IN11, 1 is output.

The selector 102 of the first sub-module 302 is supplied with the ground potential, that is, 0, as the control signal input IN23 and the output 1 of the corresponding comparator 101 as the control signal input IN24. As a result, the selector 102 supplies the value of the input IN20, that is, 10 which is the data supplied from the input register 301, to the register.

Similarly, the second and third sub-modules 3
03, 304, the control signal input I
The first or second sub-module 302, 3 as N23
03 (1 in this case) are supplied to the corresponding comparator 10 as a control signal input IN24.
One output (in this case, one) is provided. As a result, these selectors 102 store the value of the input IN21, that is, the data 01, 00 from the register 103 of the first or second sub-module 302, 303 into the corresponding register 1
03.

(Operation 7) When the above-described comparison, selection and the like are completed and the above-mentioned operation clock is supplied, the register 103 of the first sub-module 302 is supplied from the corresponding selector 102. 10 is held. At the same time, the registers 103 of the second and third submodules 303 and 304 hold the data 01 and 00 supplied through the corresponding selectors 102, respectively.

(Operation 8) The fourth two-bit data 11 is supplied to the input register 301 at the same time as or after the above (Operation 7).

The comparator 10 of the first sub-module 302
1 compares the data 11 supplied from the input register 301 as the input IN10 with the data 10 supplied from the corresponding register 103 as the input IN11.
Since 10> IN11, 1 is output.

Similarly, the second and third sub-modules 3
The comparator 101 of 03 compares the data 11 supplied from the input register 301 as the input IN10 with the data 01 and 00 supplied from the corresponding register 103 as the input IN11, and since IN10> IN11, 1 Is output.

The selector 102 of the first sub-module 302 is supplied with the ground potential, that is, 0, as the control signal input IN23, and is supplied with the output 1 of the corresponding comparator 101 as the control signal input IN24. As a result, the selector 102 sets the value of the input IN20, that is, the input register 3
The data 11 supplied from 01 is supplied to the register.

The second and third sub-modules 303, 3
The selector 102 of 04 is supplied with the output (in this case, 1) of the comparator 101 of the first or second submodule 302, 303 as the control signal input IN23, and corresponds to the control signal input IN24. The output of the comparator 101 (in this case, both are 1) is supplied. As a result, these selectors 102 determine the value of the input IN21, ie, the register 10 of the first or second sub-module 302, 303.
The data 10, 01 from 3 are supplied to the corresponding register 103.

(Operation 9) When the above-described comparison and selection are completed and the above-described operation clock is supplied, the register 103 of the first sub-module 302 is supplied from the corresponding selector 102. 11 is stored. At the same time, the registers 103 of the second and third submodules 303 and 304 hold the data 10 and 01 supplied through the corresponding selectors 102, respectively.

(Operation 10) The fifth 2-bit data 10 is supplied to the input register 301 at the same time as or after the above (Operation 9).

The comparator 10 of the first sub-module 302
1 compares the data 10 supplied from the input register 301 as the input IN10 with the data 11 supplied from the corresponding register 103 as the input IN11.
Since 10 <IN11, 0 is output.

The comparator 10 of the second sub-module 303
1 compares data 10 supplied as input IN10 from input register 301 with data 10 supplied as input IN11 from corresponding register 103,
Since 10 = IN11, 0 is output.

The comparator 10 of the third sub-module 304
1 compares the data 10 supplied from the input register 301 as the input IN10 with the data 01 supplied from the corresponding register 103 as the input IN11.
Since 10> IN11, 1 is output.

The selector 102 of the first sub-module 302 is supplied with the ground potential, that is, 0, as the control signal input IN23 and the output 0 of the corresponding comparator 101 as the control signal input IN24. As a result, the selector 102 supplies the value of the input IN22, that is, the data 11 currently held in the corresponding register 103, to the register 103 again.

The selector 10 of the second sub-module 303
2, the output 0 of the comparator 101 of the first sub-module 302 is supplied as the control signal input IN23, and the output 0 of the corresponding comparator 101 is supplied as the control signal input IN24. As a result, the selector 102 sets the input IN2
The value of 2, that is, the data 10 currently held in the corresponding register 103 is supplied to the register 103 again.

The selector 10 of the third sub-module 304
2, the output 0 of the comparator 101 of the second sub-module 303 is input as the control signal input IN23, and the output 1 of the corresponding comparator 101 is input as the control signal input IN24. As a result, the selector 102 sets the input IN2
A value of 0, that is, 10 which is data from the input register 301 is supplied to the corresponding register 103.

(Operation 11) When the above-described comparison, selection and the like are completed and the above-described operation clock is supplied, the data is supplied to the register 103 of the first sub-module 302 via the corresponding selector 102. The data 11 obtained is retained. At the same time, register 1 of second submodule 303
03, data held in the register and supplied again via the corresponding selector 102 (in this case, 1
0) is retained.

The data (10 in this case) supplied from the input register 301 via the corresponding selector 102 is stored in the register 103 of the third sub-module 304.
Is held.

Here, each of the sub-modules 302 to 304
The comparator 101 sets the output to 1 only when the data from the input register 301 is larger than the data held in the corresponding register 103 as described above. When the output of the comparator 101 is 0, the data held in the register 103 corresponding to the comparator 101 is equal to or greater than the data supplied from the input register 301.
The corresponding selector 102 supplies the data held in the register 103 to the register 103 again.

When the output of the comparator 101 becomes 1, the selector 102 in which the output of the preceding comparator 101 is 0
Supplies the data from the input register 301 to the corresponding register 103. In a sub-module subsequent to the sub-module to which the selector 102 belongs, the comparator 101
Becomes 1 and the output of the comparator 101 at the preceding stage becomes 1, so that the selector 102 supplies the data from the register 103 at the preceding stage to the corresponding register 103. Therefore, the data held in the register 103 holding data equal to or less than the data supplied from the input register 301 is transferred to the register 103 of the sub-module in the next stage.

If the data from the input register 301 is the same as the data held in the register 103 of any of the submodules, the output of the comparator 101 of this submodule becomes 0, and The data held in register 103 is input register 30
1, the data held in the register 103 of the sub-module subsequent to this sub-module, and the data held in the register 103 of the subsequent sub-modules are sequentially stored in the register 103 of the next-stage sub-module. It is deferred.

Therefore, in this maximum alignment data circuit, when the data values are the same, the data in the original data series, which has the earlier order, is ranked higher and the data is sorted. For this reason, stable alignment can be performed.

When the operations (operation 1) to (operation 11) described above are completed, the data 103 is stored in the registers 103 of the first sub-module 302, the second sub-module 303, and the third sub-module 304, respectively. , 10,
10 is held. These data are the upper three data of the input five 2-bit data 00, 01, 10, 11, and 10, that is, the expected maximum alignment data.

The processing for obtaining the maximum alignment data is performed by hardware as described above, and the arithmetic operation by another arithmetic unit in a DSP or the like provided with such a maximum alignment data circuit, Since the operation is performed independently of the logical operation or the like, it is possible to reduce the number of instruction steps in a DSP or the like, to reduce the number of additional processes, and the like.

Further, by performing the processing for obtaining the maximum alignment data in hardware, it is possible to perform parallel processing with other operations in a DSP or the like, and to obtain the maximum alignment data while performing the operation related to data generation. Becomes possible. In this case, the generated data is sequentially supplied to the maximum alignment circuit, so that it is necessary to temporarily store the generated data in a memory as in the case of obtaining the maximum alignment data by a conventional selective sorting method, and then perform an operation. As a result, it is possible to reduce write / read processing for the memory, reduce the occupied capacity of the memory for saving data, and the like.

The maximum alignment data circuit can be easily expanded by adding sub-modules according to the number of maximum alignment data.

In the maximum alignment data circuit, the timing at which the comparison of each sub-module by the comparator 101 is performed depends on the timing at which data is supplied from the input register 301. Therefore, no delay occurs even if the number m is increased. Therefore, this alignment maximum data circuit does not have a bottleneck that degrades the performance of the entire arithmetic circuit, and can be easily expanded without deteriorating the performance.

The input register 301 is provided in the maximum alignment data circuit shown in FIG. This takes into account a case where the operation time required for data generation is long, or a case where access to a bus which is a path for supplying data as an operation result to the maximum alignment data circuit is congested. The input register 301 can be omitted when the operation for generation is completed in a short time, or when data is directly input from the data operation circuit or the like to the maximum alignment data circuit without using a bus.

When data is stored in a memory such as a RAM or a ROM, and data is sequentially read from these memories and supplied to the maximum alignment data circuit, an instruction to read data from the memory is issued. If the memory read instruction to be executed and the processing for obtaining the maximum alignment data as described above can be performed in parallel, the input register 3
01 can be omitted.

In the description of each of the above embodiments, the comparator 101 of each submodule inputs the data (IN
10) is compared with the data held in the register 103, and the output (comparison result) is set to 1 only when the input data is larger than the data held in the register 103. May be set to 1 only when the input data is smaller than the data held in the register 103, and may be set to 0 when the input data is equal to or larger than the data held in the register 103. The comparator 101 operating in this manner is
It operates as a minimum value circuit for finding the minimum data in the input data series. In this case, the maximum value (here, 11) is assigned to the register 103 at the time of resetting by software or hardware.

Further, by using the comparator 101 operating in this manner to constitute an arithmetic circuit having the same configuration as that of FIG. 3, the minimum alignment data circuit for obtaining the lower three data in the input data sequence Can be configured.
Alternatively, the operation of the comparator 101 (for example, one of IN10-IN11 and IN11-IN10) may be switched by external control, and the operation may be controlled by an external arithmetic circuit or the like.

In addition, within the scope of the technical idea of the present invention, for example, in FIG. 3, the number of sub-modules is three, but various changes can be made such as changing the number of sub-modules.

[0090]

In the data operation circuit according to the present invention, when the data in the data series is sequentially supplied from outside as the first data, the data supplied to the comparator and the data held in the internal register are output. The selector selects one of the second data supplied from the outside, the first data, and the data held in the internal register according to the control signal from the outside and the comparison result from the comparator. And supplies it to the internal register. Thereby, specific data in the input data series can be selected based on the comparison result of the comparator.

For example, when the comparator detects that the first data is larger (or smaller) than the data held in the internal register, the selector supplies the first data to the internal register, and the selector supplies the first data to the internal register. If the selector holds the data held in the internal register again to the internal register when the data is equal to or smaller than the data held in the internal register, the first register sequentially supplied to the internal register is provided. After the maximum (or minimum) data in the data has been supplied and all the data in the data series have been supplied, the internal register holds the maximum (or minimum) data in the data series. .

Since the detection of such data is performed by hardware, a D provided with such a data operation circuit is provided.
The processing load of an arithmetic unit such as an SP (Digital Signal Processor) can be reduced.

In another data operation circuit according to the present invention, when data in a data series is sequentially supplied as first data from the outside, the comparators of the respective operation units operate in such a manner that the supplied data, the comparator and The data is compared with data held in an internal register provided in the same operation unit. Each selector selects the second data supplied from the register of the preceding operation unit based on the control signal from the comparing means of the preceding operation unit and the comparison result from the comparator provided in the same operation unit as the selector. , One of the first data supplied from the outside and the data held in the internal register is selected and supplied to the internal register. Thereby, based on the comparison result of the comparator of each operation unit, it is possible to select the specific data of the number corresponding to the number of the operation units in the input data series.

For example, when the comparator of each arithmetic unit has the first data equal to or smaller than the data held in the internal register, the selector supplies the data held in the internal register to the internal register again. If the selector detects that the first data is larger (or smaller) than the data held in the internal register, the selector selects the first data based on the control signal (comparison result from the comparator of the previous calculation unit). It is determined whether or not the data of the internal register of the unit has been changed, and if the data of the internal register of the preceding operation unit has not been changed, the first data is supplied to the internal register;
If the data in the internal register of the preceding operation unit has been changed, the second data is supplied to the internal register, so that each internal register stores the data in the data series supplied so far. After the upper (or lower) data has been supplied and all the data in the data series have been supplied, each internal register holds the upper (or lower) data in the data series.

The time required to obtain the upper (or lower) data as described above is substantially equal to the time to supply the data in the data sequence once. Therefore, the data in the data sequence stored in the memory or the like is required. The higher (or lower) data in the data series can be obtained at a much higher speed than in the conventional method that needs to be supplied a plurality of times.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a submodule according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a data operation circuit provided in a conventional DSP or an LSI similar thereto.

FIG. 3 is a block diagram showing a configuration of an alignment maximum data circuit according to a second embodiment of the present invention.

[Explanation of symbols]

101 comparator, 102 selector, 103 register,
301 input register, 302-304 submodule

Claims (8)

[Claims] An internal register for holding data, a comparator for comparing first data supplied from the outside with data held in the internal register, and outputting a comparison result; Based on the signal and the comparison result from the comparator, one of the second data supplied from outside, the first data, and the data held in the internal register is selected and stored in the internal register. And a selector for supplying the data. 2. The comparator according to claim 1, wherein when the data supplied from the outside is larger than the data stored in the internal register, the comparison result is a first value, and the data supplied from the outside is stored in the internal register. If the comparison result is equal to or less than the set data, the comparison result is set to the second value. If the comparison result from the comparator is the first value, the selector sets the first value based on the control signal. And the second data is selected and supplied to the internal register. When the comparison result from the comparator is a second value, the data is held in the internal register based on the control signal. 2. The data operation circuit according to claim 1, wherein the selected data is supplied to an internal register. 3. The comparator according to claim 1, wherein when the data supplied from the outside is smaller than the data held in the internal register, the comparison result is a first value, and the data supplied from the outside is held in the internal register. If the comparison result is equal to or more than the set data, the comparison result is set to the second value. If the comparison result from the comparator is the first value, the selector sets the first value based on the control signal. And the second data is selected and supplied to the internal register. When the comparison result from the comparator is a second value, the data is held in the internal register based on the control signal. 2. The data operation circuit according to claim 1, wherein the selected data is supplied to an internal register. 4. The data operation circuit according to claim 2, further comprising an input register for holding the first or second data. 5. An internal register for holding data, a comparator for comparing first data supplied from the outside with data held in the internal register, and outputting a comparison result; Based on the signal and the comparison result from the comparator, one of the second data supplied from outside, the first data, and the data held in the internal register is selected and stored in the internal register. A plurality of operation units each including a selector to be supplied; an output of a comparator of the operation unit of the preceding stage as a control signal of a selector of the operation unit of the next stage; A data operation circuit characterized in that the data held in the data operation circuit is supplied as the second data to the selector of the operation unit at the next stage and connected in multiple stages. 6. Each of the comparators sets the comparison result to a first value when the data supplied from the outside is larger than the data held in the internal register, and outputs the data supplied from the outside to the internal register. When the comparison result is equal to or less than the held data, the comparison result is set to the second value. When the comparison result from the comparator is the first value, the selector determines the second value based on the control signal. One of the first data and the second data is selected and supplied to the internal register. If the comparison result from the comparator is a second value, the data is held in the internal register based on the control signal. 6. The data operation circuit according to claim 5, wherein selected data is supplied to an internal register. 7. Each of the comparators sets the comparison result to a first value when the data supplied from the outside is smaller than the data held in the internal register, and outputs the data supplied from the outside to the internal register. When the comparison result is equal to or more than the held data, the comparison result is set to the second value. When the comparison result from the comparator is the first value, the selector determines the second value based on the control signal. One of the first data and the second data is selected and supplied to the internal register. If the comparison result from the comparator is a second value, the data is held in the internal register based on the control signal. 6. The data operation circuit according to claim 5, wherein selected data is supplied to an internal register. 8. An input register for holding the first or second data to be supplied to at least a comparator or selector of a first-stage operation unit of the plurality of operation units. 8. The data operation circuit according to 6 or 7.