JPH1056797A - Pulse generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen the burden on a CPU through an inexpensive arrangement without requiring any CPU for exclusive use. SOLUTION: A pulse generator section 1 counts the original clock CK and generates a pulse having set width corresponding to the acceleration of a motor M. A pulse counter section 2 counts pulses generated from the pulse generator section 1 and compares the counted pulse with a set value corresponding to the duration of acceleration of the motor M. When they match each other, an interruption signal is generated for a CPU 3 which performs an interruption processing based on the interruption signal from the pulse counter section 2 to set the pulse generator section 1 and the pulse counter section 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator for generating a drive pulse for controlling the acceleration of a motor and the duration of the acceleration in an image forming apparatus such as a copying machine or a printing machine.

[0002]

2. Description of the Related Art Conventionally, a pulse generator of this type generates an H or L pulse in a timer interrupt process of a CPU (hereinafter, device CPU) of an image forming apparatus and sets a time interval at which the interrupt process occurs. By sequentially changing the pulse width, the pulse width is changed as a result, and the pulse duration is changed, and the duration of the number of pulses is varied, thereby controlling the motor acceleration and the duration of the acceleration. Is configured.

[0003]

However, in the above-mentioned conventional method, when the pulse frequency to be generated is very high, the timer interrupt processing of the apparatus CPU frequently occurs, so that the processing speed other than the interrupt processing is reduced. There is a problem. Also, this problem is caused by one device CPU.
Therefore, when the acceleration / deceleration control is performed on a plurality of actuators, the acceleration becomes remarkable. In order to solve the above problem, a method of providing a CPU dedicated to pulse generation as shown in, for example, Japanese Patent Application Laid-Open No. 2-159879 is conceivable.
In this case, although fine control is possible, the cost increases.

The present invention has been made in view of the above-mentioned conventional problems, and provides a pulse generator capable of reducing the load on the device CPU and improving the processing speed other than the interrupt processing with an inexpensive configuration without providing a dedicated CPU. The purpose is to do.

[0005]

According to a first aspect of the present invention, there is provided a pulse generator for controlling the acceleration of a motor based on a variable pulse width. A clock number storage unit that stores a clock number corresponding to a pulse width corresponding to the acceleration of the clock counter, and compares the count value of the clock counter with the number of clocks stored in the clock number storage unit. Pulse generating means for generating a pulse whose low level has been switched and applying the pulse to the motor.

The second means is characterized in that in the first means, the CPU sets the number of clocks in the clock number storage means when the acceleration of the motor is switched.

Third means is a pulse number storing means for storing the number of pulses corresponding to a variable time during which the acceleration of the motor is continued in the second means, and a pulse for counting the number of pulses generated by the pulse generating means. A counter, and an interrupt signal generating means for comparing the count value of the pulse counter with the number of pulses stored in the pulse number storing means, and outputting an interrupt signal to the CPU when they match. I do.

A fourth means is the third means, wherein the C
The PU sets the number of clocks in the number-of-clocks storage means by interrupt processing when the interrupt signal is input, and sets the number of pulses in the number-of-pulses storage means.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a pulse generator according to the present invention, FIG. 2 is a block diagram showing an example of a circuit in which a CPU sets data in a register in FIG. 1, and FIG. 3 is an interrupt process of the CPU in FIG. FIG. 4 is an explanatory diagram showing an example of acceleration when the motor is accelerated and decelerated and a time period during which the acceleration is continued,
FIG. 5 is an explanatory diagram showing a table of the CPU of FIG. 1, and FIG. 6 is an explanatory diagram showing an acceleration when the motor is accelerated / decelerated and a setting timing of a time for which the acceleration is continued.

The pulse generator shown in FIG. 1 schematically includes a pulse generator unit 1 for counting an original clock CK and generating a motor clock (pulse) having a set width according to the acceleration of the motor M; The pulse counter unit 2 counts the pulses generated by the timer, compares it with a set value corresponding to the time during which the acceleration of the motor M is continued, and generates an interrupt signal when the pulses coincide with each other. Interrupt processing by the interrupt signal from the pulse counter unit 2 And a CPU 3 for making respective settings for the pulse generator 1 and the pulse counter unit 2.

The pulse generator 1 has a motor clock width setting register 11, a clock counter 12, a comparator 13, and a motor clock generator 14. The motor clock width setting register 11 is preliminarily controlled by the CPU 3 to correspond to a pulse width corresponding to the acceleration. Clock number data is set. The clock counter 12 uses the original clock C
K is counted up, and the comparator 13 compares the value set in the motor clock width setting register 11 with the count value of the clock counter 12, and outputs a match signal when they match, and clears the match signal (not shown) of the clock counter 12.
Is output to the motor clock generator 14.

The motor clock generator 14 is constituted by a flip-flop, and a Q output signal is applied as a D input signal. When the coincidence signal from the comparator 13 is applied, the pulse of the Q output signal is toggled and the pulse signal is applied to the motor M and the motor clock counter 22.

The pulse counter section 2 has a motor count compare register 21, a motor clock counter 22, and a comparator 23.
Thus, the pulse number data corresponding to the time during which the acceleration is continued is set. The motor clock counter 22 counts output pulses of the motor clock generator 14,
The comparator 23 is a motor count compare register 2
The value set to 1 is compared with the count value of the motor clock counter 22.
U3 and a clear terminal (not shown) of the motor count compare register 21 are output.

The configuration for setting data from the CPU 3 to the registers 11 and 21 can be realized by using a decoder 4 as shown in FIG. 2, for example. The CPU 3 and the registers 11 and 21 are connected to each other via a read / write control signal line (/ WR) and a data bus.
U3 and decoder 4 are connected via an address bus. The output signal of the decoder 4 is the register 11,
21 is applied to the enable terminal.

The registers 11 and 21 are mapped on an address when viewed from the CPU 3, and
Accesses the address, the output signal corresponding to the address among the plurality of output signals of the decoder 4 becomes active. At the same time, the CPU 3 outputs the set value on the data bus and the write control signal / WR.
Is activated, the set value on the data bus is set in the registers 11 and 21. Registers 11, 21
Is constituted by a latch or a D flip-flop, and holds this set value until the next access.

Here, the comparator 23 compares the value set in the motor count compare register 21 with the count value of the motor clock counter 22 and outputs an interrupt signal to the CPU 3 when they match, so that the motor clock generator 14 After generating the number of pulses, the CPU 3 starts the interrupt processing and sets the pulse width of the next acceleration and the number of output pulses in the registers 21 and 11, respectively.

FIGS. 3 to 6 show, as an example, as shown in FIG. 4, the motor M is stepwise accelerated in steps "1" to "4", and is rotated at a constant speed in step "5". 6 "
5 shows the processing when the vehicle is decelerated and stopped in steps 8. In the CPU 3, as shown in FIG. The number of pulses PC _n (PC _{1 to} PC ₈ ) to be generated and the number of clocks f _n (f _{1 to} f ₈ ) corresponding to the acceleration are stored in this order. The symbol a shown in FIG.
Is an address indicating the number of output pulses PC _n , and a symbol b is an address indicating the number of clocks f _n .

The interrupt process of the CPU 3 will be described with reference to FIG. 3. First, when an interrupt signal is input from the comparator 23, the interrupt process is started (step S1), and then, the table shown in FIG. The counter CNT (= n) is incremented by one (step S2). Then, the count value CNT is compared with the maximum data number “8” in the table (step S3). If they do not match, the pulse number PC _n and the pulse frequency f _n of the table indicated by the count value CNT as shown in FIG. The corresponding pulse width is set in each of the registers 21 and 11 (step S4), and this interrupt processing ends (step S7).

In step S3, the count value C
When NT and the maximum data number “8” in the table match, each initial value PC of the pulse number PC _n and the clock number f _n is used.
_1, set f ₁ to the registers 21 and 11 (step S5), and then disable interrupts as well as to turn off the motor M (step S6), and ends this interrupt processing (step S7).

Therefore, according to the above-described embodiment, the pulse generator 1 counts the original clock CK and generates a pulse having a set width corresponding to the acceleration of the motor M.
Further, the pulse generated by the pulse generator unit 1 is counted by the pulse counter unit 2 and compared with a set value corresponding to the time for which the acceleration of the motor M is continued. CPU3
Is a pulse generator 1 and a pulse counter 2 in an interrupt process by an interrupt signal from the pulse counter 2.
Since only the respective settings are performed, the load on the CPU 3 can be reduced and the processing speed other than the interrupt processing can be improved with an inexpensive configuration without providing a dedicated CPU. In the above embodiment, the case where only one type of pulse is generated has been described. However, a plurality of types of pulses can be generated by adding a counter in conjunction with the clock counter 12 in the pulse generator 1.

[0021]

As described above, according to the first aspect of the present invention, the pulse for controlling the acceleration during the acceleration / deceleration of the motor is generated by hardware, so that the dedicated CP is used.
It is possible to improve the processing speed other than the interrupt processing by reducing the load on the apparatus CPU with an inexpensive configuration without providing the U.

According to the second aspect of the present invention, since the CPU sets the number of clocks corresponding to the pulse width according to the acceleration of the motor, the load on the CPU is reduced and the processing speed other than the interrupt processing is improved. Can be.

According to the third aspect of the present invention, the number of pulses for controlling the time during which the acceleration of the motor is continued is counted by hardware to generate an interrupt signal, so that an inexpensive CPU can be provided without providing a dedicated CPU. Device C by configuration
The processing speed other than the interrupt processing can be improved by reducing the load on the PU.

According to the present invention, the CPU only sets the number of clocks corresponding to the pulse width corresponding to the acceleration of the motor and the number of pulses corresponding to the time during which the acceleration is continued. The load can be reduced and the processing speed other than the interrupt processing can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a pulse generator according to the present invention.

FIG. 2 is a block diagram illustrating a circuit example in which a CPU sets data in a register of FIG. 1;

FIG. 3 is a flowchart illustrating an interrupt process of a CPU in FIG. 1;

FIG. 4 is an explanatory diagram illustrating an example of acceleration when the motor is accelerated and decelerated and a time period during which the acceleration is continued.

FIG. 5 is an explanatory diagram showing a table of a CPU in FIG. 1;

FIG. 6 is an explanatory diagram showing acceleration when the motor is accelerated / decelerated and setting timing of a time period during which the acceleration is continued.

[Explanation of symbols]

 Reference Signs List 1 pulse generator section 2 pulse counter section 3 CPU 11 motor clock width setting register 12 clock counter 13 comparator 14 motor clock generator 21 motor clock compare register 22 motor clock counter 23 comparator

Claims (4)

[Claims] 1. A pulse generator for controlling a motor acceleration based on a variable pulse width, a clock counter for counting clocks, and a clock number for storing a clock number according to a pulse width according to the motor acceleration. Pulse generating means for comparing the count value of the clock counter with the number of clocks stored in the clock number storing means, generating a pulse switched between high level and low level and applying the same to the motor when they match And a pulse generator comprising: 2. The pulse generator according to claim 1, wherein a CPU sets the number of clocks in said clock number storage means when switching the acceleration of said motor. 3. A pulse number storage means for storing a pulse number corresponding to a variable time during which the acceleration of the motor continues, a pulse counter for counting the number of pulses generated by the pulse generation means, and a count value of the pulse counter. 3. The pulse generation device according to claim 2, further comprising: an interruption signal generation unit that compares the number of pulses stored in the pulse number storage unit with each other, and outputs an interruption signal to the CPU when the numbers match. apparatus. 4. The CPU according to claim 1, wherein the CPU sets the number of clocks in the number-of-clocks storage means by interrupt processing when the interrupt signal is input, and sets the number of pulses in the number-of-pulses storage means. 3. The pulse generator according to 3.