JPH1056159A - Manufacture of semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make contact holes having an identical size in an interlayer insulating film formed on respective elements in a circuit, even when multilayered electrodes are used for a gate of a nonvolatile memory in an integrated circuit having a nonvolatile memory. SOLUTION: When multilayered gate electrodes 7, 9c are used for a gate of a nonvolatile memory element, the height of the electrodes 7, 9c are different from that of gate electrodes 9a, 9b of peripheral logic circuit elements. To avoid this, in a photolithographic step, a photoresist layer 18 on the nonvolatile memory element is made thicker than the pholoresist layer 18 on the peripheral logic circuit element. When masks 17 having identical mask dimensions A and B are used in developing process, a sufficient resolution of the thicker photoresist layer 18 on the nonvolatile memory element cannot be realized and thus contact holes to be made later cannot have an identical size. To avoid this, the mask dimension B is made larger than the mask dimension A to provide a sufficient resolution for the photoresist layer 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having a nonvolatile memory and a peripheral logic circuit.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device having a nonvolatile memory section M and a peripheral logic circuit section L using multilayer gate electrodes 7 and 9c as shown in FIG. 5, electrodes are applied to the source and drain of each element. Therefore, contact holes 31 to 35 are formed in the interlayer insulating film 16. These contact holes 31 to 35 are formed by photolithography etching.

At this time, in the photolithography process,
Forming a photoresist 18 on the upper surface of the interlayer insulating film 16;
As shown in FIG. 6, the developing process is performed using the mask 17 having the same mask dimension (dimension of the light transmitting portion), and the contact hole 31 is formed.
Resolve the photoresist 18 on the part forming .about.35. Here, since the gate electrodes 7 and 9c and the gate electrodes 9a and 9b of the peripheral logic circuit portion L have different heights, a step is formed in the photoresist 18. Therefore, during the developing process, the focus is on the peripheral logic circuit portion L where the height of the photoresist 18 is low. For example, when the mask 17 having a mask dimension of 0.65 μm is used, the focus is adjusted so that the dimension C of the contact holes 32 to 35 of the peripheral logic circuit portion L becomes 0.65 μm after etching.

[0004] Thereafter, in an etching step, the interlayer insulating film 16 is removed by etching from the resolved portion to form contact holes 31 to 35.

[0005]

However, as described above, the photoresist 18 of the peripheral logic circuit portion L having a small height is used.
Therefore, the resolution of the photoresist 18 of the nonvolatile memory unit M having a high height is not sufficiently resolved. Further, since the photoresist 18 of the nonvolatile memory section M is thicker than the peripheral logic circuit section L, the phenomenon processing is insufficient.

For these reasons, the resolution of the photoresist 18 on the nonvolatile memory section M is not sufficient, and the contact hole 31 of the nonvolatile memory section M becomes small.
For example, when the above-described mask 17 is used, the contact dimension D of the contact hole 31 of the non-volatile memory unit M is set to 0.
595 μm, which is smaller than the contact size C of the contact holes 32 to 35 of the peripheral logic circuit portion L by 0.05
It becomes smaller by 5 μm.

As a result, there arises a problem that the contact resistance of the non-volatile memory portion M is increased as compared with the peripheral logic circuit portion L, or a conduction failure occurs because the contact hole 31 is not formed sufficiently. This problem becomes more remarkable as the elements formed in the semiconductor memory device become finer. Further, the thickness of the photoresist 18 can be made uniform by flattening the interlayer insulating film 16 (for example, by forming a TEOS film and then flattening it by a method of etching back or a method of CMP polishing). Problem can be solved. However, there is a problem that a flattening step or the like is required and the number of steps is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and provides an electrical connection between a source and a drain of a nonvolatile memory element and a source and a drain of a peripheral logic circuit element without using a step of planarizing an interlayer insulating film. An object of the present invention is to enable a contact hole to be formed to have the same size.

[0009]

To achieve the above object, the following technical means are employed. The semiconductor substrate (1) includes a nonvolatile memory element having a multi-layer gate electrode (7, 9c) and a peripheral logic circuit element having a single-layer gate electrode (9a, 9b). The drains (12,
14) and a method of manufacturing a semiconductor memory device in which contact holes (31 to 35) of sources (11, 13, 15) are formed in an interlayer insulating film (16) by photolithography etching, the mask dimension (B) is changed to the mask dimension ( A) Using a larger mask (17), removing the photoresist (18) on portions where the contact holes (31 to 35) are to be formed, and forming the contact holes (31 to 35). .

As described above, by making the mask size (B) on the non-volatile memory element larger than the mask size (A) on the peripheral logic circuit element, the photoresist (18) can be sufficiently resolved in the developing process. be able to.
Thus, even when a multi-layer gate electrode (7, 9c) is used as a gate of a nonvolatile memory element of a semiconductor memory device, a contact hole (7) formed in an interlayer insulating film (16) formed on each element. 31 to 35) can be formed in the same size.

When two layers of gate electrodes (7, 9c) are used for the gate of the nonvolatile memory element, the contact dimensions C and D of the contact holes (31 to 35) are formed to be the same. FIG. 4 shows the relationship between the mask dimension (A) on the peripheral logic circuit element and the mask dimension (B) on the nonvolatile memory element. As shown in FIG.
In the case where the gate electrodes (7, 9c) of the layers are used, when the mask dimensions (A) and (B) are smaller than about 0.73 μm, the mask dimensions (B) on the nonvolatile memory element are changed to the peripheral logic circuit elements. The contact dimensions C and D of the contact holes (31 to 35) must be larger than the above mask dimensions (A).
Are not formed to the same size. Since the thickness of the photoresist (18) used for forming the contact holes (31 to 35) is almost fixed, the thickness of the peripheral logic shown in FIG. 4 does not depend on the thickness of the photoresist (18). The relationship between the mask dimension (A) on the circuit element and the mask dimension (B) on the nonvolatile memory element can be said.

Based on this, in the invention according to the second aspect, when two layers of gate electrodes (7, 9c) are used for the gate of the nonvolatile memory element, the mask dimensions (A,
When B) is smaller than about 0.73 μm, the contact holes (31 to 31) are formed using a mask (17) in which the mask size (B) on the nonvolatile memory element is larger than the mask size (A) on the peripheral logic circuit element. The photoresist (18) on the part where 35) is to be formed is removed, and the contact hole (3) is removed.
1 to 35).

According to this, when two layers of gate electrodes (7, 9c) are used for the gate of the nonvolatile memory element, the contact holes (31) of the same size are formed in the interlayer insulating film (16) as in the first aspect. To 35) can be formed.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 1 is a partial cross-sectional view of a semiconductor memory device according to an embodiment of the present invention during manufacture. In addition,
The figure shows a cross section of the semiconductor memory device after contact holes 31 to 35 are formed in the interlayer insulating film 16. The semiconductor memory device shown in the figure has a peripheral logic circuit section L on the left side of the drawing and a nonvolatile memory section M on the right side. An N-type well diffusion layer 2 and a P-type well diffusion layer 3 are formed on the surface of a silicon substrate 1. Above the N-type well diffusion layer 2, a P-channel MOS transistor (peripheral logic circuit element) constituting a part of the peripheral logic circuit portion L is formed.

A P ⁺ -type drain diffusion layer 14 serving as a drain of the P-channel MOS transistor and a P ⁺ -type source diffusion layer 15 serving as a source are formed in the surface of the N-type well diffusion layer 2. A gate oxide film 6a is formed on P ⁺ -type drain diffusion layer 14 and P ⁺ -type source diffusion layer 15, and a polysilicon layer 9a serving as a gate of a P-channel MOS transistor is formed on gate oxide film 6a.
Are formed.

On the P-type well diffusion layer 3, an N-channel MOS transistor (peripheral logic circuit element) constituting a part of the peripheral logic circuit section L and a nonvolatile memory element constituting the nonvolatile memory section M are formed. Have been. This N
An N ⁺ -type drain diffusion layer 12 serving as a drain of the channel MOS transistor and an N ⁺ -type source diffusion layer 13 serving as a source are formed in a surface portion of the P-type well diffusion layer 3.
A gate oxide film 6b is formed on N ⁺ -type drain diffusion layer 12 and N ⁺ -type source diffusion layer 13, and a polysilicon layer serving as a gate of an N-channel MOS transistor is formed on gate oxide film 6b. 9b is formed.

An N ⁺ -type drain diffusion layer 10 serving as a drain of the nonvolatile memory element and an N ⁺ -type source diffusion layer 11 serving as a source are formed in the surface layer of the P-type well diffusion layer 3. A gate oxide film 5 is formed on the N ⁺ -type drain diffusion layer 10 and the N ⁺ -type source diffusion layer 11, and the gate electrodes 7 and 9c of the nonvolatile memory element are formed on the gate oxide film 5. Is formed in a two-layer structure with an interlayer insulating film 8 interposed therebetween.

On the surfaces of the N-type well diffusion layer 2 and the P-type well diffusion layer 3, these elements are located between the P-channel MOS transistor, the N-channel MOS transistor, and the nonvolatile memory element. An element isolation insulating film 4 is formed in order to isolate this. And
P-channel MOS transistor, N-channel MOS transistor, nonvolatile memory element, and element isolation insulating film 4
An interlayer insulating film 16 is formed on the entire upper surface of the substrate. The interlayer insulating film 16 is electrically connected to the N ⁺ type source diffusion layer 11, the N ⁺ type drain diffusion layer 12, the N ⁺ type source diffusion layer 13, the P ⁺ type drain diffusion layer 14, and the P ⁺ type source diffusion layer 15. Contact holes 31 to 35 are formed.

Although not shown, contact holes for establishing electrical continuity with the gate electrodes 9a to 9c are formed in the interlayer insulating film 16, and aluminum wirings extend into these contact holes. Then, an interlayer insulating film is formed on the upper surface, and a via hole for establishing electrical conduction with the aluminum wiring is formed in the interlayer insulating film. An aluminum wiring extends in the via hole, and an interlayer insulating film is formed on the entire upper surface. Thus, the semiconductor memory device is finally configured.

Next, a method of forming the semiconductor memory device shown in FIG. 1 will be described. First, the P-type silicon substrate 1 is oxidized in a wet O ₂ atmosphere to form a silicon oxide film of about 1000 ° C. Then, phosphorus and boron are ion-implanted into regions to be N-type wells and P-type wells. afterwards,
Heat treatment forms N-type well diffusion layer 2 and P-type well diffusion layer 3.

Thereafter, the silicon oxide film is removed with hydrofluoric acid, and oxidized again to form a silicon oxide film of about 400 ° C., and then a silicon nitride film of about 150 ° C. is formed by CVD.
0 ° is formed. Then, photolithography etching is performed to remove the silicon nitride film and the silicon oxide film in a portion to be an element isolation region. When oxidation is performed in a wet O ₂ atmosphere, an oxide film grows in the removed portion, and an element isolation region is formed. Oxide film 4 is formed at about 9000 °.

Next, the above-mentioned silicon nitride film is removed with heated phosphoric acid, and the above-mentioned silicon oxide film is removed with hydrofluoric acid. Thereafter, oxidation is performed in a wet O ₂ atmosphere to form a gate oxide film 5 of the nonvolatile memory element 70 to 30.
An oxide film of 0 ° is formed on the entire surface. Then, the first polycrystalline silicon film (polysilicon film) is
After the formation, the first polycrystalline silicon film other than the non-volatile memory portion M is removed by photolithography etching to leave the first polycrystalline silicon film of the non-volatile memory portion M. Thereafter, the oxide film 5 in the active region other than the nonvolatile memory unit M is removed with hydrofluoric acid.

Further, oxidation is performed in a dry O ₂ atmosphere,
Gate oxide films 6a, 6b and 250-350 of MOS transistors of peripheral logic circuit portion L of 150-200 °
The interlayer oxide film 8 is formed at the same time. Then, a second polycrystalline silicon film is formed at a thickness of about 4000 ° by the CVD method. Thereafter, the gate of the nonvolatile memory element is patterned by photolithography, and the nonvolatile memory M
Of the second polycrystalline silicon film, the interlayer oxide film 8 and the first
Is simultaneously removed by dry etching. Thus, a gate electrode 9c serving as a control gate and a gate electrode 7 serving as a floating gate of the nonvolatile memory element are formed.

Next, unnecessary portions of the second polycrystalline silicon film formed on the peripheral logic circuit portion L are removed by photolithography etching, and gate electrodes 9a and 9b of MOS transistors in the peripheral logic circuit portion L are removed. To form Then, the N-type impurity As is selectively applied to the drain and the source of the nonvolatile memory element by photolithography.
(Arsenic) is ion-implanted. Thereafter, heat treatment is performed in an N ₂ atmosphere to form a drain diffusion layer 10 and a source diffusion layer 11 of the nonvolatile memory element.

Then, an N-type impurity As is selectively ion-implanted into the drain and source of the N-channel transistor in the peripheral logic circuit portion L by photolithography, and a P-type impurity B (selectively) is selectively implanted into the drain and source of the P-channel transistor. Boron) is ion-implanted.
Thereafter, an interlayer insulating film (BPSG film) 16 is formed by CVD.
Is formed at about 7000 °. Then, heat treatment is performed in an N ₂ atmosphere to form a drain diffusion layer 12 and a source diffusion layer 13 of the N-channel transistor in the peripheral logic circuit portion and a drain diffusion layer 14 of a P-channel transistor in the peripheral logic circuit portion.
The source diffusion layer 15 is formed.

Next, predetermined portions of the interlayer insulating film 16 are removed by photolithography and etching to form contact holes 31 to 35. In the photolithography step, first, a photoresist 18 is formed as shown in FIG.
Then, a mask 17 having a hole in a predetermined portion as shown in FIG.
Is disposed on the photoresist 18 and a predetermined portion of the photoresist 18 is resolved by light exposure.

In this embodiment, the mask size B of the nonvolatile memory M is larger than the mask size A of the peripheral logic circuit L as shown in FIG. Specifically, the mask size A is set to 0.65 μm, and the mask size B is set to a size larger than the mask size A by 0.05 to 0.1 μm. In the case of this example, the plane shape of the light transmitting portion of the mask 17 is a square, and the mask dimension is defined by the length of one side.

When two layers of gate electrodes (7, 9c) are used for the gate of the nonvolatile memory element, the contact dimensions C and D of the contact holes (31 to 35) are formed to be the same. FIG. 4 shows the relationship between the mask dimension (A) on the peripheral logic circuit element and the mask dimension (B) on the nonvolatile memory element. As shown in the drawing, when the mask dimensions A and B are about 0.73 μm or more, the contact dimensions C and C are obtained by forming the contact holes 31 to 35 when the mask dimension A and the mask dimension B are 1: 1. The contact dimension D becomes the same size.

However, the mask dimensions A and B are about 0.73 μm.
If it is less than m, the contact dimensions C and D after forming the contact holes 31 to 35 will not be the same if the mask dimension A and the mask dimension B are 1: 1. As shown in FIG. 4, if the mask dimension B is larger than the mask dimension A by a predetermined dimension, the contact dimensions C and D can be formed in the same size.

Therefore, when the mask size A is 0.65 μm as shown in FIG.
If the dimension is larger by 5 to 0.1 μm, for example, about 0.705 μm, the contact holes 31 to 35 can be formed in the same size. However, also in this example, as in the related art, the focus is on the peripheral logic circuit section L, and thus the non-volatile memory section M is not on focus. However, since the mask dimension B is large even if the resolution is difficult to achieve, the size of the photoresist 18 formed afterward is such that the size of the contact hole 31 formed thereafter is the same as the size of the contact holes 32-35. Can be removed.

As described above, since the contact holes 31 to 35 of the peripheral logic circuit portion L and the nonvolatile memory portion M can be formed in the same size, the contact holes of the peripheral logic circuit portion L and the nonvolatile memory portion M can be formed. The resistance can be the same. In addition, since the contact hole 31 of the nonvolatile memory portion M is also sufficiently formed,
A margin similar to that of the peripheral logic circuit section L can be obtained. Further, the same effect can be obtained even if each element formed in the semiconductor memory device is miniaturized.

At the same time as the contact holes 31 to 35, contact holes for establishing electrical continuity with the gate electrodes 9a to 9c are also formed. After that, aluminum wiring is patterned and formed in these contact holes. Then, an interlayer insulating film is further formed on the upper surface, and a via hole for establishing electrical conduction with the aluminum wiring is formed in the interlayer insulating film. After patterning and forming an aluminum wiring in this via hole, an interlayer insulating film is formed on the entire upper surface, and the semiconductor memory device is completed.

A refractory metal polycide film or a refractory metal silicon side in which a refractory metal film of titanium, molybdenum, tungsten or the like is formed on gate electrodes 9a to 9c formed of a polycrystalline silicon film serving as a control gate. Films can also be formed to reduce gate resistance. Further, in this example, a thermal oxide film was used as an interlayer film between the first layer polycrystalline silicon film and the second layer polycrystalline silicon film.
An ONO film (oxide film, nitride film, oxide film) may be used.

In the present embodiment, a two-layer crystal silicon gate structure is used for the gate of the nonvolatile memory section M, but a multi-layer crystal silicon gate structure having three or more layers may be used.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor memory device according to an embodiment of the present invention after forming contact holes 31 to 35;

FIG. 2 is a cross-sectional view when a predetermined portion of the photoresist 18 is removed by exposure and a predetermined portion of the photoresist 18 is removed by exposure in FIG.

FIG. 3 is a cross-sectional view when a mask 17 is arranged on a photoresist 18 in a photolithography process.

FIG. 4 is a correlation diagram showing a mask dimension A and a mask dimension B when the contact holes 31 to 35 to be formed have the same size.

FIG. 5 is a cross-sectional view after formation of conventional contact holes 31-35.

FIG. 6 is a cross-sectional view when a mask 17 is conventionally arranged on a photoresist 18 and a predetermined portion of the photoresist 18 is removed by exposure.

[Explanation of symbols]

M: nonvolatile memory element unit, L: peripheral logic circuit unit,
1 ... semiconductor substrate, 7 ... gate electrode, 9a ... gate electrode,
9b, 9c... Gate electrodes in the peripheral logic section, 16
... interlayer insulating film (BPSG film), 17 ... mask, 18 ... photoresist.

Claims (2)

[Claims] Forming a nonvolatile memory element having a multi-layered gate electrode and a peripheral logic circuit element having a single-layered gate electrode on a semiconductor substrate; Forming an interlayer insulating film (16) on the nonvolatile memory element and the peripheral logic circuit element; and electrically connecting the electrodes of the nonvolatile memory element and the peripheral logic circuit element to the interlayer insulating film (16). Forming a contact hole (31-35) for establishing electrical continuity, wherein the step of forming the contact hole (31-35) comprises: ) Photoresist (1)
8) forming a mask (17) on the photoresist (18), wherein a mask dimension (B) on the nonvolatile memory element is larger than a mask dimension (A) on the peripheral logic circuit element. And etching the photoresist (18) on portions where the contact holes (31-35) are to be formed, and using the photoresist (18) formed by this process to etch the photoresist (18). Contact hole (31
To 35). A method for manufacturing a semiconductor memory device, comprising: 2. A non-volatile memory element having two-layer gate electrodes (7, 9c) and a peripheral logic circuit element having single-layer gate electrodes (9a, 9b) are formed on a semiconductor substrate (1). Forming an interlayer insulating film (16) on the nonvolatile memory element and the peripheral logic circuit element; and forming an electrode of the nonvolatile memory element and the peripheral logic circuit element on the interlayer insulating film (16). Forming a contact hole (31-35) for establishing electrical continuity, wherein the step of forming the contact hole (31-35) comprises: Photo resist (18) on (16)
Forming a mask dimension (B) on the nonvolatile memory element and a mask dimension (A) on the peripheral logic circuit element less than about 0.73 μm on the photoresist (18); A mask (17) having a mask dimension (B) larger than the mask dimension (A) is arranged, and the contact holes (31 to 31) are arranged.
35) on the portion where the photoresist (1) is to be formed.
8) a step of etching, and forming the contact holes (31 to 35) using the photoresist (18) formed in this step.