JPH1056142A - Semiconductor storage element and its forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable writing/reading of information even at a law gate voltage by, with smaller dielectric constant of a ferroelectrics film and smaller remaining polarization ratio of a ferroelectrics film, using a film where c-axis of titanic acid bismuth (BIT) is oriented vertical to the surface of an electrode as a ferroelectrics film. SOLUTION: In order to form a semiconductor storage element containing MFMIS FET, an Pt film is formed on a polycrystal Si film 16 far thermal treatoment, further for crystallizing to form a lower layer film 20a, and an organic solvent of BIT where Ti source and Bi source are dissolved is repeatedly applied, and then sintered far forming upper layer films 20b1 -20b4 . In short, FET comprising, in the order from upper side, an upper part electrode film, a ferroelectrics film 20, a lower part electrode film 18, a gate insulation film 14 and a semiconductor substrate provided, a BIT film with the ferroelectrics film 20 c-axis oriented is obtained. With dielectric constant and remaining polarization ratio of the BIT film with c-axis oriented small, a sufficient electric field is applied to the ferroelectrics film at a low gate voltage, so writing/ reading, etc., of information becomes stable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method for forming the semiconductor memory device.

[0002]

2. Description of the Related Art As an example of a semiconductor memory device using a ferroelectric, an MFMIS type field effect transistor (FE) is used.
T) references: "ISSC95Feb. 1995 Single-Transistor Fer
roelectoric Memory Cell T. Nakamura et.al ". This element is a semiconductor memory element having a structure including an upper electrode film (metal film), a ferroelectric film, a lower electrode film (metal film), a gate insulating film, and a semiconductor substrate (silicon substrate) in order from the upper side. . Hereinafter, the operation of this element will be described assuming that the FET is an N-channel type. After a positive gate voltage V sufficient to invert the polarization of the ferroelectric is once applied to the upper electrode film (also referred to as a control gate) of the FET, the gate voltage is set to 0 again. When the gate voltage is applied in this manner, charges are generated in the lower electrode film (also referred to as a floating gate) due to residual polarization of the ferroelectric,
Therefore, an inversion layer is formed in the channel portion, and thus the FET
Is turned on. Conversely, after a negative gate voltage -V is once applied to the upper electrode film, the gate voltage is set to 0 again. At this time, since the ferroelectrics undergo polarization reversal in the direction opposite to that in the case where a positive gate voltage is applied, no inversion layer is formed in the channel due to the residual polarization of the ferroelectrics.
T is turned off. Therefore, when the gate voltage is 0, the FET can be selectively turned on or off, so that the data once stored can be read by detecting the current between the source and the drain of the FET. .

[0003]

However, in the element having such a structure, a multilayer capacitor in which the capacitance is connected in series by the ferroelectric film and the gate insulating film is formed.
Since the relative dielectric constant of the ferroelectric film is higher than the relative dielectric constant of the gate insulating film, the capacitance of the ferroelectric film becomes larger than the capacitance of the gate insulating film. May be lost. If a sufficient electric field is not applied to the ferroelectric film, the polarization and polarization reversal of the ferroelectric will not be sufficient, so that information cannot be sufficiently written to or read from the semiconductor memory element. If the gate voltage applied to the upper electrode film is increased in order to apply a sufficient electric field to the ferroelectric film, the electric field may be excessively applied to the gate insulating film, and the gate insulating film may be broken down. Further, as the reversal of the polarization is repeatedly performed on the ferroelectric film, the fatigue of the ferroelectric film such that the polarization amount is reduced occurs. It is considered that the occurrence of the film fatigue is caused by oxygen vacancies generated in the ferroelectric film.

Therefore, a field effect transistor (FE) capable of writing and reading information with a low gate voltage is used.
The appearance of a semiconductor memory element composed of T) has been desired. In addition, the appearance of a method for easily forming such a semiconductor storage element has been desired. Further, there has been a demand for a semiconductor memory element capable of suppressing fatigue of a ferroelectric film.

[0005]

Therefore, the inventor of the present application has proposed an MFMIS-type FET capable of sufficiently writing and reading information without increasing the gate voltage applied to the upper electrode film. Of the MFMIS having a ferroelectric film having a small relative dielectric constant and a low remanent polarization value when the following three known facts are well combined. It has been concluded that a FET of the type can be formed and thus this FET can be used as a semiconductor storage element.

In order to apply a sufficient electric field to the ferroelectric film at a low gate voltage, it is necessary to reduce the relative dielectric constant of the ferroelectric film.

In order to apply a sufficient electric field to the ferroelectric film at a low gate voltage, it is necessary to reduce the residual polarization value of the ferroelectric film.

In a bismuth titanate film (hereinafter sometimes referred to as a BIT film), the relative dielectric constant and the remanent polarization value vary greatly depending on the crystal orientation. In particular, bismuth titanate (hereinafter referred to as BIT film) constituting the BIT film When the c-axis is oriented perpendicular to the surface of the electrode, the relative dielectric constant and the remanent polarization value become small.

Therefore, it is conceivable to use a film in which the c-axis of BIT is oriented perpendicular to the surface of the electrode (hereinafter also referred to as a c-axis oriented BIT film) as the ferroelectric film.

[0010] Further, the inventor of the present application discloses the BI
It was also confirmed that the film surface could be made flat by devising the structure of the T film. First, a film made of BIT in which the composition ratio of Bi is larger than the stoichiometric composition of BIT (hereinafter, sometimes referred to as a Bi-rich BIT film), that is, a c-axis oriented BIT film is a lower film. Is provided on the lower electrode film. When a film containing BIT having a stoichiometric composition is provided as it is on the lower electrode film, it does not become a c-axis oriented BIT film. However, the underlayer film described above,
That is, if an upper layer film containing BIT of stoichiometric composition is provided on a c-axis oriented Bi-rich BIT film, the entire film becomes a c-axis oriented BIT film. Further, a film containing BIT with a stoichiometric composition can be formed more flatly than a Bi-rich BIT film. Therefore, a BIT film having c-axis orientation and a flat surface can be obtained as a ferroelectric film. If the surface of the BIT film is flat, the patterning in the FET forming process, specifically, the lithography process after providing the BIT film is easy and accurate. Further, when the BIT film has less irregularities, it is possible to prevent the electric field concentration from occurring only in a thin portion of the BIT film when operating the FET.

Therefore, according to the semiconductor memory element of the present invention, at least a field-effect transistor having a configuration including an upper electrode film, a ferroelectric film, a lower electrode film, a gate insulating film, and a semiconductor substrate is provided in order from the upper side. In the semiconductor memory device provided, the ferroelectric film is a film composed of the following 1) to 3). 1) It is a BIT film. 2) The c-axis of the BIT constituting this film is oriented substantially perpendicular to the upper surface of the lower electrode film (the c-axis oriented BIT film). 3) Lamination of a lower film containing BIT in which the composition ratio of bismuth (Bi) is larger than the stoichiometric composition of BIT, and an upper film of a single layer or a plurality of layers containing BIT of stoichiometric composition It is a BIT film composed of a film.

According to the semiconductor memory device of the present invention, the ferroelectric film is constituted by a BIT film, and the c-axis of bismuth titanate constituting the BIT film is substantially equal to the upper surface of the lower electrode film. Since the ferroelectric film is oriented vertically vertically, the relative dielectric constant and remanent polarization value of the ferroelectric film are reduced. Therefore, it is possible to apply a sufficient electric field to the ferroelectric film with a low gate voltage, and thus it is possible to write and read information with a low gate voltage. BIT is represented as Bi ₄ Ti ₃ O ₁₂ when it has a stoichiometric composition.

Further, this BIT film is made of a Bi-rich BI
This is a BIT film composed of a laminated film of a T film and a single layer or a plurality of upper layers containing BIT having a stoichiometric composition. Therefore, a BIT film having a flat surface can be obtained. Therefore, the BIT composed of the lower film and the upper film
By forming the film, a film having c-axis orientation and being flat can be obtained. Note that the upper layer film can be any one of a single layer and a plurality of layers in consideration of the film thickness and the like.

Next, according to a first method for forming a semiconductor memory device of the present invention, the following steps a) and b) are included in forming the above-described semiconductor memory device.

A) Titanium (Ti) source and bismuth (B)
i) dissolving the source, and using a first coating solution of an organic solvent solution in which the molar ratio of Bi is larger than the molar ratio of Bi to Ti determined from the stoichiometric composition of BIT, Form.

B) dissolving a Ti source and a Bi source,
Using a second coating solution consisting of an organic solvent solution of BIT in a molar ratio determined by a stoichiometric composition, applying the second coating solution on an underlayer film, and then baking it once or more times Thereby, the upper layer film is formed.

Next, according to the second method of forming a semiconductor memory device of the present invention, a ferroelectric film and an upper layer are formed on a base formed by sequentially forming a gate insulating film and a lower electrode film on a semiconductor substrate. In forming the semiconductor memory element by sequentially forming the electrode films, the formation of the ferroelectric film includes the following steps a) and b).

A) a first organic solvent solution in which a titanium source and a bismuth source are dissolved and the molar ratio of bismuth is greater than the molar ratio of bismuth to titanium determined from the stoichiometric composition of bismuth titanate; A lower layer film is formed using a coating solution.

B) Using a second coating solution comprising an organic solvent solution of bismuth titanate in a molar ratio determined by a stoichiometric composition, in which a titanium source and a bismuth source are dissolved, An upper layer film is formed on the lower layer film by repeating application and baking once or more times.

In the first and second methods for forming a semiconductor memory device according to the present invention, the lower film and the upper film formed thereon are formed by forming the lower film.
An axially oriented BIT film can be used. In addition, since the above-mentioned upper layer film is formed on the lower layer film using a second coating solution composed of an organic solvent solution of BIT in a molar ratio determined by the stoichiometric composition, a c-axis oriented and flat BIT film is formed. Can be formed.

Here, the organic solvent solution is a solution using a solvent as an organic solvent. Further, as a Ti source and a Bi source, any suitable Ti compound soluble in an organic solvent and B
An i compound may be used.

According to the first and second methods for forming a semiconductor memory device of the present invention, the BIT film
To easily form a semiconductor storage element including an FET having a ferroelectric film in which the BIT of the BIT constituting the film is oriented substantially perpendicular to the upper surface of the lower electrode film. Can be. That is, a semiconductor memory element including an MFMIS-type FET that can apply a sufficient electric field to the ferroelectric film with a low gate voltage can be easily formed. In addition, since the surface of the BIT film can be formed flat, the subsequent FET formation process can be performed easily and accurately, and electric field concentration occurs in a part of the BIT film which is a ferroelectric film. Can be prevented.

The inventor of the present invention has made intensive studies, and as a result, has a lower film including a c-axis oriented Bi-rich BIT film and an upper film including a stoichiometric BIT film. It has been found that a ferroelectric film, which is slightly inferior to the ferroelectric film in c-axis orientation and can be sufficiently used for a semiconductor device, can be formed of a Bi-rich BIT film.
If a ferroelectric film can be formed from a Bi-rich BIT film, the number of steps is reduced, and easier manufacture is possible.

Therefore, according to the semiconductor memory device of the present invention, at least a field effect transistor having a configuration including an upper electrode film, a ferroelectric film, a lower electrode film, a gate insulating film, and a semiconductor substrate is provided in order from the upper side. The ferroelectric film is characterized in that the film is composed of the following 1) to 3). 1) It is a BIT film. 2) The c-axis of the BIT constituting this film is oriented substantially perpendicular to the upper surface of the lower electrode film. 3) Bi for Ti determined from stoichiometric composition of BIT
BiT in which the composition ratio of Bi is larger than the molar ratio of
Is a film composed of a single layer or a plurality of layers containing

According to the semiconductor memory element of the present invention, the ferroelectric film is constituted by the BIT film, and the c-axis of the BIT constituting the BIT film is substantially equal to the upper surface of the lower electrode film. Since the ferroelectric film is oriented vertically, the relative dielectric constant and the remanent polarization value of the ferroelectric film are reduced. Therefore, it is possible to apply a sufficient electric field to the ferroelectric film with a low gate voltage, and thus it is possible to write and read information with a low gate voltage. BIT is represented as Bi ₄ Ti ₃ O ₁₂ when it has a stoichiometric composition.

This BIT film is made of a Bi-rich BI
It is a BIT film composed of a single layer or a plurality of layers including a T film. This film has a slightly lower flatness than a film composed of a lower film including a Bi-rich BIT film and an upper film including a stoichiometric BIT film, but is used as a ferroelectric film of a semiconductor memory device. The film has a flat surface so that it can be used. Therefore, by forming the ferroelectric film as a BIT film composed of a single layer or a plurality of layers, a c-axis oriented and flat film can be obtained. Note that any one of a single layer and a plurality of layers can be used in consideration of the film thickness and the like for use as the ferroelectric film.

Preferably, in the semiconductor memory device, the lower electrode film is a Pt (platinum) film.

By using Pt for the lower electrode film,
An electrode which can withstand, for example, high-temperature treatment in an oxygen atmosphere in a process of forming a semiconductor memory element, that is, has excellent heat resistance and oxidation resistance can be obtained.

Preferably, the lower electrode film is a film composed of a RuO ₂ (ruthenium oxide) film on the upper side and a Ru (ruthenium) film on the lower side.

Since this RuO ₂ film is in contact with the ferroelectric film as a conductive oxide film, it supplements oxygen which is deficient in the ferroelectric film, thereby suppressing film fatigue and improving the fatigue characteristics of the ferroelectric film. It is thought that it is possible. In addition, when the two-layer film is used, when a semiconductor memory element is formed, etching can be performed simultaneously with films other than the lower electrode film.

Preferably, when the lower electrode film is made of a RuO ₂ (ruthenium oxide) film on the upper side and a Ru (ruthenium) film on the lower side, the lower electrode film and the bismuth titanate film are formed. It is preferable to further provide a flattening film containing bismuth titanate having a stoichiometric composition.

The surface of the lower electrode film composed of the RuO ₂ film and the Ru film can be made flat by the film containing BIT having the stoichiometric composition. Therefore, the ferroelectric film provided above the lower electrode film can be formed more flat.

Preferably, when the lower electrode film is a film composed of a RuO ₂ (ruthenium oxide) film on the upper side and a Ru (ruthenium) film on the lower side, the lower electrode film and the titanic acid Between the bismuth film and the bismuth titanate, it is preferable to further provide a planarizing film containing bismuth titanate in which the composition ratio of titanium to the stoichiometric composition of bismuth titanate is increased.

With this film, the surface of the lower electrode film can be made flat, and the ferroelectric film provided thereon can be made more flat. Further, since the flattening film is a film containing BIT in which the composition ratio of Ti is increased, an effect of reducing the leak current of the ferroelectric film can be expected.

Next, in order from the upper side, the semiconductor memory element having at least the field-effect transistor having the structure including the upper electrode film, the ferroelectric film, the lower electrode film, the gate insulating film, and the semiconductor substrate, The ferroelectric film is a bismuth titanate film, wherein the c-axis of bismuth titanate constituting the film is oriented substantially perpendicular to the upper surface of the lower electrode film, A semiconductor storage element is formed as the bismuth titanate film including a single layer or a plurality of layers containing bismuth titanate in which the composition ratio of bismuth to titanium is larger than the molar ratio of bismuth to titanium determined from the stoichiometric composition. The method comprises dissolving a titanium source and a bismuth source, and calculating the molar ratio of bismuth from the molar ratio of titanium to titanium determined from the stoichiometric composition of the bismuth titanate. The bismuth titanate film is formed by repeating, once or more than once, using a coating solution composed of an organic solvent solution having a higher ratio, and applying the coating solution on the lower electrode film and then firing the coating solution one or more times. Preferably, a forming step is included.

In the method of forming a semiconductor memory element by forming a ferroelectric film and an upper electrode film sequentially on a base formed by forming a gate insulating film and a lower electrode film on a semiconductor substrate sequentially. The method of forming a ferroelectric film is a method in which a titanium source and a bismuth source are dissolved, and an organic solvent solution in which the molar ratio of bismuth is larger than the molar ratio of titanium determined from the stoichiometric composition of bismuth titanate. It is preferable that the method further includes a step of forming the bismuth titanate film by repeating once or plural times applying the coating solution on the lower electrode film after using the coating solution composed of

According to such a method for forming a semiconductor element, the BIT film is formed such that the c-axis of the BIT constituting the film is substantially perpendicular to the upper surface of the lower electrode film. The number of steps of the ferroelectric film can be reduced. Therefore, the FE having the ferroelectric film as described above
A semiconductor storage element containing T can be easily formed. That is, a semiconductor storage element including an MFMIS-type FET that can apply a sufficient electric field to the ferroelectric film with a low gate electrode can be easily formed. In addition, since the surface of the BIT film can be formed flat, subsequent formation steps can be performed easily and accurately, and electric field concentration can be prevented from being generated in a part of the BIT film.

Preferably, in the semiconductor memory element, the lower electrode film is formed on the upper side and IrO ₂ (iridium oxide) is formed on the upper side.
It is preferable to use a film composed of two layers of a film and an Ir (iridium) film on the lower side.

Since this IrO ₂ film is in contact with the ferroelectric film as a conductive oxide film, the film is supplemented with oxygen which is deficient in the ferroelectric film similarly to the RuO ₂ film, thereby suppressing the film fatigue and improving the fatigue characteristics. Is considered to be able to be improved. In addition, when the two-layer film is used, when a semiconductor memory element is formed, etching can be performed simultaneously with films other than the lower electrode film. Furthermore, by using an electrode film composed of these two layers, an electrode (film) that can withstand, for example, processing in a high-temperature oxygen atmosphere in the process of forming a semiconductor memory element, that is, has excellent heat resistance is obtained. Can be Further, it is possible to prevent mutual diffusion between the ferroelectric film and the electrode, that is, to obtain an electrode having excellent barrier properties.

Preferably, in the semiconductor memory element, the lower electrode film is formed on the upper side, and IrO ₂ (iridium oxide) is formed on the upper side.
When the film and the lower side are made of two layers of Ir (iridium) film, the upper electrode film is preferably made of IrO ₂ (iridium oxide) film.

Thus, since the upper and lower electrodes sandwiching the ferroelectric film are made of the same material (IrO ₂ ), the ferroelectric hysteresis is not affected by the work function difference between the two electrodes.

Further, in the semiconductor memory device, the lower electrode film is made of an IrO ₂ (iridium oxide) film on the upper side, and the lower electrode film is made on the lower side.
When a film composed of two layers of an r (iridium) film is used,
Between the lower electrode film and the bismuth titanate film, a flattening film containing bismuth titanate having a stoichiometric composition,
Alternatively, a flattening film containing bismuth titanate in which the composition ratio of titanium with respect to the stoichiometric composition of bismuth titanate may be further provided.

By providing these flattening films, the surface of the lower electrode film can be flattened. Therefore, the ferroelectric film provided above the lower electrode film can be formed more flat.

Further, the ferroelectric film formed on the lower electrode film composed of the IrO ₂ film and the Ir film is different from the lower film containing BIT obtained by using a Bi-rich coating solution in stoichiometry. It may be a film composed of an upper layer film containing BIT having a composition, or a film composed of a single layer or a plurality of layers of a Bi-rich BIT film.

[0045]

Embodiments of the present invention will be described below with reference to the drawings. Numerical conditions such as used materials and their amounts, processing time, processing temperature, and film thickness, which are mentioned in the following description, are merely preferred examples within the scope of the present invention. Therefore, these inventions are not limited only to these conditions. In the drawings, hatching indicating a cross section is omitted except for a part.

<First Embodiment> FIGS. 1 to 4 show an MF
First of a semiconductor memory device including a MIS type FET,
It is a schematic sectional view (however, a figure of a cut end) which shows a manufacturing process in an embodiment. Here, only a portion corresponding to the active region of the semiconductor memory element is shown.

When a semiconductor memory device including an MFMIS-type FET is formed, first, a known technique is applied to a predetermined region of an n-type silicon substrate (hereinafter sometimes referred to as an n-Si substrate) 10. To form a field oxide film made of SiO ₂ (not shown). Through the surface of the n-Si substrate 10 where no field oxide film is provided,
P-type impurities are ion-implanted. Although not limited to this, boron (B) can be used as the p-type impurity. Thereafter, the p-type impurity is diffused by a high-temperature heat treatment to form the p-type well layer 12. Next, on the p-type well layer 12, Si
A gate insulating film (gate oxide film) 14 made of O ₂ is formed to a thickness of about 60 ° by, for example, thermal oxidation. The thermal oxidation includes, but is not limited to, a rapid heating device (hereinafter, RTA).
In some cases. ) Can be used. next,
A polycrystalline Si film 16 is formed on the field oxide film and the gate insulating film 14 by using SiH ₄ (monosilane) gas and PH.
The ₃ (phosphine) pressure CVD method using a gas, after forming a thickness of about 2000 Å, phosphorus at a temperature of 850 ℃ 4 × 10 ²⁰ by diffusing approximately ions cm ^-3, the conductivity of the polycrystalline Si film 16 obtain. Next, a Pt film having a thickness of about 1000 ° is formed on the polycrystalline Si film 16 by a sputtering method, and is used as a lower electrode film 18 (FIG. 1A).

Next, a ferroelectric film 20 made of a BIT film is formed on the lower electrode film 18. In this case, first, Ti
An organic solvent solution is prepared in which the source and the Bi source are dissolved and the molar ratio of Bi is larger than the molar ratio of Bi to Ti determined from the stoichiometric composition of BIT. BI
The molar ratio of Bi and Ti determined from the stoichiometric composition of T is Bi: Ti = 4: 3. Therefore, the molar ratio of Bi and Ti in the organic solvent solution is, for example, Bi: Ti =
The one of 4.4: 3 is suitable as the organic solvent solution here. The range of the molar ratio is set to Bi: Ti = 4.0.
When the ratio is about 8: 3 to 4.8: 3, the BI oriented to the c-axis is
A T film is obtained. Further, more preferable BI of c-axis orientation
To obtain a T film, the molar ratio range should be Bi: Ti = 4.2.
4: 3 to 4.6: 3 is preferable. Such a solution is obtained from Biological Chemistry Laboratory Co., Ltd. or the like as a “solution for forming bismuth titanate (BIT) by an organometallic decomposition method (sometimes referred to as a MOD method).” It can be purchased in molar ratio.

Then, the lower electrode film 18 is spin-coated using this solution as a first coating solution. for that reason,
This first coating liquid is dropped on the lower electrode film 18, and immediately thereafter, the n-Si substrate 10 is rotated at 500 rpm for 10 seconds and further at 2500 rpm for 30 seconds to form a coating film. Then, to remove the solvent from the coating film, 450
Baked at 850 ° C. for 3 minutes in dry oxygen using RTA (final calcination) to crystallize, for example, a BIT film having a thickness of 600 °, that is, lower film 2
0a is formed (FIG. 1B). The lower film 20a is a BIT film in which the c-axis of the BIT constituting the film is oriented substantially perpendicular to the upper surface of the lower electrode film 18, that is, the BIT film oriented in the c-axis. Also, this film is made of BI
It comprises BIT in which the composition ratio of Bi is larger than the stoichiometric composition of T. The BIT film oriented in the c-axis can be formed in the same manner by heat-treating the calcined film at 850 ° C. for 30 minutes in dry oxygen using a normal electric furnace.

Next, a second coating solution is prepared which comprises a solution of BIT in an organic solvent in which the Ti source and the Bi source are dissolved and whose molar ratio is determined by the stoichiometric composition. Then, the second coating solution is spin-coated on the lower layer film 20a. Therefore, the second coating solution is dropped on the lower layer film 20a to form n-Si
The substrate 10 is kept at 500 rpm for 10 seconds and further 2500 rpm.
After spinning at pm for 30 seconds to form a coating film and pre-baking at 450 ° C. for 15 minutes, main baking is performed at 850 ° C. for 3 minutes using RTA to form a _first upper layer film 20b1 (FIG. 1 (C)). The process from the formation of the coating film using the second coating solution to the preliminary baking and the main baking is further performed three times, for a total of four times, and the second, third, and fourth upper films 2 are formed.
Ob ₂ , 20b ₃ , and 20b ₄ are formed. Thus, a BIT film having a thickness of about 3000 °, that is, an upper film 20b is formed (FIG. 1D). This lower layer film 20a
And the upper film 20b are collectively referred to as a ferroelectric film 20. In the following figures, the films 20b ₁ , 20b ₂ , 20b ₃ , and 20b ₄ are omitted from the illustration of the upper film 20b only (FIG. 2A).

Next, an upper electrode film 22 made of a Ru film is formed on the ferroelectric film 20 (FIG. 2B). In this case, an upper electrode film 22 having a thickness of, for example, 2000 Å is formed on the ferroelectric film 20 by a sputtering method.

Next, these films 2 are formed on the upper electrode film 22.
After forming an SiO ₂ film 24 (FIG. 2C) to form a mask for patterning 0a, 20b and 22, a resist is applied, and a photolithography technique is used to form a desired FET size. A resist pattern is formed (not shown). Then, using the resist pattern as a mask, the SiO ₂ film 24 is etched to remove unnecessary portions, thereby obtaining a patterning mask 24x. Thereafter, the lower film 20a and the upper film 20 are adjusted in accordance with the patterning mask 24x.
b, and unnecessary portions of the upper electrode film 22 are removed by etching (FIG. 3A). In this case, unnecessary portions of these films 20a, 20b and 22 are removed by dry etching using a chlorine-based or fluorine-based gas as an etching gas. For the etching, a reactive ion etching apparatus (hereinafter referred to as R
It may be referred to as an IE device. ) Can be used. In particular, when a magnetron type RIE device is used,
The etching rate is improved. In the drawing, 20ax is the etched lower layer film, 20bx is the etched upper layer film, 20x is the etched ferroelectric film, and 22x is the etched upper electrode layer. Each of the films is shown.

Next, the etched film 20ax,
Using 20bx and 22x as masks, an unnecessary portion of the lower electrode film 18 made of a Pt film is removed by ion milling and patterned into a desired shape (FIG. 3B). In the figure, reference numeral 18x denotes a patterned lower electrode film that remains. At this time, the patterning mask 24x has been thinned by etching.

Next, these films 18x, 20ax, 20x
Using the bx and 22x as masks, unnecessary portions of the gate insulating film 14 and the polycrystalline Si film 16 are removed using an RIE apparatus.
Dry etching with a chlorine-based or fluorine-based gas is performed to remove. At this time, the patterning mask 24x is completely removed (FIG. 3C). In the figure,
14x is a gate insulating film remaining after etching, 16
x is the remaining etched polycrystalline Si film.

Next, the entire device is covered with a low-temperature CVD oxide film (hereinafter sometimes referred to as LTO) (not shown). Then, this LTO is anisotropically etched to obtain S
A sidewall 26 made of iO ₂ is formed (FIG. 4A). Anisotropic etching includes, but is not limited to, R
An IE device can be used.

Next, the source 28a and the drain 28b are formed by ion-implanting an n-type impurity (FIG. 4B). The n-type impurities include, but are not limited to, arsenic (A
s) or antimony (Sb) can be used.

Next, the entire device is covered with an interlayer insulating film (not shown). Then, using a known technique, the source 2
6 and contact hole 3 exposing drain 28
0 is formed. In the figure, reference numeral 32 denotes an interlayer insulating film remaining after the formation of the contact hole 30. Thereafter, a W buried layer 34 is formed in the contact hole 30 by a selective tungsten (W) CVD method. Finally, if necessary, metal wiring is formed. Here, aluminum (A
After l) is formed on the entire surface by a sputtering method (not shown), photolithography and etching using an RIE apparatus are performed to form an Al wiring 36 (FIG. 4C).
As described above, a semiconductor memory element including an MFMIS-type FET is formed.

The semiconductor memory device thus formed has, in order from the upper side, an F having a configuration including an upper electrode film, a ferroelectric film, a lower electrode film, a gate insulating film, and a semiconductor substrate.
The ferroelectric film is made of ET (here, an MFMIS type FET), and the ferroelectric film is a BIT film oriented in the c-axis. Since the relative dielectric constant and the remanent polarization value of the BIT film oriented in the c-axis are small, when this element is operated, a sufficient electric field is applied to the ferroelectric film composed of the BIT film at a low gate voltage. As a result, stable operations such as writing and reading of information can be performed with a low gate voltage.

Here, when the ratio of Bi to Ti in the organic solvent solution is Bi: Ti = 4.4: 3 as a coating liquid, the hysteresis characteristic of the BIT film formed by the above-mentioned spin coating method is shown. Examined. However, as a sample for hysteresis characteristic measurement, the p-type Si substrate, an SiO ₂ film having a thickness of 2000Å was formed by thermal oxidation, further the SiO ₂
A Pt film having a thickness of 600 ° is formed on the film by a sputtering method as a base, and a BIT film is formed on the base,
Further, a 2,000-mm-thick ruthenium (Ru) film was formed on the BIT film. The hysteresis characteristics were measured using a Pt film and a Ru film as electrodes and using a well-known technique using a Sawyer tower circuit. Considering the difference in work function between Pt and Ru, a substantial remanent polarization value was found to be about 1.8 (μC / cm ² ). The relative dielectric constant was 67 and the coercive electric field was about 12 (kV / cm).
The dielectric constant of lead titanate (PZT) generally used as a ferroelectric film is 875, and the remanent polarization value is 2
5.4 (μC / cm ² ), and the coercive electric field was 57.5 (k
V / cm) (see the 1995 Spring Applied Physics Conference proceedings, second volume 30p-D-16, p492), the molar ratio of Bi and Ti in the organic solvent solution is Bi: Ti =
BIT formed using 4.4: 3 as coating solution
It can be understood that the relative permittivity, the remanent polarization value, and the coercive electric field of the film, that is, the BIT film oriented in the c-axis, are all sufficiently low. Therefore, when the BIT film is used as a ferroelectric film of a semiconductor memory element composed of an FET, a sufficient electric field can be applied to the ferroelectric film with a low gate voltage. Furthermore, since the coercive electric field is small, the gate voltage required to saturate the hysteresis characteristics is reduced, and the gate oxide film is less likely to be destroyed.

In order to confirm the flatness of the surface of the ferroelectric film 20 formed by the method of the first embodiment, a ferroelectric film 20 formed on an underlayer was used as a first sample.
Further, a ferroelectric film consisting of only a Bi-rich BIT film formed on an underlayer was used as a second sample, and the surfaces of the first and second samples were measured using a scanning electron microscope (SEM). Photos were taken at 10,000 times magnification and compared. As a result, it was confirmed that the first sample according to the present invention was clearly flatter than the second sample.

FIG. 5 is a model diagram of a cross section of a first sample (FIG. 5A) and a second sample (FIG. 5B). The first sample has a flatter surface than the second sample. For this reason, it can be understood that in a semiconductor memory device using the ferroelectric film 20 formed by the method for forming a semiconductor memory device of the present invention, electric field concentration hardly occurs in a part of the ferroelectric film during operation.

<Second Embodiment> A second embodiment is basically the same as the first embodiment except that the lower electrode film 18 is formed on the upper side and a RuO ₂ (ruthenium oxide) film is formed on the upper side. ,
The lower side is a film composed of two layers of Ru (ruthenium) film.

FIGS. 6A and 6B are schematic cross-sectional views (however, cutaway views) for describing the configuration and the method of forming the semiconductor memory element according to the second embodiment. 2 shows a part of a process of forming a semiconductor storage element.

The steps up to the step of forming the polycrystalline Si film 16 are the same as in the first embodiment. Then, the polycrystalline Si film 1
6 by sputtering, for example, a Ru film having a thickness of 500 °
A film 18a is formed, and a RuO ₂ film 18b having a thickness of, for example, 1000 ° is formed on the Ru film by a sputtering method. Next, a ferroelectric film 20 and an upper electrode film 22 are sequentially formed on the RuO ₂ film 18b by the same method as in the first embodiment (FIG. 6A). As described above, since the oxide film (RuO ₂ film 18b) is in contact with the ferroelectric film 20, oxygen can be supplied to the ferroelectric film to supplement oxygen vacancies in the film. As a result, it is possible to suppress the film fatigue and improve the fatigue characteristics. Further, providing the Ru film 18a between the polycrystalline Si film 16 without directly forming the RuO ₂ film prevents oxidation of the polycrystalline Si film,
This is for improving the adhesion between the film 16 and the RuO ₂ film.

Here, the Ru film 18a and the RuO ₂ film 1
8b does not need to be processed by ion milling like the Pt film in the first embodiment, and like the upper electrode film 22, the ferroelectric film 20, the polycrystalline Si film 16, and the gate insulating film 14, Dry etching can be performed using a chlorine-based or fluorine-based etching gas. Therefore, all of these films 14, 16, 18a, 18b, 2
Dry etching is simultaneously and collectively performed on all of the films 0 (20a, 20b) and 22 (FIG. 6B). For this reason, the process is simplified. Further, since a finer pattern can be formed as compared with a method including a patterning step by ion milling, miniaturization of an element can be expected. In the figure, 18ax indicates the remaining Ru film, and 18bx indicates the remaining RuO ₂ film.

The other manufacturing steps, effects, and the like are the same as those in the first embodiment, and a detailed description thereof will be omitted.

<Third Embodiment> In the third embodiment, as in the second embodiment, the lower electrode film 18 is formed of a RuO ₂ film 18b on the upper side and a Ru film 18a on the lower side. And a flattening film containing stoichiometric bismuth titanate is further provided between the lower electrode film 18 and the ferroelectric film 20. This is R
The lower electrode film composed of the u film and the RuO ₂ film
Compared with the lower electrode film composed of t, there is substantially no problem, but since the surface is rough, it is provided for the purpose of alleviating this.

FIGS. 7A and 7B are schematic cross-sectional views (excluding cutaways) for explaining the configuration and the method of forming the semiconductor memory element according to the third and fourth embodiments described later. FIG. 2) shows a part of the process of forming the semiconductor memory element.

Here, as shown in the second embodiment, after the lower electrode film 18 composed of the Ru film 18a and the RuO ₂ film 18b is formed, the BIT having a molar ratio determined by the stoichiometric composition is obtained. A coating solution composed of an organic solvent solution is applied on the lower electrode film 18 and baked. This forms a flat BIT film that is not oriented along the c-axis.
This is used as a flattening film 19. After that, BIT having a large Bi composition ratio is fired to form a BIT film having a c-axis orientation, and then one or several BIT films having a stoichiometric composition are formed. Here, as in the first embodiment, four BIT films having a stoichiometric composition were formed, and the ferroelectric film 20 was obtained. Thereafter, an upper electrode film 22 is formed on the ferroelectric film 20 (FIG. 7A). Next, as in the second embodiment, the upper electrode film 22, the ferroelectric film 20 (20a, 20b), the flattening film 19, and the lower electrode film 18 (18a, 18a) are formed by photolithography and dry etching. 18b), polycrystalline S
The i film 16 and the gate insulating film 14 are all patterned simultaneously (FIG. 7B). In the figure, 19x is
2 shows a patterned planarizing film.

For this reason, the lower electrode film 18 is made of a Ru film and a Ru film.
In the case where the ferroelectric film 20 is composed of the O ₂ film, the ferroelectric film 20 can be formed more flat.

The other manufacturing steps, effects, and the like are the same as those of the first and second embodiments, so that detailed description will be omitted.

<Fourth Embodiment> A fourth embodiment is directed to a flattening film 19 (19x) according to the third embodiment.
Is a film containing BIT in which the composition ratio of Ti with respect to the stoichiometric composition of BIT is increased (hereinafter, referred to as a film containing BIT).
This film is also called a Ti-rich BIT film. ).

Here, as shown in the second and third embodiments, after the lower electrode film 18 composed of the Ru film 18a and the RuO ₂ film 18b is formed, the Ti source and the Bi source are dissolved. , A coating solution composed of an organic solvent solution in which the molar ratio of Ti is larger than the molar ratio of Ti to Bi determined from the stoichiometric composition of BIT is applied to the lower electrode film 18.
Apply on top and bake. As a result, the planarizing film 1 which is not oriented in the c-axis but is a flat BIT film is formed.
9 is formed. After that, BIT having a large Bi composition ratio is fired to form a BIT film having a c-axis orientation, and then one or several BIT films having a stoichiometric composition are formed. here,
As in the first embodiment, a BIT film having a stoichiometric composition
A layer was formed, and a ferroelectric film 20 was obtained. Then, an upper electrode film 22 is formed on the ferroelectric film 20 (FIG. 7A), and the upper electrode film 22 and the ferroelectric film are formed by photolithography and dry etching as in the second embodiment. Membrane 20
(20a, 20b), flattening film 19, lower electrode film 1
8 (18a, 18b), the polycrystalline Si film 16, and the gate insulating film 14 are all simultaneously patterned.

For this reason, as in the third embodiment, when the lower electrode film 18 is composed of the Ru film and the RuO ₂ film, the ferroelectric film 20 can be formed more flat. Further, by using the Ti-rich BIT film as the flattening film, an effect of reducing the leak current of the ferroelectric film can be expected.

The other manufacturing steps, effects, and the like are the same as those of the first, second, and third embodiments, and therefore, detailed description is omitted.

<Fifth Embodiment> In a fifth embodiment, the ferroelectric film composed of the BIT film of the first embodiment is formed by changing the composition ratio of Bi to the stoichiometric composition of BIT. BIT composed of multiple layers including increasing BIT
An example of a film will be described with reference to the drawings. FIG. 8 is a schematic diagram showing a part of a main semiconductor memory element forming process in the description of the fifth embodiment, which is shown by a cross-sectional cut at each process stage.

First, as in the first embodiment, n
-A p-type well layer 12, a gate insulating film 14, a polycrystalline Si film 16, and a lower electrode film 18 are sequentially formed on the Si substrate 10 (FIG. 8A).

After that, a ferroelectric film containing BIT is formed on the lower electrode film 18. In this case, first, an organic solvent in which the Ti source and the Bi source are dissolved and the molar ratio of Bi is larger than the molar ratio of Bi to Ti determined from the stoichiometric composition of BIT is prepared. The molar ratio of Bi and Ti determined from the stoichiometric composition of BIT is Bi: T
i = 4: 3. In this example, Bi in the organic solvent solution
A solution in which the molar ratio between Ti and Ti is, for example, Bi: Ti = 4.4: 3 is used. Further, the range of this molar ratio is defined as Bi:
When Ti = approximately 4.08: 3 to 4.8: 3, a c-axis oriented film can be obtained. Within this range, Bi: Ti = 4.
The ratio is preferably from 24: 3 to 4.6: 3. More optimal is the case where Bi: Ti = 4.4: 3.
When such an organic solvent solution is used, a film suitable for use as a ferroelectric film oriented in the c-axis can be obtained. Further, such a solution can be obtained from Bismuth titanate (BI) by an organic metal decomposition method (MOD method) by Kojundo Chemical Laboratory Co., Ltd.
T) A solution for formation "can be purchased in the desired molar ratio of Bi and Ti.

Then, using this solution as a coating solution,
The lower electrode film 18 is spin-coated. The coating liquid is dropped on the lower electrode film 18, and immediately thereafter, the n-Si substrate 10 is kept at 500 rpm for 10 seconds, and further at 2500 rpm for 30 seconds.
Rotate for 2 seconds to form a coating film. After that, the coating film is preliminarily baked at 450 ° C. for 15 minutes in order to remove the solvent, and further heat-treated at 850 ° C. for 3 minutes (main firing) in dry oxygen using RTA to crystallize, for example, to a thickness of 600 ° A BIT film is formed. This film is referred to as a first film 30a (FIG. 8B). The film 30a is a BIT film in which the c-axis of the BIT constituting the film 30a is oriented substantially perpendicular to the upper surface of the lower electrode film 18, that is, the BIT film oriented in the c-axis. Further, this film 30a has a composition ratio of Bi which is larger than the stoichiometric composition of BIT.
IT. Note that a c-axis-oriented BIT film can be similarly formed by performing a heat treatment on the pre-baked film at 850 ° C. for 30 minutes in dry oxygen using a normal electric furnace.

Next, the above coating solution is further applied to the first film 30.
a and dropped on the n-Si substrate 10 at 500 rpm.
After rotating at 2500 rpm for 30 seconds to form a coating film, and calcining at 450 ° C. for 15 minutes, RTA
Baked at 850 ° C. for 3 minutes using
A second layer film 30b is formed on Oa. Similarly, a series of processes from the formation of the coating film using the coating solution to the preliminary baking and the main baking is further performed three times to form the third, fourth, and fifth layers (30c, 30d, and 30e). I do. As a result, a ferroelectric film including the BIT film 30 having a thickness of about 3000 ° is obtained (FIG. 8C).

The subsequent steps (from forming the upper electrode film on the ferroelectric film 30 to forming the Al wiring) are the first steps.
Since the third embodiment is the same as the first embodiment, the description is omitted here.

As a result, the MFMI
A semiconductor storage element including an S-type FET can be formed.

Such semiconductor memory elements are arranged in order from the top.
Upper electrode film, ferroelectric film, lower electrode film, gate insulating film,
And a FET having a semiconductor substrate (here, MF
MIS FET), and the ferroelectric film is a BIT film oriented along the c-axis. c
Since the BIT film oriented in the axis has a small relative dielectric constant and a small residual polarization value, when this element is operated, a sufficient electric field is applied to the ferroelectric film composed of the BIT film at a low gate voltage. As a result, stable operations such as writing and reading of information can be performed with a low gate voltage.

Further, a coating solution having a ratio of Bi: Ti = 4.4: 3 in the organic solvent solution was used as the coating solution, and this ratio was Bi: Ti = 4.08: 3-4. 8: 3
When the above range is satisfied, a film oriented in the c-axis is obtained. This ratio is Bi: Ti = 4.24: 3 to 4.6: 3.
In this case, a film substantially oriented along the c-axis and suitable for use as a ferroelectric film can be obtained. Bi: T
When i = 4.6: 3 to 4.8: 3, it can be used as a ferroelectric film, but the intensity of the c-axis is saturated, indicating that the result of analysis by XRD (X-Ray Diffraction method). Has been confirmed from. In addition, Bi:
A film formed using a coating solution in which Ti = 4.4: 3 is most suitable for use as a ferroelectric film of this device.

The surface of the ferroelectric film formed by the method of the fifth embodiment has a slightly lower flatness than that of the film formed by the method of the first embodiment. There is no problem in using it as a dielectric film.
Further, as in this embodiment, since the ferroelectric film can be constituted by one type of film formed using a Bi-rich coating solution, the manufacturing process is simplified, and the formation of the element is simplified. Becomes easier.

Also, it is basically the same as the fifth embodiment, except that the lower electrode film 18 is composed of a RuO ₂ (ruthenium oxide) film on the upper side and a Ru (ruthenium) film on the lower side. It may be provided as a film. The steps of forming the ferroelectric film and the effects of the ferroelectric film are the same as those of the fifth embodiment, and the other steps and effects are the same as those of the second embodiment. I do.

The lower electrode film 18 is made of RuO ₂
The lower side is a film composed of two layers of a Ru film. Between the lower electrode film 18 and the ferroelectric film 20, a flattening film containing bismuth titanate having a stoichiometric composition is provided. A film may be further provided.

Further, the flattening film is made of a BI having a high composition ratio of Ti to the stoichiometric composition of BIT.
It may be a film containing T (hereinafter, this film is also referred to as a Ti-rich BIT film).

<Sixth Embodiment> The sixth embodiment is basically the same as the first embodiment, except that the lower electrode film 18 is formed on the upper side and an IrO ₂ (iridium oxide) film is formed on the upper side. ,
The lower side is a film composed of two layers of Ir (iridium) film.

FIGS. 9A and 9B are schematic cross-sectional views (although cutaway views) for describing the configuration and the method of forming the semiconductor memory element according to the sixth embodiment. 2 shows a part of a process of forming a semiconductor storage element.

The steps up to the step of forming the polycrystalline Si film 16 are the same as in the first embodiment. Then, the polycrystalline Si film 1
6 by sputtering, for example, an I
An r film 18c is formed, and an IrO ₂ film 18d having a thickness of, for example, 1000 ° is formed on the Ir film 18c by a reactive sputtering method in an atmosphere containing oxygen and argon. Next, the ferroelectric film 20 is formed on the IrO ₂ film 18d.
Is formed in the same manner as in the first embodiment. Subsequently, on the ferroelectric film 20, an IrO film is used as an upper electrode film 22 here.
_{The two} films 22a are formed to a thickness of 2000 ° by sputtering (FIG. 9A). Thus, the ferroelectric film 20
Since the oxide film (IrO ₂ film 18d) is in contact with the oxide film, oxygen, which is easily deficient in the ferroelectric film, is supplied to the film, thereby suppressing film fatigue. As a result, the fatigue characteristics of the ferroelectric film can be improved. Further, providing the Ir film 18c between the polycrystalline Si film 16 without directly forming the IrO ₂ film prevents oxidation of the polycrystalline Si film, and prevents the polycrystalline Si film 16 and the IrO ₂ film 18d from being oxidized. This is for improving the adhesion. The IrO ₂ film 18d and the Ir film 18c
The lower electrode film 18 having excellent heat resistance. That is, the lower electrode film 18 is stable in a high-temperature oxygen atmosphere such as when a ferroelectric film is formed. Further, the lower electrode film 18 has a property of preventing mutual diffusion between the ferroelectric film and the electrode, that is, also has an excellent barrier property. When an IrO ₂ film is used as the upper electrode film 22, the upper and lower electrodes sandwiching the ferroelectric are electrodes of the same material, so that the ferroelectric hysteresis is not affected by the work function difference between the two electrodes.

Further, the Ir film 18c and the IrO ₂ film 1
8d is the upper electrode film 2 in the same manner as in the second embodiment.
Dry etching can be performed by using a chlorine-based or fluorine-based etching gas together with the IrO ₂ film 22a, the ferroelectric film 20, the polycrystalline Si film 16, and the gate insulating film 14 serving as 2. Therefore, all these films 1
4, 16, 18c, 18d, 20 (20a, 20b),
Dry etching is performed simultaneously and collectively on all the films 22a (FIG. 9B). For this reason, the process is simplified. Further, since a finer pattern can be formed as compared with a method including a patterning step by ion milling, miniaturization of an element can be expected. In the figure, 18c
x is the remaining Ir film, 18dx is the remaining IrO ₂ film,
And 22ax indicate the remaining IrO ₂ film.

The other manufacturing steps, effects, and the like are the same as those in the first embodiment, and thus detailed description will be omitted.

A flattening film containing stoichiometric bismuth titanate may be further provided between the lower electrode film 18 and the ferroelectric film 20. The flattening film may be a Ti-rich BIT film.

The ferroelectric film 20 is made of Bi in this example.
Although it is a composite film of a lower film obtained using a rich coating solution and an upper film obtained from a stoichiometric BIT,
It may be a single-layer film or a laminated film of a film obtained with a Bi-rich coating solution.

It is clear that the invention is not limited only to the exemplary embodiments. For example, in the above-described first, second, third, fourth, fifth, and sixth embodiments, the semiconductor memory element is constituted by an MFMIS-type FET, but the BIT film is used as the ferroelectric film. Is not limited to the MFMIS type as long as the semiconductor memory element is suitable for use.

For example, as a modification, the present invention
(Metal Ferroelectric Insulator Semiconductor) type FET can be applied. After forming up to the gate insulating film 14 (the n-Si substrate 10, the p-type well layer 12 and the gate insulating film 14) on the upper side of the n-Si substrate 10 as in the first embodiment, the gate insulating film 14 B on
The IT film 40 is formed as a ferroelectric film. BIT film 40
May be a composite film of a lower film obtained by using a Bi-rich coating solution and an upper film obtained from a BIT of stoichiometric composition as in the first embodiment, or the fifth embodiment As in the embodiment, a film obtained from a Bi-rich coating solution may be used. Thereafter, an electrode film 42 is formed (FIG. 10). The electrode film 42 may be made of a Ru-based material used for the upper electrode film of the first to fifth embodiments, Ir, IrO ₂ , Re, and ReO.
₂ can be used. Thus, from top to bottom
An MFIS-type FET including an electrode film, a ferroelectric film, a gate insulating film, and a semiconductor substrate can be formed. Note that, for the gate insulating film 14, Ta ₂ O ₅ , ZrO ₂ , CeO _2, or the like having a high dielectric constant can be used.

In each of the above-described embodiments, the case where the BIT film is formed by using an organic solvent solution in which the ratio of Bi to Ti is Bi: Ti = 4.4: 3 as a coating solution is shown. But the ratio of Bi and Ti is Bi: Ti = 4.
It was also confirmed that a c-axis oriented BIT film could be obtained similarly when a coating solution in the range of 08: 3 to 4.6: 3 was used as the coating solution. Also, here, a Pt film or Ru
O ₂ film has been described the case of forming a BIT film on the laminated film of the (Ru film and RuO ₂ film), other, IrO ₂
It was also confirmed that when a BIT film was formed on the film, the Si film, and the SiO ₂ film, a BIT film oriented in the c-axis was similarly obtained. The relative dielectric constant and remanent polarization of a BIT film formed using a coating solution in which the ratio of Bi to Ti in the organic solvent solution is in the range of Bi: Ti = 4.24: 3 to 4.6: 3. It was confirmed that the value and the coercive electric field were also sufficiently low.

[0099]

As is clear from the above description, according to the semiconductor memory device of the present invention, the upper electrode film, the ferroelectric film, the lower electrode film, the gate insulating film, and the semiconductor substrate are sequentially arranged from the upper side. In a semiconductor memory device including at least a field-effect transistor having a configuration, the ferroelectric film is a c-axis oriented BIT film, a Bi-rich lower film and a stoichiometric BIT single layer or The BIT film was composed of a laminated film including a plurality of upper films. Therefore, the relative permittivity and the remanent polarization value of the ferroelectric film are reduced. Therefore, a sufficient electric field can be applied to the ferroelectric film at a low gate voltage. As a result, stable operations such as writing and reading of information can be performed with a low gate voltage. Further, since the BIT film can have a flat surface, the subsequent formation process can be performed easily and accurately. In addition, since the ferroelectric film is flat, an electric field is uniformly applied, and electric field concentration can be prevented. Also,
By providing an oxide film such as a RuO ₂ film or an IrO ₂ film in contact with the ferroelectric film, the fatigue characteristics of the ferroelectric film can be improved.

Further, according to the method for forming a semiconductor memory device of the present invention, when forming the above-described semiconductor memory device, or on a base formed by sequentially forming a gate insulating film and a lower electrode film on a semiconductor substrate. Next, in forming a semiconductor memory element by forming a ferroelectric film and an upper electrode film sequentially, a ferroelectric film is formed including the following steps. First, a Ti source and a Bi source are dissolved,
The lower layer film is formed by using a first coating solution composed of an organic solvent solution in which the molar ratio of Bi is larger than the molar ratio of Bi to Ti determined from the stoichiometric composition of the above. Next, T
Using a second coating solution comprising an organic solvent solution of BIT in a molar ratio determined from the stoichiometric composition in which the i source and the Bi source are dissolved, the second coating solution is coated on the lower layer film, and By repeating firing one or more times, an upper layer film is formed. Therefore, it is a BIT film,
To easily form a semiconductor storage element including an FET having a ferroelectric film in which the BIT of the BIT constituting the film is oriented substantially perpendicular to the upper surface of the lower electrode film. Can be. That is, a semiconductor memory element including an MFMIS-type FET that can apply a sufficient electric field to the ferroelectric film with a low gate voltage can be easily formed. In addition, since the surface of the BIT film can be formed flat, the subsequent FET forming process can be performed easily and accurately. Further, since the BIT film is flat, it is possible to prevent electric field concentration from being generated in a part of the film.

Further, a ferroelectric film is formed including the following steps. First, a Ti source and a Bi source are dissolved, and Bi to Ti determined from the stoichiometric composition of BIT is used.
By using a coating solution composed of an organic solvent solution in which the molar ratio of Bi is larger than that of the above, the coating solution is applied on the lower electrode film and then baked one or more times. A BIT film with c-axis orientation is formed.
Therefore, a ferroelectric film can be formed more easily. Therefore, an FET having such a ferroelectric film
Can be more easily formed.

[Brief description of the drawings]

FIGS. 1A to 1D are schematic cross-sectional views illustrating a manufacturing process of a semiconductor memory element for explaining a first embodiment;

FIGS. 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor memory element for explaining the first embodiment, following FIG. 1;

FIGS. 3A to 3C are schematic cross-sectional views subsequent to FIG. 2, illustrating a manufacturing process of a semiconductor memory element used for describing the first embodiment;

FIGS. 4A to 4C are schematic cross-sectional views showing a manufacturing process of the semiconductor memory element used for describing the first embodiment following FIG. 3;

FIGS. 5A and 5B are model diagrams for explaining the flatness of the surface of the ferroelectric film according to the first embodiment; FIGS.

FIGS. 6A and 6B are schematic cross-sectional views for explaining a second embodiment.

FIGS. 7A and 7B are schematic cross-sectional views for explaining a third and a fourth embodiment.

FIGS. 8A to 8C are schematic sectional views for explaining a fifth embodiment;

FIGS. 9A and 9B are schematic cross-sectional views for explaining a sixth embodiment.

FIG. 10 is a schematic cross-sectional view for describing a modification of the present invention.

[Explanation of symbols]

10: n-Si substrate 12: p-type well layer 14: gate insulating film 14x: (residual) gate insulating film 16: polycrystalline Si film 16x: (residual) polycrystalline Si film 18: lower electrode film 18x: ( Lower electrode film 18a: Ru film 18b: RuO ₂ film 18c: Ir film 18d: IrO ₂ film 19: Flattening film 19x: (Remaining) flattening film 20: Ferroelectric film 20x: (Remaining) ferroelectric film 20a: Lower film 20ax: (Remaining) lower film 20b: Upper film 20bx: (Remaining) upper film 22: Upper electrode film 22a: IrO ₂ film 22x: (Remaining) upper electrode Film 24: SiO ₂ film 24x: Mask for patterning 30, 40: BIT film, ferroelectric film 42: Electrode film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/792

Claims (22)

[Claims] 1. A semiconductor memory device having at least a field-effect transistor having a configuration including an upper electrode film, a ferroelectric film, a lower electrode film, a gate insulating film, and a semiconductor substrate, in order from the top, The film is: 1) a bismuth titanate film; 2) the c-axis of bismuth titanate constituting the film is oriented substantially perpendicular to the upper surface of the lower electrode film; 3) titanium Stacking of a lower layer containing bismuth titanate in which the composition ratio of bismuth to the stoichiometric composition of bismuthate is higher, and an upper layer containing a single layer or a plurality of layers containing bismuth titanate having a stoichiometric composition A bismuth titanate film comprising a film. 2. The semiconductor memory device according to claim 1, wherein said lower electrode film is a Pt (platinum) film. 3. The semiconductor memory device according to claim 1, wherein said lower electrode film is made of RuO ₂ (ruthenium oxide).
A semiconductor memory element comprising a film and a lower layer formed of two layers of a Ru (ruthenium) film. 4. The semiconductor memory device according to claim 1, wherein said lower electrode film is made of RuO ₂ (ruthenium oxide).
When the film and the lower side are made of two layers of Ru (ruthenium) films, a flat film containing bismuth titanate having a stoichiometric composition is provided between the lower electrode film and the bismuth titanate film. A semiconductor memory element further comprising a film for conversion. 5. The semiconductor memory device according to claim 1, wherein the lower electrode film is made of RuO ₂ (ruthenium oxide).
When the film and the lower side are composed of two layers of Ru (ruthenium) films, the composition of titanium with respect to the stoichiometric composition of bismuth titanate is between the lower electrode film and the bismuth titanate film. It contains bismuth titanate whose ratio is increasing,
A semiconductor memory element further comprising a planarizing film. 6. A semiconductor memory device according to claim 1, wherein: a) a titanium source and a bismuth source are dissolved, and the molar ratio of bismuth to titanium determined from the stoichiometric composition of bismuth titanate is: Forming the underlayer film using a first coating solution comprising an organic solvent solution having an increased molar ratio of bismuth; and b) dissolving a titanium source and a bismuth source and determining a molar amount determined from a stoichiometric composition. Using a second coating solution consisting of an organic solvent solution of bismuth titanate in a ratio, the second coating solution is
Forming the upper layer film by repeating, once or more than once, applying and baking on the lower layer film, thereby forming the upper layer film. 7. A method for forming a semiconductor memory device by sequentially forming a ferroelectric film and an upper electrode film on a base in which a gate insulating film and a lower electrode film are sequentially formed on a semiconductor substrate. The ferroelectric film is formed by: a) an organic solvent in which the titanium source and the bismuth source are dissolved and the molar ratio of bismuth is greater than the molar ratio of bismuth to titanium determined from the stoichiometric composition of bismuth titanate Forming a lower layer film using a first coating solution comprising a solution; and b) dissolving a titanium source and a bismuth source and comprising a bismuth titanate organic solvent solution in a molar ratio determined by a stoichiometric composition. 2 using the second coating solution,
Forming an upper layer film by repeating application and baking on the lower layer film once or a plurality of times to form an upper layer film. 8. A semiconductor memory device including at least a field effect transistor having a configuration including an upper electrode film, a ferroelectric film, a lower electrode film, a gate insulating film, and a semiconductor substrate, in order from the top, wherein: The film is: 1) a bismuth titanate film; 2) the c-axis of bismuth titanate constituting the film is oriented substantially perpendicular to the upper surface of the lower electrode film; 3) titanium The bismuth titanate film is composed of a single layer or a plurality of layers containing bismuth titanate in which the composition ratio of bismuth is greater than the molar ratio of bismuth to titanium determined from the stoichiometric composition of bismuth acid. Semiconductor memory element. 9. The semiconductor memory device according to claim 8, wherein said lower electrode film is a Pt (platinum) film. 10. The semiconductor memory device according to claim 8, wherein said lower electrode film is made of RuO ₂ (ruthenium oxide).
A semiconductor memory element comprising a film and a lower layer formed of two layers of a Ru (ruthenium) film. 11. The semiconductor memory device according to claim 8, wherein said lower electrode film is made of RuO ₂ (ruthenium oxide).
When the film and the lower side are made of two layers of Ru (ruthenium) films, a flat film containing bismuth titanate having a stoichiometric composition is provided between the lower electrode film and the bismuth titanate film. A semiconductor memory element further comprising a film for conversion. 12. The semiconductor memory device according to claim 8, wherein said lower electrode film is made of RuO ₂ (ruthenium oxide).
When the film and the lower side are composed of two layers of Ru (ruthenium) films, the composition of titanium with respect to the stoichiometric composition of bismuth titanate is between the lower electrode film and the bismuth titanate film. It contains bismuth titanate whose ratio is increasing,
A semiconductor memory element further comprising a planarizing film. 13. A method for forming a semiconductor memory device according to claim 8, wherein a titanium source and a bismuth source are dissolved, and a molar ratio of bismuth is determined based on a molar ratio of titanium to titanium determined from a stoichiometric composition of the bismuth titanate. The bismuth titanate film is formed by repeating, once or more than once, using a coating solution composed of an organic solvent solution having a higher ratio, and applying the coating solution on the lower electrode film and then firing the coating solution one or more times. A method for forming a semiconductor memory element, comprising a step of forming. 14. A method for forming a semiconductor memory element by sequentially forming a ferroelectric film and an upper electrode film on a base on which a gate insulating film and a lower electrode film are sequentially formed on a semiconductor substrate. The ferroelectric film is formed by coating an organic solvent solution in which a titanium source and a bismuth source are dissolved and the molar ratio of bismuth is larger than that of titanium determined from the stoichiometric composition of bismuth titanate. A step of forming the bismuth titanate film by repeating, once or more than once, applying the coating solution on the lower electrode film using a liquid and then baking the coating solution. Element formation method. 15. The semiconductor memory device according to claim 1, wherein the lower electrode film has an upper side made of IrO ₂ (iridium oxide).
A semiconductor memory element comprising a film and a lower layer formed of two layers of an Ir (iridium) film. 16. The semiconductor memory device according to claim 1, wherein the lower electrode film has an upper side made of IrO ₂ (iridium oxide).
A semiconductor memory device, wherein the upper electrode film is an IrO ₂ (iridium oxide) film when the film is a film composed of two layers of Ir (iridium) film on the lower side. 17. The semiconductor memory device according to claim 1, wherein the lower electrode film has an upper side made of IrO ₂ (iridium oxide).
When the film and the lower side are formed of two layers of an Ir (iridium) film, a flat surface containing bismuth titanate having a stoichiometric composition is provided between the lower electrode film and the bismuth titanate film. A semiconductor memory element further comprising a film for conversion. 18. The semiconductor memory device according to claim 1, wherein the lower electrode film has an upper side made of IrO ₂ (iridium oxide).
Assuming that the film and the lower side are composed of two layers of Ir (iridium) film, the composition of titanium with respect to the stoichiometric composition of bismuth titanate is between the lower electrode film and the bismuth titanate film. A semiconductor memory element, further comprising a planarizing film containing bismuth titanate having an increased ratio. 19. The semiconductor memory device according to claim 8, wherein said lower electrode film has an upper side made of IrO ₂ (iridium oxide).
A semiconductor memory element comprising a film and a lower layer formed of two layers of an Ir (iridium) film. 20. The semiconductor memory device according to claim 8, wherein the lower electrode film has an upper side made of IrO ₂ (iridium oxide).
A semiconductor memory device, wherein the upper electrode film is an IrO ₂ (iridium oxide) film when the film is a film composed of two layers of Ir (iridium) film on the lower side. 21. The semiconductor memory device according to claim 8, wherein the lower electrode film has an upper side made of IrO ₂ (iridium oxide).
When the film and the lower side are formed of two layers of an Ir (iridium) film, a flat surface containing bismuth titanate having a stoichiometric composition is provided between the lower electrode film and the bismuth titanate film. A semiconductor memory element further comprising a film for conversion. 22. The semiconductor memory device according to claim 8, wherein the lower electrode film has an upper side made of IrO ₂ (iridium oxide).
Assuming that the film and the lower side are composed of two layers of Ir (iridium) film, the composition of titanium with respect to the stoichiometric composition of bismuth titanate is between the lower electrode film and the bismuth titanate film. A semiconductor memory element, further comprising a planarizing film containing bismuth titanate having an increased ratio.