JPH1056067A - Automatically laid-out wiring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of generating a wiring layout which meets delay constraints. SOLUTION: Slack graphs which represent delay constraints under various design conditions are prepared. Several conditions are present, so that two or more slack graphs are generated. A pin layout step 4 where a pin layout is improved by the use of the slack graphs, a cell layout step 1 where a cell layout is improved, and an approximate wiring step 3 where an approximate wiring route is improved are carried out, but it constitutes a feature of this method that all the steps are repeatedly carried out until a wiring layout meets the delay constraints represented by the all the slack graphs. By this setup, timing violations are previously removed, so that no timing violations are detected in a final verification stage of an LSI design, and a time required for design can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an automatic placement and routing method in a layout design of a semiconductor LSI. In other words, after arranging a plurality of functional blocks or a plurality of logic cells which are constituent elements of a semiconductor integrated circuit, wiring the plurality of functional blocks or a plurality of logic cells in accordance with a logical connection request and performing a layout design,
A timing-driven layout for arranging a plurality of logic cells with the wiring delay of each net as a constraint, a timing-driven rough wiring for determining a rough wiring route with the wiring delay of each net as a constraint, and a wiring delay for each net. The present invention relates to an automatic placement and routing method based on at least one timing driven pin arrangement that determines the arrangement of external pins (hereinafter, referred to as floating external pins) of a functional block that has not been laid out as a constraint.

[0002]

2. Description of the Related Art In recent years, as is called the system-on-silicon era, semiconductor LSI chips that are highly integrated to mount a system on one chip have been developed, and the man-hours required for LSI design have increased. It's going on. Among them, layout design is no exception, and man-hours and processing time are increasing exponentially.
A great deal of time and effort is spent laying out the entire circuit at once. Therefore, a hierarchical design technique is often employed in which a circuit is divided into several functional blocks, each is individually designed, and finally, the functional blocks are wired and assembled. An LSI in which a plurality of blocks are hierarchically assembled and a one-chip layout is designed is called a building block type LSI.

As a layout design method of a semiconductor LSI chip, a gate array (or sea of gate) is used.
System and standard cell system. In these methods, basic logic cells such as NAND gates and OR gates and composite cells combining them are arranged in an array on an LSI substrate, and wiring is performed between terminals on the cells according to a desired circuit connection. This is a method of making an LSI chip. These methods have advanced design automation,
Various design support systems (CAD systems) have been developed.

The basic procedure for designing with this system will be described. 1) Arrange logic cells in a virtual chip area (cell arrangement). 2) Apply schematic wiring for determining a rough wiring path on the chip (schematic wiring). 3) Based on the schematic wiring path, detailed wiring is performed to specifically satisfy the design rule and determine wiring between all nets (detailed wiring). Here, a net is a set of terminals that must be connected to the same potential.

[0005] In the case of designing with a building block type LSI as described above, a floor plan for deciding where to place the functional blocks on the entire chip is often performed first. At this time, since an unlaid-out functional block is also arranged, a pin arrangement for determining the position of an external terminal (floating external terminal) which controls input / output with the outside of the functional block is performed.

[0006] Advances in semiconductor LSI manufacturing technology have led to the design of chips with a design rule of 0.5 micron or less, which is now called deep submicron. Accordingly, the relationship between the wiring delay and the gate delay occupying the signal transmission time in the circuit, that is, the signal delay time (simply, the delay time) is expressed as wiring delay> gate delay,
It is an essential issue to consider wiring delay in chip design. In order to solve such a problem, designing a chip in consideration of a delay time is called timing-driven design.

Here, the basic principle of timing driven design will be briefly described. Generally, many semiconductor LSIs are designed with a synchronous circuit. This synchronization circuit is shown in FIG.
As shown in (1), it can be modeled as a set of combinational circuits that connect sets of synchronous elements (such as flip-flops) and synchronous elements. At this time, the clock cycle time Tclk of the synchronous circuit can be formulated as Tclk ≧ max (Thold + TD-Q + Tdelay + Tskew). Here, Thold is the setup and hold time of the synchronous element, TD-Q is the delay time from signal input to output inside the synchronous element, Tdelay is the delay time of the combinational circuit, and Tskew is the clock skew. For details, see the Proceedings of the 27th Design Automation Conference, 1990, page 57.
3-579 (Proc. Of the 27th Design Automation Co
nference, 1990, pp.573-579) ".

Furthermore, the delay time Tdelay of the combinational circuit
Can be modeled by the sum of the delays between gates (the delay from the fan-in of one gate to the fan-in of the next gate) Td. For example, two flip-flops (FF1 and FF2) as shown in FIG.
In an example in which the circuit is configured by gates, Tdelay = TQ + TAND + TOR. TQ, TAND, and TOR are delay times Td from the output driver of FF1, the AND gate, and the OR gate, respectively.

Further, the inter-gate delay time Td can be formulated as Td = Tintrinsic + Tload + Twire + Tpriv. Here, Tintrinsic is the gate delay time independent of the load, and Tload is the entire load (wiring capacitance +
Twire is a wiring delay time that depends on the wiring shape and the like, and Tpriv is a delay time that depends on the waveform blunting of the preceding stage. For details, see the Proceedings of the 31st Design Automation Conference, 1994, pages 327-332.
(Proc. Of the 31st Design Automation Conference,
1994, pp. 327-332) ".

Further, if the model is simplified and three terms except the wiring delay time Twire depending on the wiring shape are set in the gate delay time Tgate, the gate-to-gate delay time Td becomes Td = Tgate + Twire. The timing-driven design is a method of estimating a gate delay time and a wiring delay time based on the above-described modeling to design.

A design is advanced while estimating a gate delay and a wiring delay from an upper level of the design (for example, a functional design and a logic design). In a layout design, a layout diagram satisfying the estimated wiring delay is created. It must be generated. That is, the placement and routing is performed under the restriction of a certain wiring delay. As a method of expressing the delay constraint, a concept called slack is generally used. The slack value is a value indicating a margin of a signal path or the like with respect to a timing constraint (delay constraint), and is defined as slack (x) = Tr (x) -Ta (x). Here, Tr (x) is the arrival time required (by design) for circuit x (elements, signal paths, etc.), T
a (x) is actually in circuit x (determined on the layout diagram)
The time of arrival. If slack (x) is negative, it means that the timing has been violated.

Further, a slack graph often used in timing driven design will be described with reference to FIGS. FIG. 6A shows a circuit diagram of a circuit including six logic cells 1 to 6 (four AND cells and two buffer cells), and the signals of this circuit flow from left to right, The path delay constraint of this circuit is, for example, 19
And In this figure, the numerical value indicating the intra-cell delay obtained when a certain layout is performed is described near each logic cell, and the numerical value indicating the net wiring delay is set close to the wiring connecting each logical cell. It has been described. In addition,
The unit of the delay constraint or each delay value is, for example, picosecond or nanosecond.

FIG. 6 (b) is a schematic diagram showing an example of an arrangement result when a circuit including the circuit of FIG. 6 (a) is arranged (laid out) by a standard cell LSI. FIG.
FIG. 6C is an enlarged view of the circuit portion of FIG. 6A in FIG. 6B. For example, in-cell delay and net wiring delay when the layout is laid out as shown in FIG.
This is described in the circuit of FIG. The layout can be performed by arranging the logic cells 1 to 6 constituting the circuit of FIG. 6A on a column and performing net wiring between the logic cells 1 to 6. The arrangement of the logic cells 1 to 6 is arbitrary.
Thus, when the arrangement of each of the logic cells 1 to 6 is determined,
The wiring of the net has a physical distance, and the wiring delay of the net can be calculated. Further, since the length of the wiring is known, it is possible to calculate the intra-cell delay. Therefore, once the arrangement position is determined, the net wiring delay and the intra-cell delay are calculated.

Here, the reason why the intracell delay can be calculated by knowing the length of the wiring will be described. As described above, the inter-gate delay time Td is represented by Td = Tintrinsic + Tload + Twire + Tpriv. This is referred to as intra-cell delay Tgate and wiring delay Twire.
As described above, Td = Tgate + Twire. Here, Tgate = Tintrinsic + Tload + Tpriv.

Next, how the intra-cell delay Tgate is calculated will be described below. Since Tintrinsic is a gate delay independent of load, it is uniquely determined when a cell is determined and does not depend on wiring. Tload is the gate delay time for the entire load, which is calculated based on the sum of the load capacities of the nets connected to the output side of the cell. Therefore, if the length of the wiring is known, the wiring load capacity can be determined, and the calculation can be performed. Tpriv is a delay time that depends on the waveform blunting of the preceding stage connected to the input side of the cell, and is calculated by the wiring net of the preceding stage. If the length of the wiring is known, it cannot be calculated accurately, but it can be calculated approximately. From the above, if the length of the wiring is known, Tgate can be calculated.

Next, the reason why the path delay constraint can be replaced with the net wiring delay constraint will be described. Design delay constraints are defined in the form of path delay constraints. However, as can be seen from FIG. 6B, since the length of the wiring is known at the stage of the placement, the wiring delay of the net is known. When the placement is improved to satisfy the path delay constraint, some changes are repeatedly made with reference to the original placement position, so it is verified whether the delay constraint is adhered to in the path. The basis,
The net result is to change the net length to some extent, so that the path delay constraint can be replaced with the net wiring delay constraint. Therefore, it is considered that the layout design is equivalent to the path delay constraint and the net wiring delay constraint.

FIG. 7 shows an initial state of a first slack graph prepared based on the arrangement result of FIG. 6C of the circuit of FIG. 6A. This slack graph is converted to condition 0 (typi
cal condition) is defined as the graph below. Conventionally, this typical
Timing-driven placement / wiring is performed only under a condition (condition 0), that is, under only one condition. In FIG. 7, FIG.
The output end of each logic cell of (a), that is, the vertex is indicated by a circle,
The wiring (net) of the input / output unit of each of the logic cells 1 to 6 in FIG. Vertices 1 to 6 in FIG.
Each of the vertices 1 to 6 corresponds to the logic cell 1 to 6 in FIG. 6A, and describes the same intra-cell delay value as shown in FIG. Describes the cumulative delay value. Also, the wiring delay value of the same net shown in FIG. 6A is described in the undirected branches connected to the vertices 1 to 6, and the cumulative delay value is described in parentheses in addition thereto. Note that the cumulative delay value is the maximum value (longest path) of the cumulative value of the delay values from each start end of the circuit in FIG. 6A to the corresponding vertex or undirected branch. At this time, since the path delay is not calculated, the accumulated delay values are all zero.

FIG. 8 shows a slack graph as a result (typical condition (condition 0)) of path delay calculation based on the slack graph in the initial state of FIG. In the slack graph of this figure, the critical path is from vertex 2 to vertex 4
→ It becomes vertex 6. Here, a method of calculating a path delay (calculation of an accumulated delay value) in the slack graph of FIG. 8 will be described.

The path delay is calculated using the longest delay time required to reach a certain vertex. For example, vertex 1
Since the path delay up to that time is 1, the sum with the intra-cell delay value 1 is obtained, and the path delay up to vertex 1 = 1 + 1 = 2. Similarly, the path delay up to vertex 2 = 2 + 3 = 5. Further, the path delay to vertex 3 is the sum of the path delay to vertex 1 and the wiring delay between vertex 1 and vertex 3, and the sum of the path delay to vertex 2 and the wiring delay between vertex 2 and vertex 3. Is obtained by taking the sum of the maximum value among the above and the intra-cell delay value of vertex 3. That is, path delay to vertex 3 = path delay to vertex 2 + vertex 2
Delay between node and vertex 3 + delay in vertex 3 cell = 5 + 1
+ 4 = 10 Similarly, path delay to vertex 4 = 5 + 1 + 6 = 12 path delay to vertex 5 = 10 + 2 + 6 = 18 path delay to vertex 6 = 12 + 2 + 6 = 20. Since the path delay constraint is 19, slack (5) = 19−18 = 1 slack (6) = 19−20 = −1. Since slack (5)> slack (6), the path for which slack (6) is calculated is 2 → 4 → 6, and this path is a critical path. In addition, since the slack value is negative, a timing violation has occurred. To eliminate this violation, wiring up to vertex 2, vertex 2 to vertex 4
, Or any of the vertices 4 to 6 must be shortened.

In the timing driven design, the wiring is improved (shortened) until all slack values become positive. See “Proceedings of 22nd
Times, Design Automation Conference, 1
985, pages 124-130 (Proc. Of the 22nd De
sign Automation Conference, 1985, pp.124-130).

A method of arranging cells in consideration of a delay time is called a timing driven arrangement.
"IEE International Conference on Computer Aided Design, 1988, pp. 506-509 (Proc. IEEE I
nternational Conference on Computer Aided Design, 1
988, pp.506-509) "," IEE International Conference on Computer Aided Design, 1991, pp. 48-
51 (Proc. IEEE International Conference on Compu
ter Aided Design, 1991, pp.48-51) ”.

In the schematic wiring, a timing-driven schematic wiring is called, and as a conventional technique, "IEE.
IEEE International Conference on Computer Aided Design, 1990, pp. 48-51 (Proc. IEEE International Conference
on Computer Aided Design, 1990, pp.48-51).

There are few examples where the pin arrangement is performed in a timing driven manner. As described above, the design is advanced in the order of cell arrangement → schematic wiring → detailed wiring, but the effect of preventing a delay violation taking into account delay constraints (timing) appears in the cell arrangement> schematic wiring. > Detailed wiring order.

[0024]

SUMMARY OF THE INVENTION Designed semiconductor LS
As a process for determining whether or not to manufacture an I chip, there is a final verification simulation, a so-called back annotation process. In this technique, a gate delay and a wiring delay are estimated based on a layout diagram designed on a computer, and an operation simulation is performed under various conditions.
If the final verification simulation fails,
It is necessary to change the layout drawing. This leads to an increase in design costs. In many cases, a simulation is performed by varying gate delays and wiring delays determined from a layout diagram within a certain range in order to consider variations in chip manufacturing. For example, a simulation is performed by doubling each of the reference gate delay value and the reference wiring delay value.

As described above, in the actual chip design, it is necessary to satisfy a plurality of delay constraints in order to consider the manufacturing and use conditions of the chip. In the above-described cell placement technique, there is only one wiring delay constraint for each net. Therefore, as a method for solving the problem, the timing-driven arrangement is performed by representing the worst delay constraint, that is, the one having a severe wiring delay constraint (small wiring delay value). This method satisfies the setup time in the clock design, but cannot guarantee that the hold time, which is another index, is satisfied, and may cause an error in the final verification simulation.

In other words, in the layout design, it is a problem whether the time at the latest time is smaller than the design value of the setup time, and whether the time at the earliest time is larger than the design value of the hold time. The problem is that the timing-driven placement is typified by the one with strict wiring delay constraints, which addresses the former problem, but does not address the latter problem.

Here, the setup time is a time required to store data in a cell, for example, a time until data is completely set in a flip-flop. The hold time is a time during which data must be held in a cell, for example, a time during which data must be held at least in a flip-flop. Also, in the above-described general wiring technique, there is only one wiring delay constraint for each net. Therefore, there is the same problem as the cell arrangement.

In the pin placement technique, the placement is rarely timing driven. The pin arrangement problem is a problem that occurs when wiring between function blocks, and is a problem of where a floating external terminal can be placed in a non-layout function block (on the periphery of the normal block) to reduce the chip area. Until now, the pin placement technology has been aimed at placing the wiring between functional blocks at a position where the wiring length can be minimized. Considering wiring delay is treated as a problem of functional block placement in the floor plan, and wiring delay is controlled by determining the wiring route between functional blocks (schematic wiring).
It was entrusted to. If the wiring delay is severe (small), it is dealt with by relatively approaching the arrangement of the functional blocks having the strictly restricted nets. Furthermore, approximate wiring is performed for the purpose of minimizing the wiring length, thereby approaching the restriction. However, since the pin arrangement can be freely arranged on the periphery of the functional block, there is a possibility that a large change which cannot be controlled by the schematic wiring can be made. In a chip design with stricter timing constraints, it is essential to perform timing-driven operation at the pin arrangement stage.

Accordingly, it is an object of the present invention to provide an automatic placement and routing method that can eliminate the occurrence of an error due to a timing violation in a final verification simulation.

[0030]

In order to solve the above-mentioned problems, an automatic placement and routing method according to the first aspect of the present invention provides a method for automatically placing and routing a plurality of function blocks or a plurality of logic cells which are constituent elements of a semiconductor integrated circuit. Automatic placement and routing method using timing-driven placement for arranging a plurality of logic cells while restricting the wiring delay of each net when performing layout design by wiring between functional blocks or a plurality of logic cells according to a logic connection request Wherein each cell has a plurality of wiring delay constraints, and includes a cell arrangement step of arranging a plurality of logic cells so as to satisfy all of the plurality of wiring delay constraints.

According to this configuration, since a plurality of logic cells are arranged so as to satisfy all of the plurality of wiring delay constraints, a plurality of logic cells can be arranged so as not to cause a timing violation. Thus, the occurrence of an error due to a timing violation can be eliminated. In the automatic placement and routing method according to the second aspect, in the automatic placement and routing method according to the first aspect, the cell placement step represents a plurality of wiring delay constraints by a plurality of delay constraint graphs (hereinafter, referred to as slack graphs). , When they are defined as a slack graph Gi (i is a natural number),
a slack graph generation step of creating i based on a plurality of wiring delay constraints, a cell initial placement step of temporarily arranging a plurality of logic cells, and a plurality of wiring delay constraints can be satisfied based on the slack graph Gi. And a cell arrangement improvement step of improving the arrangement of a plurality of logic cells, and sequentially repeating the cell arrangement improvement step so as to satisfy the plurality of wiring delay constraints expressed by all slack graphs Gi. .

According to this configuration, a slack graph Gi is created based on a plurality of wiring delay constraints, a plurality of logic cells are temporarily arranged, and then a plurality of wiring delay constraints are created based on all slack graphs Gi. Since the arrangement of a plurality of logic cells is improved so as to satisfy the above condition, the plurality of logic cells can be arranged so as not to cause a timing violation, and an error due to a timing violation in a final verification simulation can be eliminated.

In the automatic placement and routing method according to the third aspect, after arranging a plurality of function blocks or a plurality of logic cells as constituent elements of a semiconductor integrated circuit, a logical connection request is made between the plurality of function blocks or the plurality of logic cells. Is a timing-driven general routing method for determining a general routing path with the wiring delay of each net as a constraint when performing a layout design by wiring according to the following. And a general wiring step of determining a general wiring path so as to satisfy all of a plurality of wiring delay constraints.

According to this configuration, the rough wiring path is determined so as to satisfy all of the plurality of wiring delay constraints, so that the rough wiring path can be determined without causing a timing violation. Can eliminate the occurrence of an error. In the automatic placement and routing method according to a fourth aspect, in the automatic placement and routing method according to the third aspect, the general routing step expresses a plurality of wiring delay constraints by a plurality of delay constraint graphs (hereinafter, referred to as slack graphs). , They are slack graph Gi
(I is a natural number), a slack graph generating step of creating a slack graph Gi based on a plurality of wiring delay constraints, an initial wiring path determining step of temporarily determining a schematic wiring path, and a slack graph Gi. And a wiring route improving step of improving a schematic wiring route so as to satisfy a plurality of wiring delay constraints on the basis of the above, and sequentially providing a plurality of wiring delay constraints expressed in all slack graphs Gi so as to satisfy the constraints. It is characterized in that the improvement step is repeated.

According to this configuration, the slack graph Gi is created based on a plurality of wiring delay constraints, and after a rough wiring path is temporarily determined, a plurality of wiring delay constraints can all be satisfied based on the slack graph Gi. Since the general wiring path is improved as described above, the general wiring path can be determined so as not to cause a timing violation, and an error due to the timing violation in the final verification simulation can be eliminated.

In the automatic placement and routing method according to the fifth aspect, after arranging a plurality of function blocks or a plurality of logic cells as constituent elements of a semiconductor integrated circuit, a logical connection request is made between the plurality of function blocks or the plurality of logic cells. Automatic layout and wiring method using timing-driven pin layout for deciding the layout of external pins (hereinafter referred to as floating external pins) of a functional block that has not been laid out with the wiring delay of each net as a constraint when performing the layout design by wiring according to And has a plurality of wiring delay constraints for each net,
It is characterized by including a pin arrangement step of arranging floating external pins on the function block so as to satisfy all of the plurality of wiring delay constraints.

According to this configuration, the floating external pins on the functional block are arranged so as to satisfy all of the plurality of wiring delay constraints. Therefore, the floating external pins on the functional block are arranged so as not to cause a timing violation. Therefore, it is possible to eliminate an error due to a timing violation in the final verification simulation. In the automatic placement and routing method according to a sixth aspect, in the automatic placement and routing method according to the fifth aspect, the pin placement step represents a plurality of wiring delay constraints by a plurality of delay constraint graphs (hereinafter, referred to as slack graphs). And a slack graph Gi (i is a natural number), a slack graph generating step of creating the slack graph Gi based on a plurality of wiring delay constraints, and temporarily arranging floating external pins on functional blocks. Floating external pin initial arrangement step, floating external pin initial wiring path determining step for temporarily determining a schematic wiring path between functional blocks, and floating external pin initial wiring path determining step based on slack graph Gi. Floating external pin placement improvement step for improving the placement of floating external pins so as to maintain the schematic routing path and satisfy a plurality of wiring delay constraints ,
A wiring path improvement step of improving the schematic wiring path so that the schematic wiring path determined in the floating external pin initial wiring path determination step based on the slack graph Gi can satisfy a plurality of wiring delay constraints. The method is characterized in that a floating external pin arrangement improving step and a wiring path improving step are sequentially repeated so as to satisfy a plurality of wiring delay constraints expressed by Gi.

According to this configuration, the slack graph Gi is created based on a plurality of wiring delay constraints, the floating external pins on the function blocks are temporarily arranged, and the general wiring path between the function blocks is temporarily determined. After that, the layout of the floating external pins is improved so as to satisfy the constraints of the plurality of wiring delays based on the slack graph Gi so as to hold the schematic wiring paths, and the schematic wiring path has a plurality of wiring based on the slack graph Gi. Since the schematic wiring path is improved so as to satisfy the delay constraint, the floating external pins can be arranged so as not to cause a timing violation, and an error due to the timing violation in the final verification simulation can be eliminated.

In the automatic placement and routing method according to the present invention, after arranging a plurality of function blocks or a plurality of logic cells which are constituent elements of a semiconductor integrated circuit, a logical connection request is made between the plurality of function blocks or the plurality of logic cells. And a timing-driven arrangement for arranging a plurality of logic cells with the wiring delay of each net as a constraint, and a timing-driven arrangement for roughly determining a routing path with the wiring delay of each net as a constraint when performing a layout design by wiring according to An automatic placement and routing method using schematic routing and timing driven pin placement for determining the placement of external pins (hereinafter referred to as floating external pins) of a functional block that has not been laid out with the wiring delay of each net as a constraint. Have multiple routing delay constraints on the net and satisfy all the multiple routing delay constraints A cell placement step for arranging a number of logic cells, a rough wiring step having a plurality of wiring delay constraints for each net, and determining a wiring route so as to satisfy all of the plurality of wiring delay constraints; The present invention is characterized by including a plurality of wiring delay constraints on the net and a pin arrangement step of arranging floating external pins on the functional block so as to satisfy all of the plurality of wiring delay constraints.

According to this configuration, the first and third aspects operate in combination. The automatic placement and routing method according to claim 8 is the automatic placement and routing method according to claim 7.
The cell arrangement step is configured in the same manner as in claim 2. According to this configuration, the operation is the same as that of the second aspect. Claim 9
In the automatic placement and routing method according to the seventh aspect, the schematic routing step is configured in the same manner as in the fourth aspect.

According to this configuration, the operation is the same as that of the fourth aspect. An automatic placement and routing method according to a tenth aspect is the seventh aspect of the invention.
In the automatic placement and routing method described above, the pin placement step is configured in the same manner as in claim 6. According to this configuration, the operation is the same as that of the sixth aspect.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an automatic placement and routing method according to an embodiment of the present invention will be described with reference to the drawings.
An embodiment of the present invention provides a layout design by arranging a plurality of function blocks or a plurality of logic cells which are constituent elements of a semiconductor integrated circuit and then wiring the plurality of function blocks or a plurality of logic cells in accordance with a logical connection request. A timing-driven layout for arranging a plurality of logic cells with the wiring delay of each net as a constraint, a timing-driven schematic wiring for determining a rough wiring path with the wiring delay of each net as a constraint, 9 shows an automatic placement and routing method based on at least one timing driven pin arrangement for deciding the arrangement of external pins (hereinafter referred to as floating external pins) of a functional block that has not been laid out with a restriction on a net wiring delay. In each embodiment of the present invention, a layout design is performed using a plurality of slack graphs. Therefore, prior to the description of the embodiment, each net has a plurality of wiring delay constraints and a plurality of wiring delay constraints. Therefore, a plurality of wiring delay constraints, that is, a plurality of slack graphs will be described. The first slack graph for the circuit of FIG. 6 is the slack graph of the typical conditions of FIGS. 7 and 8 described above. In addition, the first slack graph of the circuit of FIG. It is possible to create second to fifth slack graphs different from each other. The number of slack graphs is arbitrary.

FIG. 9 shows an initial state of a second slack graph created based on the arrangement result of FIG. 6C of the circuit of FIG. 6A. This slack graph shows an initial slack graph when the intra-cell delay and the net delay are each doubled with respect to the typical conditions of the slack graph of FIG. This slack graph is defined as a graph under condition 1. In the slack graph under the condition 1, the respective delay values are doubled as compared with the slack graph under the condition 0. Therefore, the physical meaning is assumed to be a case where the manufacturing state of the entire chip is bad. It can be said. Subsequent processing of the path delay calculation is performed in the same manner as in the case of the condition 0.

FIG. 10 shows an initial state of a third slack graph created based on the arrangement result of FIG. 6C of the circuit of FIG. 6A. This slack graph is an initial slack graph when the intra-cell delay and the net delay are each multiplied by 0.5 with respect to the typical conditions of the slack graph of FIG. This slack graph is defined as a graph under condition 2. In the slack graph under the condition 2, the respective delay values are set to 0.5 times as compared with the slack graph under the condition 0. Therefore, the physical meaning is that the manufacturing state of the entire chip is good. It can be said that it is assumed. Subsequent processing of the path delay calculation is performed in the same manner as in the case of the condition 0.

FIG. 11 shows the initial state of the fourth slack graph created based on the layout result of FIG. 6C of the circuit of FIG. 6A. This slack graph shows an initial slack graph when the intracell delay is doubled and the net delay is doubled with respect to the typical conditions of the slack graph of FIG. This slack graph is defined as a graph under condition 3. The slack graph under this condition 3 is
Compared to the slack graph under condition 0, the delay value of the intra-cell delay is set to 0.5 times and the net delay is doubled.
Physically, it can be said that it is assumed that the manufacturing state of the wiring region is bad, but the manufacturing state of the transistor region is good. Actually, since the number of layers and materials in the vertical direction of the wiring region and the transistor region are different, it is quite possible that the wiring region and the transistor region have different manufacturing states. Subsequent processing of the path delay calculation is performed in the same manner as in the case of the condition 0.

FIG. 12 shows an initial state of a fifth slack graph created based on the arrangement result of FIG. 6C of the circuit of FIG. 6A. This slack graph shows an initial slack graph when the net delay is multiplied by 0.5 and the intra-cell delay is doubled with respect to the typical conditions of the slack graph of FIG. This slack graph is defined as a graph under condition 4. The slack graph under this condition 4 is
Compared to the slack graph under the condition 0, the delay value of the net delay is 0.5 times and the delay in the cell is 2 times.
Physically, it can be said that it is assumed that the manufacturing state of the transistor region is bad, but the manufacturing state of the wiring region is good. Subsequent processing of the path delay calculation is performed in the same manner as in the case of the condition 0.

The arrangement is improved until the path delay constraint is satisfied based on the slack graphs of the above conditions 1 to 4 and the above condition 0. In this case, as described above,
For determining whether the time at the latest time is smaller than the design requirement value of the setup time, the condition of the requirement value of the setup time can be verified in the slack graphs of the conditions 1 and 3. In addition, regarding the determination as to whether or not the earliest time is greater than the design value of the hold time, the condition of the required value of the hold time can be verified in the slack graphs of Condition 2 and Condition 4. As described above, when a layout is designed using a plurality of slack graphs with different conditions, it is possible to eliminate timing violations, and to eliminate errors due to timing violations in the final verification simulation.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 11 is a flowchart regarding cell arrangement in the automatic arrangement and wiring method according to the embodiment. Standard cell system L of FIG.
This will be described by taking SI as an example. FIG. 13A shows a state before arranging logic cells in a standard cell LSI. On the left side of the figure is a group of cells 11 to be arranged, and on the right side of FIG.
1 shows a standard cell system block 10 composed of a set of cells (each box is called a slot).

First, as shown in FIG. 1, a slack graph as described with reference to FIGS. 6 to 12 is created based on the delay constraint (slack graph generation step 2). At this time (in the actual LSI design as described above), there are a plurality of delay constraints, and therefore, a plurality of slack graphs exist. This is defined as a slack graph Gi (i is a natural number).
FIG. 13C schematically shows a case where there are two delay constraints (slack graphs G1 and G2).

Next, in the initial cell arrangement step 1a, cell arrangement is temporarily performed. At this time, the timing-driven arrangement may be performed using the slack graph G1 by any method, but the present embodiment does not apply the slack graph G1. FIG. 13B shows an arrangement result. In order to highlight only one net, cells (cell 11) and the connection relationship therebetween are represented by solid lines (net 13) in order to highlight only one net. Hereinafter, how the movement of the net changes by applying the slack graph Gi will be illustrated.

The application of the slack graph Gi is continued until all the constraints are satisfied by the cell arrangement improving step 1b. FIG. 13D shows a cell arrangement result when the timing-driven arrangement is improved by applying the slack graph G1. This shows that the arrangement distribution of the cells 11 of the net 13 has slightly changed. Next, timing-driven placement is improved by applying a slack graph G2 based on the placement result shown in FIG. Further, the arrangement distribution of the cells 11 of the net 13 changed as shown in FIG. Here, the placement was improved by applying two delay constraints. Since the placement was improved by the slack graph G2, it is verified again whether or not the slack graph G1 satisfies the delay constraints. If so, the configuration ends. However, if the delay constraint is not satisfied, the slack graph G
1 to improve timing-driven placement. FIG.
In (e), the arrangement is improved because the delay constraint is not satisfied. The arrangement result is shown in FIG. Then, similarly, it is verified whether or not the delay constraint is satisfied by the slack graph G2 based on the arrangement result of FIG. If so, the configuration ends. FIG. 13 (g) shows the final result on the assumption that the present embodiment is satisfied.

At this time, each time the arrangement of the cells 11 is changed by applying the slack graphs G1 and G2, the wiring delay constraint of the nets of the slack graphs G1 and G2 is changed. With the above operation, the cell placement step 1 is performed in which a plurality of wiring delay constraints are provided for each net and a plurality of cells are placed so as to satisfy all of the plurality of wiring delay constraints.

As described above, according to the present embodiment, at the cell placement stage, the placement is improved until the plural wiring delay constraints of the net are satisfied, and the timing violation is removed in advance. No timing violation is detected in the final verification stage, and the design period can be shortened. (Second Embodiment) FIG. 2 is a flowchart for schematic wiring in an automatic placement and routing method according to a second embodiment of the present invention.

The standard cell type LS shown in FIG.
A description will be given by taking the cell arrangement result in I as an example. FIG.
(A) shows the state of the connection relationship between the cell 11 and the net 13 connected to it. Similarly, two delay constraints are used. First, as shown in FIG. 2, since there are two delay constraints in the slack graph generation step 2, slack graphs G1 and G2 are generated (FIG. 14C).

Next, in an initial wiring route determination step 3a, a rough wiring route is temporarily obtained. This is also similar to the initial cell arrangement step 1a, and the slack graph G1
May be used to perform timing-driven placement,
In the present embodiment, the slack graph G1 is not applied.
FIG. 14B shows an example of the wiring route result in the initial wiring route determination step 3a, and only the net 13 is highlighted. Hereinafter, how the movement of the net changes by applying the slack graph Gi will be illustrated.

The application of the slack graph Gi is continued until all the wiring delay constraints are satisfied in the wiring path improvement step 3b. FIG. 14D is a schematic wiring result when the timing-driven general wiring is improved by applying the slack graph G1. This indicates that the wiring route of the net 13 has slightly changed. Next, the timing-driven general wiring is improved by applying the slack graph G2 based on the arrangement result of FIG. Further, the wiring route of the net 13 has changed. Here, the wiring route is improved by applying two delay constraints. However, since the wiring route is improved by the slack graph G2, it is verified again whether or not the slack graph G1 satisfies the delay constraint. If satisfied, the wiring improvement ends there. However, if the delay constraint is not satisfied, the timing-driven general routing is improved again based on the slack graph G1. FIG. 14E shows that the delay constraint is satisfied, and this is the final result.

At this time, every time the slack graphs G1 and G2 are applied and the schematic wiring of the net 13 is changed, the wiring delay constraint of the nets of the slack graphs G1 and G2 is changed. In the above operation, the global routing step 3 is executed, which has a plurality of routing delay constraints for each net and determines a rough routing path so as to satisfy all the plurality of routing delay constraints.

As described above, according to the present embodiment, the timing violation is removed in advance by improving the wiring path until a plurality of delay constraints are satisfied at the time of the general wiring, so that the final LSI design is completed. No timing violation is detected at the verification stage, and the design period can be shortened. (Third Embodiment) FIG. 3 is a flowchart relating to the pin arrangement in the automatic arrangement and wiring method according to the third embodiment of the present invention. This will be described with reference to FIG.

FIG. 15A shows three unlaid-out function blocks 23 (called soft blocks, for example, formed by standard cell type blocks) and laid-out function blocks 24 (called hard blocks, for example, a memory, a multiplier, etc.). 1) is a floor plan diagram in which there is one. The function block 24 has fixed external pins 22 whose positions are fixed, and the function block 23 has floating external pins 21 whose positions are undefined. In the figure, the floating external pin 21 is temporarily arranged at the center of the functional block 23. Further, it is assumed that those pins are the same net (net 20). It is also assumed that there are two delay constraints as in the previous embodiment.

First, as shown in FIG. 3, since there are two delay constraints in the slack graph generation step 2, slack graphs G1 and G2 are generated (FIG. 15B).
This is the same as described above. Next, the floating external pins 21 of the functional block 23 are arranged at a certain position (here, on the periphery of the block) of the functional block 23 in the initial arrangement step 4a of the floating external pin (FIG. 15C). Similarly to the initial cell arrangement step 1a in FIG. 1, timing-driven arrangement may be performed using the slack graph G1 by any method, but the present embodiment does not apply the slack graph G1. FIG. 15C shows an example of the pin arrangement result after the execution of the floating external pin initial arrangement step 4a, in which only the net 20 is highlighted. Hereinafter, how the movement of the net changes by applying the slack graph Gi will be illustrated.

Since the arrangement of the floating external pins 21 has been determined,
A schematic wiring in the net 20 is obtained in an external pin initial wiring path determination step 4b. At this time, timing-driven general routing is performed using the slack graph Gi, as in the case of the general routing step 3. The result is shown in FIG.
Is shown in Here, if all the delay constraints can be satisfied (slack graph Gi), the pin arrangement is terminated here. In the case of the present embodiment, it is assumed that all delay constraints have not been satisfied.

Next, floating external pin arrangement improvement step 4
The floating external pin arrangement is improved using c. Also at this time, the pin arrangement is performed on the slack graph Gi in a timing driven manner. The timing driven pin arrangement can be realized by replacing the pins with cells and arranging timing driven cells. In the case of this example, it is illustrated that the floating external pin 21 of the function block 23 has slightly moved (FIG. 9E).

Next, a schematic wiring route is determined according to the pin arrangement. The method is the placement route improvement step 3b.
Is the same as Here, it is verified again whether all the delay constraints are satisfied. If not satisfied, the floating external pin arrangement improving step 4c or the arrangement path improving step 3b is executed. The pin arrangement is more effective for improving the delay (adjusting the wiring path length). This is because if the number of wiring channels (wiring regions) is not large between the blocks, the wiring path length rarely changes significantly. In FIG. 15F, the delay constraint is satisfied, and this is the final result.

At this time, every time the slack graphs G1 and G2 are applied and the floating external pin arrangement is changed, the wiring delay constraint of the nets of the slack graphs G1 and G2 is changed. In the above operation, the pin arrangement step 4 for arranging the floating external pins on the functional blocks so as to have a plurality of wiring delay constraints for each net and to satisfy all of the plurality of wiring delay constraints is executed. become.

As described above, according to the present embodiment, the timing of the timing violation is removed in advance by improving the pin arrangement and wiring route until a plurality of delay constraints are satisfied at the pin arrangement stage. No timing violation is detected at the final verification stage of the LSI design, and the design period can be shortened. (Fourth Embodiment) FIG. 4 is a flowchart showing an automatic placement and routing method according to a fourth embodiment of the present invention. This will be described with reference to FIG. FIG. 16A is similar to FIG. 15A. An illustration is given of how the net wiring changes according to a series of procedures.

First, as shown in FIG. 4, in the floor plan, the layout positions of the functional blocks are determined (function block layout step 5), and the layout of the external pins in the unlayout functional blocks (the pin layout step) is taken into consideration in consideration of the inter-block wiring route. The main processing is to perform 4). FIG. 16 (a)
Indicates the result at the time when the functional block arrangement step 5 is completed. The position of the functional block arrangement can be arbitrarily determined.

Next, in the slack graph generation step 2, the delay constraint is expressed by a slack graph Gi. The pin arrangement step 4 is executed using the slack graph Gi. At this time, the pin arrangement is determined according to the procedure described in the third embodiment. The result is shown in FIG. Next, since the arrangement of the external pins has been determined, a layout in a functional block that has not been laid out is created (placement and wiring). Here, taking the functional block 23 as an example, it is assumed that the functional block 23 is created by a standard cell type block (FIG. 16).
(C)). In the cell arrangement step 1, the logic cells 11 are arranged on a column based on a previously designed circuit. The arrangement result is shown in FIG. Of course, the placement result satisfies all delay constraints.

Further, in the general wiring step 3, a general wiring path is determined in a timing driven manner. The result is shown in FIG. 9E (only the net 13 is highlighted). Since the schematic wiring routes have been determined, the detailed wiring step 6 is executed to generate a wiring pattern satisfying the design rule for them. The results obtained are shown in FIG. Perform those steps for all unlayout functional blocks. When layout of all blocks is completed, layout between functional blocks is performed.

The layout between functional blocks has two phases, that is, schematic wiring and detailed wiring, similarly to the layout within functional blocks. The general wiring between the functional blocks can be realized by the same procedure as the general wiring in the functional block (the general wiring step 3 between the functional blocks = the general wiring step 3). Finally, the detailed inter-functional-block wiring step 7 is executed to generate a wiring pattern that satisfies the design rule, and the process ends.

As described above, according to the present embodiment, the placement of cells, the placement of cells, and the route of wiring are improved until a plurality of delay constraints are satisfied at each stage of placement and routing to remove timing violations in advance. As a result, no timing violation is detected at the final verification stage of the LSI design.
The design period can be shortened.

[0071]

According to the automatic placement and routing method of the present invention, a plurality of logic cells are arranged so as to satisfy all of a plurality of wiring delay constraints, so that a timing violation does not occur in a plurality of logic cells. In the final verification simulation, an error due to a timing violation can be eliminated.

According to the automatic placement and routing method of the present invention, a slack graph Gi is created based on a plurality of wiring delay constraints, and after temporarily arranging a plurality of logic cells, all slack graphs Gi are created. Based on this, the layout of multiple logic cells is improved so as to satisfy the constraints of multiple wiring delays.
A plurality of logic cells can be arranged so as not to cause a timing violation, and an error due to a timing violation can be eliminated in the final verification simulation.

According to the automatic placement and routing method according to the third aspect, since the rough wiring path is determined so as to satisfy all of the plurality of wiring delay constraints, the rough wiring path can be determined so as not to cause a timing violation. Thus, it is possible to eliminate an error due to a timing violation in the final verification simulation. According to the automatic placement and routing method according to the fourth aspect, the slack graph Gi is created based on a plurality of wiring delay constraints, a general wiring path is temporarily determined, and then a plurality of wirings are all based on the slack graph Gi. Since the general wiring path is improved so as to satisfy the delay constraint, the general wiring path can be determined so as not to cause a timing violation, and an error due to the timing violation in the final verification simulation can be eliminated.

According to the automatic placement and routing method according to the fifth aspect, the floating external pins on the functional block are arranged so as to satisfy all of the plurality of wiring delay constraints. Can be arranged so as not to cause the occurrence of an error due to a timing violation in the final verification simulation.

According to the automatic placement and routing method according to the sixth aspect, the slack graph Gi is created based on a plurality of wiring delay constraints, and floating external pins on the function blocks are temporarily arranged, and After the schematic wiring path is temporarily determined, the layout of floating external pins is improved so as to satisfy the constraints of a plurality of wiring delays by maintaining the general wiring path based on the slack graph Gi, and based on the slack graph Gi. Improve the schematic routing path so that the schematic routing path can satisfy multiple routing delay constraints, so that floating external pins can be placed so as not to cause timing violations, and errors due to timing violations occur in the final verification simulation Can be eliminated.

According to the automatic placement and routing method of the seventh aspect, the effects of the first, third and fifth aspects are obtained. According to the automatic placement and routing method of the eighth aspect, the effects of the first, second, third and fifth aspects are obtained. According to the automatic placement and routing method of the ninth aspect, the effects of the first, third, fourth, and fifth aspects are obtained.

According to the automatic placement and routing method of the tenth aspect, the effects of the first, third, fifth and sixth aspects are obtained.

[Brief description of the drawings]

FIG. 1 is a flowchart of cell placement in an automatic placement and routing method according to a first embodiment of the present invention.

FIG. 2 is a schematic flowchart of a wiring in an automatic placement and routing method according to a second embodiment of the present invention;

FIG. 3 is a flowchart of a pin arrangement in an automatic placement and routing method according to a third embodiment of the present invention.

FIG. 4 is a flowchart of placement and routing in an automatic placement and routing method according to a fourth embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating the principle of synchronous design.

FIG. 6 is a schematic diagram illustrating the concept of a slack graph.

FIG. 7 is a schematic diagram showing an example of a slack graph.

FIG. 8 is a schematic diagram showing an example of a slack graph.

FIG. 9 is a schematic diagram showing an example of a slack graph.

FIG. 10 is a schematic diagram showing an example of a slack graph.

FIG. 11 is a schematic diagram showing an example of a slack graph.

FIG. 12 is a schematic diagram showing an example of a slack graph.

FIG. 13 is an exploded view illustrating a cell arrangement in the automatic placement and routing method according to the first embodiment of the present invention.

FIG. 14 is an exploded view for explaining schematic wiring in the automatic placement and routing method according to the second embodiment of the present invention.

FIG. 15 is an exploded view illustrating a pin arrangement in the automatic placement and routing method according to the third embodiment of the present invention.

FIG. 16 is an exploded view for explaining placement and routing in the automatic placement and routing method according to the fourth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 Cell placement step 1a Initial cell placement step 1b Cell placement improvement step 2 Slack graph generation step 3 Schematic routing step 3a Initial routing path determination step 3b Routing path improvement step 4 Pin placement step 4a Initial pin placement step 4b Initial routing between floating external pins Route determination step 4c Floating external pin placement improvement step

Claims (10)

[Claims] After arranging a plurality of function blocks or a plurality of logic cells which are constituent elements of a semiconductor integrated circuit, wiring is performed between the plurality of function blocks or a plurality of logic cells in accordance with a logical connection request to perform a layout design. In this case, there is provided an automatic placement and routing method based on timing-driven placement in which the plurality of logic cells are placed with the wiring delay of each net as a constraint, wherein each of the nets has a plurality of wiring delay constraints,
An automatic placement and routing method, comprising a cell placement step of placing the plurality of logic cells so as to satisfy all of the plurality of routing delay constraints. 2. The cell placement step, wherein a plurality of wiring delay constraints are represented by a plurality of delay constraint graphs (hereinafter, referred to as slack graphs), and when these are defined as slack graphs Gi (i is a natural number), A slack graph generating step of creating a slack graph Gi based on the plurality of wiring delay constraints, a cell initial arrangement step of temporarily arranging a plurality of logic cells, and the plurality of wiring delays based on the slack graph Gi. And a cell placement improving step of improving the placement of the plurality of logic cells so as to satisfy the constraints of the above. The cell placement is sequentially performed so as to satisfy the constraints of the plurality of wiring delays expressed by all the slack graphs Gi. 2. The automatic placement and routing method according to claim 1, wherein the improvement step is repeated. 3. A layout design is performed by arranging a plurality of functional blocks or a plurality of logic cells which are constituent elements of a semiconductor integrated circuit, and then wiring the plurality of functional blocks or the plurality of logic cells in accordance with a logical connection request. In this case, there is provided an automatic placement and routing method based on timing-driven schematic routing that determines a schematic routing path with the wiring delay of each net as a constraint, wherein each of the nets has a plurality of wiring delay constraints,
An automatic placement and routing method, comprising a general routing step of determining a general routing path so as to satisfy all of the plurality of wiring delay constraints. 4. The general routing step expresses a plurality of wiring delay constraints as a plurality of delay constraint graphs (hereinafter, referred to as slack graphs), and when these are defined as slack graphs Gi (i is a natural number), A slack graph generating step of creating a slack graph Gi based on the plurality of wiring delay constraints, an initial wiring path determining step of temporarily determining a schematic wiring path, and the plurality of wiring delays based on the slack graph Gi. And a wiring path improving step of improving the general wiring path so as to satisfy the constraint, and sequentially performing the wiring path improving step so as to satisfy the constraints of the plurality of wiring delays represented by all the slack graphs Gi. 4. The automatic placement and routing method according to claim 3, wherein the method is repeated. 5. After arranging a plurality of function blocks or a plurality of logic cells as constituent elements of a semiconductor integrated circuit, wiring is performed between the plurality of function blocks or the plurality of logic cells in accordance with a logical connection request to perform a layout design. In this case, there is provided an automatic placement and routing method based on timing-driven pin placement for determining the placement of external pins (hereinafter referred to as floating external pins) of a functional block that has not been laid out with the wiring delay of each net as a constraint. Has multiple wiring delay constraints for
A method of arranging floating external pins on the functional block so as to satisfy all of the plurality of wiring delay constraints. 6. The pin placement step, wherein the plurality of wiring delay constraints are represented by a plurality of delay constraint graphs (hereinafter, referred to as slack graphs), and when these are defined as slack graphs Gi (i is a natural number), A slack graph generation step of creating a slack graph Gi based on the constraints of the plurality of wiring delays, a floating external pin initial placement step of temporarily arranging floating external pins on functional blocks, and a schematic wiring between the functional blocks A step of determining an initial wiring path between floating external pins for temporarily determining a path; and a step of storing the plurality of wiring delays by holding a schematic wiring path obtained in the step of determining an initial wiring path between floating external pins based on the slack graph Gi. A floating external pin arrangement improving step of improving the arrangement of the floating external pins so as to satisfy the following constraint: And a wiring path improving step of improving the general wiring path so that the general wiring path obtained in the floating external pin initial wiring path determining step satisfies the plurality of wiring delay constraints.
6. The automatic placement and routing method according to claim 5, wherein the floating external pin placement improvement step and the wiring path improvement step are sequentially repeated so as to satisfy the constraints of the plurality of wiring delays expressed by: 7. A layout design is performed by arranging a plurality of function blocks or a plurality of logic cells which are constituent elements of a semiconductor integrated circuit and then wiring the plurality of function blocks or a plurality of logic cells in accordance with a logical connection request. In this case, a timing-driven layout for arranging the plurality of logic cells with the wiring delay of each net as a constraint, a timing-driven schematic wiring for determining a rough wiring path with the wiring delay of each net as a constraint, A timing-driven pin arrangement for determining the arrangement of external pins (hereinafter referred to as floating external pins) of a functional block that has not been laid out with the wiring delay of the net being a constraint. With multiple routing delay constraints,
A cell arranging step of arranging the plurality of logic cells so as to satisfy all of the plurality of wiring delay constraints; and a plurality of wiring delay constraints for each of the nets, all of the plurality of wiring delay constraints being satisfied. A general routing step of determining a wiring route so as to perform the routing, and arranging floating external pins on the functional block so as to satisfy all of the plurality of wiring delay constraints. Automatic placement and routing method, which includes a pin placement step of performing the following. 8. The cell arranging step includes, when a plurality of wiring delay constraints are represented by a plurality of delay constraint graphs (hereinafter, referred to as slack graphs), and when these are defined as slack graphs Gi (i is a natural number), A slack graph generating step of creating a slack graph Gi based on the plurality of wiring delay constraints, a cell initial arrangement step of temporarily arranging a plurality of logic cells, and the plurality of wiring delays based on the slack graph Gi. And a cell placement improving step of improving the placement of the plurality of logic cells so as to satisfy the constraints of the above. The cell placement is sequentially performed so as to satisfy the constraints of the plurality of wiring delays expressed by all the slack graphs Gi. 8. The automatic placement and routing method according to claim 7, wherein the improvement step is repeated. 9. The schematic routing step includes: expressing a plurality of wiring delay constraints in a plurality of delay constraint graphs (hereinafter, referred to as slack graphs), and defining them as slack graphs Gi (i is a natural number). A slack graph generating step of creating a slack graph Gi based on the plurality of wiring delay constraints, an initial wiring path determining step of temporarily determining a schematic wiring path, and the plurality of wiring delays based on the slack graph Gi. And a wiring path improving step of improving the general wiring path so as to satisfy the constraint, and sequentially performing the wiring path improving step so as to satisfy the constraints of the plurality of wiring delays represented by all the slack graphs Gi. 8. The automatic placement and routing method according to claim 7, wherein the method is repeated. 10. The pin placement step, wherein a plurality of wiring delay constraints are represented by a plurality of delay constraint graphs (hereinafter, referred to as slack graphs), and when these are defined as slack graphs Gi (i is a natural number), A slack graph generation step of creating a slack graph Gi based on the constraints of the plurality of wiring delays, a floating external pin initial placement step of temporarily arranging floating external pins on functional blocks, and a schematic wiring between the functional blocks A step of determining an initial wiring path between floating external pins for temporarily determining a path; and a step of storing the plurality of wiring delays by holding a schematic wiring path obtained in the step of determining an initial wiring path between floating external pins based on the slack graph Gi. A floating external pin arrangement improving step of improving the arrangement of the floating external pins so as to satisfy the following constraint; and based on the slack graph Gi. A wiring path improving step of improving the general wiring path so that the general wiring path obtained in the floating external pin initial wiring path determining step satisfies the plurality of wiring delay constraints.
8. The method according to claim 7, wherein the floating external pin arrangement improving step and the wiring path improving step are sequentially repeated so as to satisfy the constraints of the plurality of wiring delays represented by i.
Automatic placement and routing method described.