JPH1055265A - Arithmetic processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a time penalty with sign extension as to partial product addition by parallel multipliers. SOLUTION: A partial product adder 15 which adds four partial products P0, P1, P2, and P3 that are binary numbers represented as complement of '2' and differ in weight from one another comprises a carry storage adder 20 constituted by arraying 4:2 compressors. In each 4:2 compressor, a W input among the four inputs shows the shortest propagation delay and Y and Z inputs constitute a critical path. So that the 1st partial product P0 having the least weight is sign-extended, a logic circuit 30 sets the logical operation value between the value of the sign digit P0s of the 1st partial product and the value of the sign digit P1s of the 2nd partial product having the 2nd small weight to digits higher in order than the sign digit P0s of the 1st partial product, and while the sign-extended 1st partial product P0 is allocated to the W input of the carry storage adder 20, the values of the high-order digits of the Z input regarding the 2nd partial product P1 are fixed at 0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit having a multiplication function, and more particularly to a multiplier.

[0002]

2. Description of the Related Art In a parallel multiplier, a product is calculated by adding a plurality of partial products generated in parallel using a multiplier and a multiplicand. According to the Booth's algorithm, the number of partial products can be reduced.

[0003] MRSantoro et al., "SPIM: A Pipelined
64x64-bit Iterative Multiplier ", IEEE Journal of So
lid-State Circuits, Vol. 24, No. 2, pp. 487-493, A
According to pril 1989, a 4: 2 compressor capable of building a binary tree is suitable for adding partial products. A carry save adder consisting of a number of 4: 2 compressors is provided for the addition of partial products, and each 4: 2 compressor has two 3-input 2
It is composed of an output full adder.

A plurality of partial products have different weights from each other. Therefore, when each partial product is a binary number expressed in two's complement, it is necessary to perform sign extension of the partial product prior to carry save addition of the partial product. Here, an example is considered in which four partial products P0, P1, P2, and P3 generated according to the secondary Booth's algorithm are added. These four partial products P0, P1, P2 and P3 have weights of 2 ⁰ , 2 ² , 2 ⁴ and 2 ⁶ , respectively, and each have 9 digits. The most significant digit of each partial product is the sign digit. In this example, it is necessary to sign-extend each of the three partial products P0, P1, and P2 except for the partial product (highest partial product) P3 having the largest weight. Specifically, the first partial product is divided into six digits higher than the sign digit of the first partial product so as to sign-extend the partial product (first partial product) P0 having the minimum weight. Set the value of the sign digit. Also, the sign of the second partial product is added to the four digits higher than the sign digit of the second partial product so as to sign-extend the partial product (second partial product) P1 having the second smallest weight. Set the digit value. Furthermore, 3
The partial product having the second smallest weight (third partial product) P2
Is set to the value of the sign digit of the third partial product in two digits higher than the sign digit of the third partial product.
Carry save addition is performed for each of the four partial products P0, P1, P2, and P3 after the sign extension.

[0005]

The 4: 2 compressor has, as the name implies, four inputs and two outputs. One of the four inputs passes through only one of the two full adders to both outputs of the 4: 2 compressor, while the other three inputs sequentially pass through the two full adders. To both outputs of the 4: 2 compressor. That is, any of the latter three inputs constitutes a critical path having the longest propagation delay in the carry save adder. However, when sign-extending all partial products except the highest-order partial product as described above, the input of the critical path depends on the value of the sign digit of any of the partial products,
There is a time penalty.

An object of the present invention is to reduce a temporal penalty associated with sign extension in partial product addition.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for specifying a specific partial product sign-extended based on a plurality of code digits without forming a critical path in a carry save adder. , And the input constituting the critical path in the carry save adder is fixed to a constant value.

More specifically, an arithmetic processing unit or a multiplier according to the present invention provides a partial product for adding a plurality of partial products each of which is a binary number represented by a two's complement and has different weights from each other. A carry-save adder having a plurality of inputs and at least one output for carry-save-adding the plurality of partial products; and the plurality of partial products. Of the sign digit of the first partial product and the sign digit of the other partial product in a plurality of digits higher than the sign digit of the partial product (first partial product) having the smallest weight of And a logic circuit for setting the logical operation value of Moreover, in the carry save adder, a particular input has a shorter propagation delay with respect to an output than at least one other input, and the first partial product sign-extended by the logic circuit is Assigned to a specific input.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a multiplier, which is a kind of arithmetic processing unit according to the present invention, will be described below with reference to the drawings.

FIG. 1 shows a specific configuration example of a multiplier according to the present invention. The multiplier of FIG. 1 calculates a product M of a multiplicand U and a multiplier V, each of which is an 8-digit binary number represented by a two's complement, and a multiplier encoder 10 and four partial product generators 11, 12, 13 and 14 and a partial product adder 15
And a carry look-ahead adder 16. The multiplier encoder 10 calculates four encoded values E0, E1, E2 from the multiplier V according to the second-order Booth algorithm.
And E3. Four partial product generators 11, 12,
13 and 14 are a multiplicand U and four encoded values E0,
From E1, E2, and E3, 2's complement representation of 2
Four partial products P0, P1, P2 and P3 which are base numbers and have different weights are generated in parallel. These four
Pieces of partial products P0, P1, P2 and P3 are respectively 2 ⁰ , 2 ² ,
It has 2 ⁴ and the weight of 2 ^6, and each consisting of 9 digits. The most significant digit of each partial product is the sign digit. The partial product adder 15
Carry save addition is performed for each of the four partial products P0, P1, P2, and P3, and the addition result (consisting of two binary numbers) Q is supplied. Carry look-ahead adder 16 obtains product M based on addition result Q supplied from partial product adder 15.

FIGS. 2 and 3 show the partial product adder 1 shown in FIG.
5 shows the internal configuration. 2 and 3, 2
0 is a carry save adder composed of 15 4: 2 compressors 200 to 214, and 30 is a logic circuit composed of an exclusive OR gate 31 and an OR gate 32. Each of the fifteen 4: 2 compressors 200-214 actually has five inputs X, Y, Z, W and CI,
It has three outputs C, S and CO. Here, CI is a carry input from the lower digit, and CO is a carry output to the upper digit. C is a carry output to the carry look-ahead adder 16, and S is a sum output to the carry look-ahead adder 16. Four partial products P0, P1, P2 and P3
Are the W and Z inputs of the carry save adder 20, respectively.
Allocated to Y input and X input. In FIG. 2, P0s is the code digit of the partial product (first partial product) P0 having the smallest weight, P1s is the code digit of the partial product (second partial product) P1 having the second smallest weight, P2s is the partial product having the third smallest weight (third partial product) P
2 and P3s represent the code digit of the partial product (most significant partial product) P3 having the maximum weight.

According to FIG. 2, the first partial product P0 is sign-extended as follows. That is, the value of the code digit P0s of the first partial product is set as it is to the digit (weight 2 ⁹ ) one digit higher than the code digit P0s of the first partial product. Second
The exclusive OR gate 31 assigns the value of the sign digit P0s of the first partial product to the digit (weight 2 ¹⁰ ) of the first partial product P0 at a position corresponding to the position of the sign digit P1s of the partial product of An exclusive OR value A with the value of the sign digit P1s of the second partial product is set. Then, from the digit (weight 2 ¹¹ ) of the first partial product P0 at the position corresponding to the digit one digit higher than the code digit P1s of the second partial product, the position of the code digit P3s of the highest partial product is changed. By the OR gate 32, the value of the sign digit P0s of the first partial product and the value of the sign digit P1s of the second partial product before the digit (weight 2 ¹⁴ ) of the first partial product P0 at the corresponding position Is set as the logical sum value B. Here, A = P0s∧P1s B = P0s + P1s, where “∧” indicates an exclusive OR and “+” indicates a logical OR.

On the other hand, the sign digit of the second partial product P1 (weight 2
¹⁰ ) and the four digits (weights 2 ¹¹ to 2 ¹⁴ ) higher than the code digit are fixed to 0. Also, the third partial product P
The value of the code digit P2s of the third partial product is set in the two digits (weights 2 ¹³ to 2 ¹⁴ ) higher than the code digit of 2.

If the first and second partial products P0 and P1 are sign-extended respectively according to the above-mentioned conventional example, 2 ¹⁰ to 2
Add the two partial products for 5 digits with weights up to ¹⁴ , 0000 + 000 if P0s = 0 and P1s = 0
00 = 000000 If P0s = 1 and P1s = 0, then 111111 + 000
00 = 11111 If P0s = 0 and P1s = 1, then 000000 + 111
11 = 11111 If P0s = 1 and P1s = 1, then 11111 + 111
11 = 11110. That is, as described above, if the value of the five digits of the first partial product P0 (weights 2 ¹⁰ to 2 ¹⁴ ) is determined by the logic circuit 30, the five digits of the second partial product P1 (weight 2
The values of ¹⁰ to 2 ¹⁴ ) can all be fixed to 0 as described above.

FIG. 4 shows a single 4: 2 compressor 214.
2 shows the internal configuration of the device. 4: 2 compressor 214
Is composed of first and second full adders 101 and 102. The first and second full adders 101 and 102 each have three inputs IN1, IN2 and IN3 and two outputs C
Y (carry) and SUM (sum).
The X, Y and Z inputs of the 4: 2 compressor 214 are the IN1 and IN inputs of the first full adder 101, respectively.
Allocated to 2 inputs and IN3 inputs. Also,
The W input of the 4: 2 compressor 214 is assigned to the IN2 input of the second full adder 102. The SUM output of the first full adder 101 is equal to the IN output of the second full adder 102.
One input and the carry input CI from the lower digit are applied to the IN3 input of the second full adder 102, respectively. The carry output CO to the upper digit is supplied from the first full adder 101, and the C output and the S output to the carry look-ahead adder 16 are supplied from the second full adder 102, respectively. The internal configuration of the other fourteen 4: 2 compressors 200 to 213 in FIGS. 2 and 3 is the same as that in FIG.

FIG. 5 shows the internal configuration of the first full adder 101. The full adder 101 includes two exclusive OR gates 111 and 112 and three two-input NAND gates.
Gates 113, 114 and 115 and one 3-input NA
And an ND gate 116. The internal configuration of second full adder 102 in FIG. 4 is the same as that in FIG.

According to FIGS. 4 and 5, the W input of the 4: 2 compressor 214 passes only through the second full adder 102, ie, through at most two gates, the C output of the 4: 2 compressor 214. And S output. The X input reaches the C output via at most three gates in the first and second full adders 101 and 102. On the other hand, the Y and Z inputs are up to four of the first and second full adders 101 and 102, respectively.
Through several gates to the C output. That is, the W input exhibits the shortest propagation delay, and the Y and Z inputs are the carry save adders 2
It can be seen that a critical path in 0 is formed. Therefore, as described above, the first partial product P0 is applied to the W input, the second partial product P1 is applied to the Z input, the third partial product P2 is applied to the Y input, and the fourth partial product P3 is applied to the X input. Assigned.

FIG. 6 shows the four partial products P0, P1, P
2 conceptually shows sign extension and allocation of P2 and P3.
Since the five most significant digits of the Z input constituting the critical path are fixed to a constant value 0 which does not depend on the value of the sign digit of any of the partial products, the time penalty associated with sign extension is reduced, and high-speed multiplication is performed. It can contribute to realization. Moreover, the exclusive OR value A and the OR value B relating to the first partial product P0 are generated by one gate in the logic circuit 30, and the first partial product P0 is allocated to the W input. Therefore, the propagation delay in the logic circuit 30 does not increase the propagation delay of the partial product adder 15.

The four partial products P0, P1, P2 and P3 may be assigned to the X, Y, Z and W inputs of the carry save adder 20, respectively. In this case, the five most significant digits of the Y input constituting the critical path are fixed to a fixed value of 0, so that the time penalty associated with sign extension is also reduced. Moreover, since the first partial product P0 having the input delay of one gate is assigned to the X input, the propagation delay in the logic circuit 30 does not increase the propagation delay of the partial product adder 15.

FIG. 7 shows a modification of FIG. In this modification, not only the most significant five digits of the Z input but also the most significant three digits of the Y input of the carry save adder 20 are fixed to a constant value 0.
In FIG. 7, reference numeral 40 denotes a logic circuit including two exclusive OR gates 41 and 43 and two OR gates 42 and 44. The point that the four partial products P0, P1, P2 and P3 are allocated to the W input, the Z input, the Y input and the X input of the carry save adder 20, respectively, is the same as in FIG.

According to FIG. 7, the first partial product P0 is sign-extended as follows. That is, the value of the code digit P0s of the first partial product is set as it is to the digit (weight 2 ⁹ ) one digit higher than the code digit P0s of the first partial product. Second
The exclusive OR gate 41 assigns the value of the sign digit P0s of the first partial product to the digit (weight 2 ¹⁰ ) of the first partial product P0 at the position corresponding to the position of the sign digit P1s of the partial product An exclusive OR value A with the value of the sign digit P1s of the second partial product is set. The digit (weight 2) of the first partial product P0 at the position corresponding to the digit position one digit higher than the code digit P1s of the second partial product
^{In (11} ), the OR gate 42 sets the OR value B of the value of the sign digit P0s of the first partial product and the value of the sign digit P1s of the second partial product. Sign digit P2s of third partial product
At the position corresponding to the position of the first partial product P0 (weight 2
¹² ), the exclusive OR gate 43 outputs the OR value B
An exclusive OR value G of the value and the value of the sign digit P2s of the third partial product is set. And the sign digit P2s of the third partial product
From the digit (weight 2 ¹³ ) of the first partial product P0 at the position corresponding to the position of the digit one digit higher than the code digit P3 of the highest partial product
Until the digit (weight 2 ¹⁴ ) of the first partial product P0 at the position corresponding to the position of s, the logical sum gate 44 sets the logical sum value B
The logical sum value H of the value of the sign digit P2s of the third partial product and the value is set. Here, A = P0s∧P1s B = P0s + P1s G = B∧P2s H = B + P2s, where “∧” indicates exclusive OR and “+” indicates OR.

On the other hand, the code digit of the second partial product P1 (weight 2
¹⁰ ) and the four digits (weights 2 ¹¹ to 2 ¹⁴ ) higher than the code digit are fixed to 0. The sign digit (weight 2 ¹² ) of the third partial product P2 and the two digits (weight 2 ¹³ ) higher than the sign digit
To 2 ¹⁴ ) are also fixed to 0.

FIG. 8 shows the four partial products P0, P1, P
2 conceptually shows sign extension and allocation of P2 and P3.
Since the upper digits of both the Y and Z inputs constituting each critical path are fixed to a constant value 0 which does not depend on the value of the sign digit of any partial product, the time penalty associated with sign extension is further reduced. , And can contribute to the realization of high-speed multiplication. Moreover, the exclusive OR value A relating to the first partial product P0
And G and OR values B and H are generated by at most two gates in the logic circuit 40, and the first partial product P0 is assigned to the W input.
Does not increase the propagation delay of the partial product adder 15.

Although each of the above embodiments is a multiplier provided with a carry save adder composed of a plurality of 4: 2 compressors, the present invention provides that a specific input among a plurality of inputs is at least one. It is generally applicable to multipliers with carry save adders that exhibit shorter propagation delays compared to the other inputs.
For example, in a 16 digit × 16 digit multiplier, a plurality of 7: 3
The present invention can be applied to addition of partial products in a carry save adder in which compressors are arranged. Further, the algorithm to be adopted in the multiplier encoder is not limited to the secondary Booth algorithm, but may be a higher-order Booth algorithm.

[0025]

As described above, according to the present invention, a specific partial product sign-extended based on a plurality of code digits is allocated to a specific input which does not constitute a critical path in a carry save adder. Since the input constituting the critical path in the carry save adder is fixed at a constant value, the time penalty associated with sign extension in partial product addition can be reduced, and high-speed multiplication can be realized. Can contribute to

[Brief description of the drawings]

FIG. 1 is a block diagram showing a specific example of a multiplier according to the present invention.

FIG. 2 is a block diagram showing a part of the internal configuration of the partial product adder in FIG.

FIG. 3 is a block diagram showing another portion of the internal configuration of the partial product adder in FIG. 1;

FIG. 4 is a block diagram showing an internal configuration of one 4: 2 compressor in FIGS. 2 and 3;

FIG. 5 is a circuit diagram showing an internal configuration of one full adder in FIG. 4;

FIG. 6 is a diagram showing an operation of the partial product adder having the configuration of FIGS. 2 and 3;

FIG. 7 is a block diagram showing a modification of FIG. 2;

8 is a diagram illustrating an operation of the partial product adder having the configuration of FIG. 7;

[Explanation of symbols]

 Reference Signs List 10 multiplier encoder 11-14 partial product generator 15 partial product adder 16 carry look-ahead adder 20 carry save adder 30, 40 logic circuit 101, 102 full adder 200-214 4: 2 compressor

Claims (10)

[Claims] 1. An arithmetic processing device comprising a partial product adder for adding a plurality of partial products each having a binary number represented by two's complement and having different weights, wherein the partial product addition is performed. A carry-save adder having a plurality of inputs and at least one output for carry-save-adding the plurality of partial products; and a partial product having a minimum weight among the plurality of partial products. In order to sign-extend (first partial product), the value of the sign digit of the first partial product and the sign digit of another partial product are added to a plurality of digits higher than the sign digit of the first partial product. And a logic circuit for setting a plurality of logical operation values with a value of the carry-save adder, wherein in the carry save adder, a specific input of the plurality of inputs has a shorter propagation length than at least one other input. A delay between said output and said logic circuit. Sign extended first partial product processing unit, characterized in that allocated to the specific input. 2. The arithmetic processing device according to claim 1, wherein the first partial product sign-extended by the logic circuit has an input having a shortest propagation delay between the input and the output of the plurality of inputs. An arithmetic processing device characterized by being assigned to: 3. The arithmetic processing device according to claim 1, wherein the logic circuit has a maximum weight of the plurality of partial products from a digit one digit higher than the code digit of the first partial product. An arithmetic processing device having a function of determining each value up to the first partial product digit at a position corresponding to the code digit position of the partial product (highest partial product). 4. The arithmetic processing device according to claim 3, wherein the logic circuit has a second smallest weight of the plurality of partial products from a digit one digit higher than the code digit of the first partial product. The first partial product at the position corresponding to the position of the digit one digit lower than the sign digit of the partial product (the second partial product)
The value of the sign digit of the first partial product is set in the digit of the first partial product at a position corresponding to the position of the sign digit of the second partial product. Setting an exclusive OR value with the value of the code digit of the second partial product; and setting the first partial product at a position corresponding to a position of a digit one digit higher than the code digit of the second partial product From the digit of the first partial product to the digit of the first partial product at a position corresponding to the position of the code digit of the most significant partial product.
An arithmetic processing unit having a function of setting a logical sum value of a partial digit of a partial product and a sign digit value. 5. The arithmetic processing device according to claim 3, wherein the logic circuit has a second smallest weight of the plurality of partial products from a digit one digit higher than the code digit of the first partial product. The first partial product at the position corresponding to the position of the digit one digit lower than the sign digit of the partial product (the second partial product)
The value of the sign digit of the first partial product is set in the digit of the first partial product at a position corresponding to the position of the sign digit of the second partial product. Setting an exclusive OR value with the value of the code digit of the second partial product; and setting the first partial product at a position corresponding to a position of a digit one digit higher than the code digit of the second partial product , The partial product having the third smallest weight among the plurality of partial products (the third product)
Up to the digit of the first partial product at a position corresponding to the digit one digit lower than the code digit of the partial product of the first partial product and the sign digit of the first partial product. Setting a logical sum value with a code digit value, and setting the logical sum value and the third partial product in the first partial product digit at a position corresponding to the code digit position of the third partial product An exclusive OR value with the value of the sign digit of the third partial product is set. From the digit of the first partial product at a position corresponding to the position of the digit one digit higher than the sign digit of the third partial product, A function of setting a logical sum value of the logical sum value and the code digit value of the third partial product up to the digit of the first partial product at a position corresponding to the code digit position of the upper partial product An arithmetic processing unit comprising: 6. A multiplier for calculating a product of a multiplicand and a multiplier, each of which is a binary number represented by a two's complement, wherein the multiplier is configured to generate a plurality of encoded values from the multiplier. A plurality of partial product generators for generating a plurality of partial products, each of which is a binary number represented by a two's complement and having different weights, from the multiplicand and the plurality of encoded values; A partial product adder for adding the plurality of partial products, wherein the partial product adder includes a plurality of inputs and at least one output for carry-save addition of the plurality of partial products. A carry-save adder having the following formula: A plurality of digits, the first part A logic circuit for setting a plurality of logical operation values of the value of the sign digit of the partial product and the value of the sign digit of the other partial product, wherein, in the carry save adder, of the plurality of inputs, A particular input has a shorter propagation delay with respect to the output than at least one other input, and the first partial product sign-extended by the logic circuit is assigned to the particular input. A multiplier characterized by the above-mentioned. 7. The multiplier according to claim 6, wherein the first partial product sign-extended by the logic circuit is applied to an input exhibiting the shortest propagation delay between the first partial product and the output of the plurality of inputs. A multiplier characterized by being assigned. 8. The multiplier according to claim 6, wherein the logic circuit has a portion having the largest weight among the plurality of partial products from a digit one digit higher than the code digit of the first partial product. A multiplier having a function of determining each value up to the digit of the first partial product at a position corresponding to the position of the sign digit of the product (most significant partial product). 9. The multiplier according to claim 8, wherein the logic circuit assigns a second smallest weight among the plurality of partial products from a digit one digit higher than the code digit of the first partial product. The first partial product digit at a position corresponding to the digit position one digit lower than the sign digit of the partial product (second partial product)
The value of the sign digit of the first partial product is set in the digit of the first partial product at a position corresponding to the position of the sign digit of the second partial product. Setting an exclusive OR value with the value of the code digit of the second partial product; and setting the first partial product at a position corresponding to a position of a digit one digit higher than the code digit of the second partial product From the digit of the first partial product to the digit of the first partial product at a position corresponding to the position of the code digit of the most significant partial product.
A multiplier having a function of setting a logical sum value with a value of a sign digit of a partial product of. 10. The multiplier according to claim 8, wherein the logic circuit assigns a second smallest weight of the plurality of partial products from a digit one digit higher than the code digit of the first partial product. The first partial product digit at a position corresponding to the digit position one digit lower than the sign digit of the partial product (second partial product)
The value of the sign digit of the first partial product is set in the digit of the first partial product at a position corresponding to the position of the sign digit of the second partial product. Setting an exclusive OR value with the value of the code digit of the second partial product; and setting the first partial product at a position corresponding to a position of a digit one digit higher than the code digit of the second partial product , The partial product having the third smallest weight among the plurality of partial products (the third product)
Up to the digit of the first partial product at a position corresponding to the digit one digit lower than the code digit of the partial product of the first partial product and the sign digit of the first partial product. Setting a logical sum value with a code digit value, and setting the logical sum value and the third partial product in the first partial product digit at a position corresponding to the code digit position of the third partial product An exclusive OR value with the value of the sign digit of the third partial product is set. From the digit of the first partial product at a position corresponding to the position of the digit one digit higher than the sign digit of the third partial product, A function of setting a logical sum value of the logical sum value and the code digit value of the third partial product up to the digit of the first partial product at a position corresponding to the code digit position of the upper partial product A multiplier, comprising: