JPH1051811A - Method and device for adjusting stereoscopic effect - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust the stereoscopic effect of three-dimensional video by controlling the sharpness of the video by specific unit areas in one field image plane of the three-dimensional video according to information regarding distances of the video by the specific unit areas. SOLUTION: A stereoscopic effect adjusting circuit is equipped with a coefficient generating circuit 601 and a stereoscopic effect adjusting circuit 602 (603) for left (right) video. According to parallax information PR by pixels, the circuit 601 generates a 1st coefficient KL, a 2nd coefficient KH, and a 3rd coefficient KC. The coefficient KL is a coefficient for adjusting the rate of low-frequency components of video, i.e., a coefficient for blurring the outline of the video. The coefficient KH is a coefficient for adjusting the rate of high-frequency components of the video, i.e., a coefficient for increasing the sharpness of the outline. The coefficient KC is a coefficient for adjusting the chroma of the video. The coefficients KL and KH are supplied to a circuit 610 which adjusts the sharpness of the outline and processed as specified with a luminance signal YL, and an output YL-OUT is sent out. The coefficient KC, on the other hand, is supplied to a circuit 620 which adjusts the chroma and processed as specified with color difference signals (R-Y)L and (B-Y)L, and an output is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional effect adjusting method and a three-dimensional effect adjusting device for adjusting the three-dimensional effect of a three-dimensional image.

[0002]

2. Description of the Related Art Devices that provide a three-dimensional image by displaying a three-dimensional image signal comprising a left image and a right image having parallax on each other have been already developed. Further, an apparatus for generating a three-dimensional video signal from a two-dimensional video signal has already been developed.

[0003] However, a device capable of adjusting the stereoscopic effect of a stereoscopic image obtained by a three-dimensional video signal by processing the three-dimensional video signal in real time has not yet been developed.

[0004]

SUMMARY OF THE INVENTION The present invention provides a three-dimensional effect adjusting method and a three-dimensional effect capable of adjusting the three-dimensional effect of a three-dimensional image obtained by the three-dimensional image signal by processing the three-dimensional image signal in real time. It is an object to provide an adjusting device.

[0005]

According to a first stereoscopic effect adjusting method according to the present invention, a three-dimensional image is adjusted on the basis of information on the perspective of an image for each predetermined unit area in one field screen of a three-dimensional image.
The stereoscopic effect of the three-dimensional image is adjusted by controlling the sharpness of the outline of the image for each predetermined unit area of the three-dimensional image. The predetermined unit area is, for example, an area of one pixel unit.

More specifically, the sharpness of the outline of the image is increased in a region where a near image is projected, and the sharpness of the outline of the image is reduced in a region where a distant image is projected. Thus, the sharpness of the outline of the video is controlled. To the human eye, the closer the object is, the sharper the outline is, and the farther the object is, the more the outline is blurred, so that the stereoscopic effect of the image is emphasized.

A second method for adjusting a three-dimensional effect according to the present invention is as follows.
By controlling the saturation of the image for each predetermined unit area of the three-dimensional image based on information about the perspective of the image for each predetermined unit area in one field screen of the three-dimensional image, 3
It is characterized in that the stereoscopic effect of the two-dimensional image is adjusted. The predetermined unit area is, for example, an area of one pixel unit.

[0008] More specifically, the saturation of the image is increased in a region where a near image is reflected, and the saturation of the image is lowered in a region where a distant image is reflected.
The saturation of the video is controlled. To the human eye, the closer the object, the more vivid the color, and the farther the object, the lighter the color. This enhances the stereoscopic effect of the image.

A third stereoscopic effect adjusting method according to the present invention is as follows.
Controlling the sharpness of the outline of the image and controlling the saturation of the image for each predetermined unit area of the three-dimensional image based on information on the perspective of the image for each predetermined unit area within the one-field screen of the three-dimensional image. Thus, the stereoscopic effect of the three-dimensional image is adjusted. The predetermined unit area is, for example, an area of one pixel unit.

[0010] More specifically, the sharpness of the outline of the image is increased in a region where a near image is projected, and the sharpness of the outline of the image is reduced in a region where a distant image is projected. As described above, the sharpness of the outline of the image is controlled, and the saturation of the image is reduced in the region where a distant image is reflected, as the saturation of the image is increased in the region where a close image is reflected. Thus, the saturation of the video is controlled. The closer to the human eye, the sharper the outline and the more vivid the color, and the farther the object is, the more the outline appears blurred and the color looks paler, so that the stereoscopic effect of the image is emphasized.

A first three-dimensional effect adjusting device according to the present invention is:
Contour control means for controlling the sharpness of the contour of the video for each predetermined unit area of the three-dimensional video based on information about the perspective of the video for each predetermined unit area in one field screen of the three-dimensional video It is characterized by. The predetermined unit area is, for example, an area of one pixel unit.

[0012] The contour control means may include, for example, a sharpness of the outline of the image in a region where a distant image is projected so that the sharpness of the outline of the image is high in a region where a near image is projected. Is used to control the sharpness of the outline of the video so that the image quality is reduced. To the human eye, the closer the object, the more vivid the color, and the farther the object, the lighter the color. This enhances the stereoscopic effect of the image.

As a specific example of such a contour control means, for a region where a near image is reflected, the ratio of the low frequency component of the image is reduced and the ratio of the high frequency component of the image is increased. As for the area where is displayed, there is one that increases the ratio of the low frequency component of the video and decreases the ratio of the high frequency component of the video.

A second three-dimensional effect adjusting device according to the present invention is:
The image processing apparatus further includes a saturation control unit configured to control the saturation of the image for each of the predetermined unit regions of the three-dimensional image based on information about the perspective of the image for each of the predetermined unit regions in the one-field screen of the three-dimensional image. Features. The predetermined unit area is, for example, an area of one pixel unit.

As the saturation control means, for example, the saturation of a video is increased in a region where a distant video is displayed, while the saturation of the video is lowered in a region where a near video is displayed. As described above, one that controls the saturation of an image is used. To the human eye, the closer the object, the more vivid the color, and the farther the object, the lighter the color. This enhances the stereoscopic effect of the image.

A third three-dimensional effect adjusting device according to the present invention is:
Contour control means for controlling the sharpness of the contour of the image for each predetermined unit area of the three-dimensional image based on information about the perspective of the image for each predetermined unit area within one field screen of the three-dimensional image; 3 based on the information about the perspective of the video for each predetermined unit area in the one-field screen
The image processing apparatus further includes a saturation control unit that controls the saturation of the image for each predetermined unit area of the two-dimensional image. The predetermined unit area is, for example, an area of one pixel unit.

The contour control means may include, for example, the definition of the contour of the image is increased so that the definition of the contour of the video is high in the region where the near image is reflected. Is controlled so as to reduce the sharpness of the outline of the image. As the saturation control means, for example, for a region where a close image is shown,
A device that controls the saturation of an image is used such that the saturation of the image is high and the saturation of the image is low in a region where a distant image is reflected.

The closer to the human eye, the sharper the outline and the more vivid the color, and the farther the object, the more the outline appears blurred and the color appears lighter, so that the stereoscopic effect of the image is emphasized.

As a specific example of such a contour control means, for a region where a near image is reflected, the ratio of the low-frequency component of the image is reduced and the ratio of the high-frequency component of the image is increased, so that the distant image is reduced. As for the area where is displayed, there is one that increases the ratio of the low frequency component of the video and decreases the ratio of the high frequency component of the video.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

[1] Description of First Embodiment of the Invention

First, an embodiment in which the present invention is applied to a 2D / 3D video conversion system will be described.

[1-1] Description of overall configuration of 2D / 3D video conversion system.

FIG. 1 shows the configuration of a 2D / 3D video conversion system.

The 2D / 3D video conversion system converts a 2D / 3D video signal obtained by the 2D / 3D video conversion device 501 and a 2D / 3D video conversion device 501 for converting a 2D video into a 3D video. A three-dimensional effect adjusting circuit 502 for adjusting the three-dimensional effect is provided.

The 2D / 3D video converter 501 has a luminance signal Y-IN and a color difference signal (R
-Y) -IN and a color difference signal (BY) -IN. The 2D / 3D video converter 501 outputs a luminance signal YL, a chrominance signal (RY) L and a chrominance signal (BY) L constituting a left video signal, a luminance signal YR constituting a right video signal, and a chrominance signal. Signal (RY) R and the color difference signal (B-
Y) Output R and parallax information PR for each pixel.

Each output signal of the 2D / 3D video converter 501 is sent to a stereoscopic effect adjusting circuit 502. From the three-dimensional effect adjustment circuit 502, a luminance signal YL-OUT, a color difference signal (RY) L-OUT and a color difference signal (BY) L-OUT, which constitute the left video signal after the three-dimensional effect adjustment, and a three-dimensional effect. The luminance signal YR-OUT, the color difference signal (RY) R-OUT, and the color difference signal (BY) RO constituting the adjusted right video signal
UT and are output.

[1-2] 2D / 3D Video Converter 501
Description

As the 2D / 3D video converter 501,
For example, a first 2D / 3D video converter, a second 2D / 3D video converter, and the like described below are used.

[1-2-1] Description of First 2D / 3D Video Converter

FIG. 2 shows the overall configuration of the first 2D / 3D video converter.

The luminance signal Y, the color difference signal RY, and the color difference signal BY constituting the two-dimensional video signal are converted by the AD conversion circuit 1
(ADC), the digital Y signal, R-
It is converted into a Y signal and a BY signal.

The Y signal is sent to a luminance integrating circuit 7, a high-frequency component integrating circuit 8, and a luminance contrast calculating circuit 9, and is sent to a first left image arbitrary pixel delay FIFO 11 and a first right image arbitrary pixel delay FIFO 21. Sent. The RY signal is sent to the saturation integration circuit 10 and also sent to a second left image arbitrary pixel delay FIFO 12 and a second right image arbitrary pixel delay FIFO 22. B
The −Y signal is sent to the saturation integration circuit 10 and sent to the third left image arbitrary pixel delay FIFO 13 and the third right image arbitrary pixel delay FIFO 23.

The luminance integrating circuit 7 calculates, for each field, a luminance integrated value for each of a plurality of parallax calculation areas E1 to E12 set in advance in one field screen as shown in FIG. The high-frequency component integrating circuit 8 calculates an integrated value of a high-frequency component for each of the parallax calculation areas E1 to E12 for each field. The brightness contrast calculation circuit 9 calculates each parallax calculation area E1 for each field.
The brightness contrast for each of E12 to E12 is calculated. The saturation integration circuit 10 calculates an integrated value of saturation for each of the parallax calculation areas E1 to E12 for each field.

The luminance integrated value for each of the parallax calculation areas E1 to E12, the integrated value of the high frequency component for each of the parallax calculation areas E1 to E12, and the respective parallax calculation areas E1 to E1
The integrated values of the luminance contrast for each of the two and the saturation for each of the parallax calculation regions E1 to E12 are image feature amounts relating to the perspective of the video for each of the parallax calculation regions E1 to E12.

Note that a total of 60 parallax calculation areas of 6 rows and 10 columns are actually set in the one-field screen as shown in FIG. 16, but for convenience of explanation, as shown in FIG. It is assumed that a total of 12 parallax calculation areas E1 to E12 of 3 rows and 4 columns are set in one field screen.

The CPU 3 generates parallax information for each of the parallax calculation areas E1 to E12 based on the information transmitted from the luminance integration circuit 7, the high-frequency component integration circuit 8, the luminance contrast calculation circuit 9 and the saturation integration circuit 10. I do. In this example, the parallax information is generated such that the front-side object such as the subject has a smaller parallax amount, and the back-side object such as the background has a larger parallax amount. The details of the method of generating the parallax information will be described later.

The parallax information for each of the parallax calculation areas E1 to E12 calculated by the CPU 3 is sent to the parallax control circuit 4. The parallax control circuit 4 controls the parallax calculation areas E1 to E
On the basis of the disparity information for No. 12, disparity information for each pixel position in each field (information regarding the perspective of an image for each predetermined unit area) is generated. Then, based on the obtained parallax information for each pixel position, each of the FIFOs 11 to 13,
Video signals (Y signal, RY signal, BY
Signal), the read addresses are arbitrary pixel delay FIFOs 11 to 13 for the left image and arbitrary pixel delay F for the right image.
Each of the FIFOs 1 to 23 is shifted from the FIFOs 21 to 23.
Read addresses 1 to 13 and 21 to 23 are controlled.
Therefore, the left image arbitrary pixel delay FIFOs 11 to 13
, And the horizontal phase of the right video signal read from the right video arbitrary pixel delay FIFOs 21 to 23 becomes different.

Left image arbitrary pixel delay FIFOs 11 to 13
From the left video signal (YL signal, (RY) L
Signal, (BY) L signal) is a DA conversion circuit (DAC)
After being converted into an analog signal by 5, the signal is sent to a three-dimensional display device (not shown) via a three-dimensional effect adjustment circuit 502.
The right video signal (YR signal, (RY) R signal, (B-
Y) R signal) is converted into an analog signal by a DA conversion circuit (DAC) 6, and then sent to a stereoscopic display device (not shown) via a stereoscopic effect adjustment circuit 502.

Since the horizontal phase of the left video signal is different from the horizontal phase of the right video signal, a parallax occurs between the left video and the right video. As a result, the left image is observed only with the left eye,
When the right image is observed only with the right eye, a three-dimensional image in which the subject is located in front of the background is obtained.

FIG. 4 shows the configuration of the luminance integrating circuit 7.

In FIG. 3, each of the parallax calculation areas E1 to E
12, the number of pixels in the horizontal direction is m, and each of the parallax calculation areas E1 to E
12, the number of pixels in the vertical direction is n, and the first parallax calculation area E1
The horizontal position (HAD), where the coordinates of the upper left of
And the vertical position (VAD).

The luminance integrating circuit 7 includes a timing signal generating circuit 201, an adding circuit 202, and a luminance integrating register group 2.
03 and a selection circuit (SEL) 204. The luminance integration register group 203 stores the parallax calculation areas E1 to E1.
2 are provided with first to twelfth luminance integrating registers 211 to 222 respectively corresponding to the two.

The timing signal generating circuit 201 receives a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync of the input video signal and a clock signal CLK for detecting a horizontal address in each horizontal period.

The timing signal generation circuit 201 outputs first to twelfth enable signals EN1 to EN12, a reset signal RST and an output timing signal DOUT based on the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the clock signal CLK. .

Each of the enable signals EN1 to EN12 corresponds to each of the parallax calculation regions E1 to E12, and is always at the L level. Level. The first to twelfth enable signals EN1 to EN12 are input as write signals to the first to twelfth luminance integration registers 211 to 222, respectively. Further, the first to twelfth enable signals EN1 to EN12 are also sent to the selection circuit 204. The selection circuit 204 selects and outputs input data corresponding to the H-level enable signal.

The reset signal RST is output at the effective video start timing of each field in the input video signal, and is sent to each of the luminance integration registers 211 to 222. A reset signal RST is sent to each of the brightness integration registers 211 to 222.
Is input, the content is set to 0.

As shown in FIG. 3, the output timing signal DOUT is at the H level for a certain period from the time when the vertical position of the input video signal exceeds the vertical position at the lower end of the lowermost parallax calculation area E12. Output timing signal DOUT
Is sent to the CPU 3.

A reset signal is output at the effective video start timing of the input video signal,
The contents of 11 to 222 are set to 0. When the horizontal / vertical position of the input video signal is within the first parallax calculation area E1,
Since the first enable signal EN1 is at the H level, the luminance value held in the first luminance integration register 211 is sent to the addition circuit 202 via the selection circuit 204, and the Y signal in the input video signal is added. Input to the circuit 202.

Therefore, the first luminance integrating register 21
1 and the Y value in the input video signal.
The signal and the signal are added by the adding circuit 202, and the result of the addition is stored in the first luminance integration register 211. That is, when the horizontal and vertical positions of the input video signal are within the first parallax calculation area E1, the first parallax calculation area E1
The luminance values of the pixels within are accumulated, and the accumulation result is accumulated in the first luminance accumulation register 211.

In this manner, each of the parallax calculation areas E1 to E
The brightness integration value for each of the 12 is stored in the corresponding brightness integration register 2
11 to 222. When the output timing signal DOUT becomes H level, each of the brightness integration registers 2
Each of the parallax calculation areas E1 to E stored in 11 to 222
The integrated luminance value for each of the CPUs 12 is sent to the data bus (DA
TA-BUS).

FIG. 5 shows the configuration of the high frequency component integrating circuit 8.

The high-frequency component integrating circuit 8 includes a timing signal generating circuit 231, a high-pass filter (HPF) 232,
An absolute value conversion circuit 233, a slice processing circuit 234, an addition circuit 235, a high frequency component integration register group 236, and a selection circuit 237 are provided. The high-frequency component accumulation register group 236 includes first to twelfth high-frequency component accumulation registers 241 to 241 corresponding to the parallax calculation areas E1 to E12, respectively.
252.

The input signal and the output signal of the timing signal generation circuit 231 correspond to the timing signal generation circuit 20 shown in FIG.
1 is the same as the input signal and the output signal.

As the high-pass filter 232, for example, as shown in FIG.
A high-pass filter having tap coefficients of −1, 0, 2, 0 and −1 including a bit shift circuit 266 for obtaining an output twice as large as the input value, an adder 267 and a subtractor 268 is used. Can be

Further, as the slice processing circuit 234,
A circuit having input / output characteristics as shown in FIG. 7 is used. The output is set to 0 for inputs from 0 to Ia in order to prevent noise from being extracted as a high-frequency component.

Therefore, the high-frequency component of the Y signal in the input video signal is extracted by the high-pass filter 232, the absolute value is obtained by the absolute value circuit 233, and the slice processing circuit 234 removes noise from the absolute value of the high-frequency component. You.

A reset signal is output at the effective video start timing of the input video signal, and the contents of each of the high frequency component integration registers 241 to 252 are set to 0. When the horizontal / vertical position of the input video signal is within the first parallax calculation area E1, the first enable signal EN1 is at the H level, so that the high-frequency component held in the first high-frequency component integration register 241 is stored. Is added through the selection circuit 237 to the addition circuit 23.
5 and the high frequency component of the Y signal in the input video signal (the output of the slice processing circuit 234) is input to the addition circuit 235.

Therefore, the high-frequency component held in the first high-frequency component integration register 241 and the high-frequency component of the Y signal in the input video signal are added by the addition circuit 235, and the addition result is added to the first high-frequency component integration. It is stored in the register 241. That is, when the horizontal and vertical positions of the input video signal are within the first parallax calculation area E1, the high-frequency components of the pixels in the first parallax calculation area E1 are integrated, and the integration result is the first. It is stored in the high frequency component integration register 241.

In this manner, the parallax calculation areas E1 to E
The integrated value of the high frequency component for each 12 is stored in the corresponding high frequency component integration register 241. When the output timing signal DOUT becomes H level, the integrated value of the high frequency component for each of the parallax calculation areas E1 to E12 stored in each of the high frequency component integration registers 241 to 252 is determined by the CPU.
3 via the data bus.

FIG. 8 shows another example of the high frequency component integrating circuit 8.

The high-frequency component integrating circuit 8 includes a timing signal generating circuit 238, a high-pass filter 232, a peak detecting circuit 239, an adding circuit 235, a high-frequency component integrating register group 236, and a selecting circuit 237.

The timing signal generation circuit 238 is almost the same as the timing signal generation circuit 201 of FIG. 4, but as shown in FIG. 3, the horizontal position of the input video signal is set immediately before the parallax calculation areas E1, E5, E9. 4 is different from the timing signal generating circuit 201 in FIG. 4 in that a trigger pulse (region boundary signal RST1) is output when the horizontal position of the image and the horizontal position at the end of each of the parallax calculation regions E1 to E12 are reached. . The region boundary signal RST1 is supplied to the peak detection circuit 23
9

The high frequency component of the Y signal extracted by the high pass filter 232 is sent to a peak detection circuit 239. The peak detection circuit 239 controls each of the parallax calculation areas E1 to E1.
The maximum value of the high frequency component is detected for each horizontal line in E12. As shown in FIG. 9, the peak detection circuit 239 includes a comparison circuit 271, a maximum value register 272, and a gate 273. FIG. 10 shows a horizontal synchronizing signal Hsync of an input video signal and a region boundary signal R.
The output of ST1, the gate 273, etc. is shown.

The maximum value register 272 includes a high-frequency component of the Y signal extracted by the high-pass filter 232, an area boundary signal RST 1, and a determination result signal L of the comparison circuit 271.
a and the clock signal CLK are input. Comparison circuit 2
71 compares the output of the maximum value register 272 with the high frequency component of the Y signal in the input video signal, and when the high frequency component of the Y signal is larger than the output of the maximum value register 272,
The determination result signal La is set to the H level.

When the region boundary signal RST1 goes high, the contents of the maximum value register 272 are set to zero. If the determination result signal L1 from the comparison circuit 271 is at the H level while the region boundary signal RST1 is at the L level,
The high frequency component of the Y signal is stored in the maximum value register 272. That is, the contents of the maximum value register 272 are updated. Therefore, the maximum value register 272 stores the parallax calculation areas E1 to E12 corresponding to the horizontal and vertical positions of the input video signal every time the area boundary signal RST1 is at the L level.
The maximum value of the high frequency components of the Y signal for each pixel of one horizontal line is stored.

Gate 273 outputs the output value of maximum value register 272 when region boundary signal RST1 attains H level, and outputs 0 when region boundary signal RST1 is at L level. That is, every time the region boundary signal RST1 becomes H level, the gate circuit 273 outputs the predetermined parallax calculation regions E1 to E1 stored in the maximum value register 272.
The maximum value of the high frequency component of the Y signal for one horizontal line in 2 is output. Therefore, the integrated value of the maximum value of the high frequency component of the Y signal for each horizontal line in the corresponding parallax calculation area is accumulated in each of the high frequency component integration registers 241 to 252 (see FIG. 8).

FIG. 11 shows the configuration of the luminance contrast calculation circuit 9.

The luminance contrast calculation circuit 9 includes a timing signal generation circuit 301 and a luminance contrast detection circuit group 302. Brightness / contrast detection circuit group 3
02 denotes first to twelfth luminance contrast detection circuits 311 to 311 corresponding to the parallax calculation areas E1 to E12, respectively.
22.

The input signal and the output signal of the timing signal generation circuit 301 correspond to the timing signal generation circuit 20 shown in FIG.
1 is the same as the input signal and the output signal.

Each of the luminance contrast detection circuits 311 to 32
2, includes a first comparison circuit 331, a maximum value register 332, a second comparison circuit 333, a minimum value register 334, and a subtractor 335, as shown in FIG.

The maximum value register 332 stores the Y signal in the input video signal and the enable signal EN (N = 1, N = 1, E2) in the areas E1 to E12 corresponding to the luminance contrast detection circuit.
2... 12), reset signal RST, first comparison circuit 33
1 and the clock signal CL
K is input. The first comparison circuit 331 compares the output value of the maximum value register 332 with the Y signal of the input video signal, and when the Y signal of the input video signal is larger than the output value of the maximum value register 332, sets the determination signal Lb to H. To level.

When the reset signal RST goes high,
The contents of the maximum value register 332 are set to 0. The enable signals EN of the areas E1 to E12 corresponding to the luminance contrast detection circuit are at the H level and the determination signal Lb is at the H level.
When the signal is at the level, the Y signal is stored in the maximum value register 332. That is, the contents of the maximum value register 332 are updated. Therefore, immediately before the output timing signal DOUT is output, the maximum value register 332 stores the parallax calculation area E corresponding to the luminance contrast detection circuit.
The maximum value of the luminance values of the pixels in 1 to E12 is accumulated.

The minimum value register 334 stores the Y signal of the input video signal and the enable signal EN (N = 1, N = 1, E2) in the areas E1 to E12 corresponding to the luminance contrast detection circuit.
2... 12), reset signal RST, second comparison circuit 33
3 and the clock signal CL output from
K is input. The second comparison circuit 334 compares the output value of the minimum value register 334 with the Y signal of the input video signal, and when the Y signal of the input video signal is smaller than the output value of the minimum value register 334, sets the determination signal Lc to H. To level.

When the reset signal RST goes high,
A predetermined maximum value is set in the minimum value register 334. When the enable signals EN of the areas E1 to E12 corresponding to the luminance contrast detection circuit are at the H level and the determination signal Lc is at the H level, the Y signal is stored in the minimum value register 334. That is, the minimum value register 3
34 is updated. Therefore, immediately before the output timing signal DOUT is output, the minimum value of the luminance values of the pixels in the parallax calculation areas E1 to E12 corresponding to the luminance contrast detection circuit is accumulated in the minimum value register 334. You.

As a result, at the point in time when the output timing signal DOUT is output, the output of the subtracter 335 is the difference between the maximum value and the minimum value of the luminance values of the pixels in the corresponding parallax calculation areas E1 to E12. The value corresponds to the difference (luminance contrast). Then, the output timing signal DOUT
Is output, the output (luminance contrast) of the subtractor 335 is sent to the CPU 3.

FIG. 13 shows the structure of the saturation accumulating circuit 10.

The saturation integration circuit 10 includes a timing signal generation circuit 341, a saturation calculation circuit 342, an addition circuit 343, a saturation integration register group 344, and a selection circuit 345. The saturation integration register group 344 stores the parallax calculation areas E
There are first to twelfth saturation integration registers 351 to 362 corresponding to 1 to E12, respectively.

The input signal and the output signal of the timing signal generation circuit 341 are the same as those of the timing signal generation circuit 20 shown in FIG.
1 is the same as the input signal and the output signal.

The saturation calculation circuit 342 sets the value of the RY signal in the input video signal to (RY) and the value of the BY signal in the input video signal to (BY), and calculates the following equation (1).
To obtain the value SAI corresponding to the saturation.

[0081]

(Equation 1)

A reset signal RST is output at the effective video start timing of the input video signal, and the contents of the saturation integration registers 351 to 362 are set to 0. When the horizontal / vertical position of the input video signal is within the first parallax calculation area E1, the first enable signal EN1 is at the H level, and thus the saturation held in the first saturation integration register 351 is stored. Is sent to the addition circuit 343 via the selection circuit 345, and the saturation calculated by the saturation calculation circuit 342 is input to the addition circuit 343.

Therefore, the first saturation integration register 35
The saturation held at 1 and the saturation calculated by the saturation calculation circuit 342 are added by the addition circuit 343, and the addition result is stored in the first saturation integration register 351. That is, the horizontal and vertical positions of the input video signal
Is within the parallax calculation area E1, the saturation of the pixels in the first parallax calculation area E1 is accumulated, and the accumulation result is accumulated in the first saturation accumulation register 351.

Thus, the parallax calculation areas E1 to E
The integrated value of the saturation for each 12 is stored in the corresponding saturation integration registers 351 to 362. When the output timing signal DOUT becomes H level, the parallax calculation areas E1 to E1 stored in the saturation integration registers 351 to 362 are stored.
The integrated value of the saturation for each E12 is sent to the CPU 3 via the data bus.

FIG. 14 shows a method of calculating the amount of parallax performed by the CPU 3.

The first normalizing means 401 normalizes the integrated value of the high frequency component for each of the parallax calculation areas E1 to E12 to a value in the range of 0 to 10. The second normalization unit 402 sets the luminance contrast of each of the parallax calculation areas E1 to E12 to 0.
Normalize to a value in the range of -10. Third normalizing means 40
3 normalizes the integrated luminance value for each of the parallax calculation areas E1 to E12 to a value in the range of 0 to 10. Fourth normalizing means 4
A step 04 normalizes the saturation integration value for each of the parallax calculation areas E1 to E12 to a value in a range of 0 to 10.

Each normalized parallax calculation area E1 to E12
The integrated value of the high-frequency component for each is multiplied by the coefficient K1 by the multiplying unit 405 and then sent to the adding unit 409. The normalized luminance contrast for each of the parallax calculation areas E1 to E12 is added to the coefficient K2 by the multiplication unit 406.
Are accumulated and sent to the adding means 409. After the coefficient K3 is multiplied by the multiplication means 407 to the normalized luminance integrated value for each of the parallax calculation areas E1 to E12,
It is sent to the adding means 409. The normalized saturation integrated value for each of the parallax calculation areas E1 to E12 is multiplied by a multiplication unit 408.
After the coefficient K4 is integrated by the above, it is sent to the adding means 409.

As specific examples of the coefficients K1, K2, K3, K4, K1 = 0.6, K2 = 0.2, K3 = 0.1, K3
4 = 0.1. Also, K1 = 0.75, K2
= 0.25, K3 = 0.0, K4 = 0.0.

By controlling the set values of these coefficients K1 to K4, any one or any combination selected from the integrated value of the high-frequency component, the luminance contrast, the integrated value of the luminance and the integrated value of the saturation can be obtained. , Can be used as an image feature amount related to the perspective of a video.

Therefore, only the integrated value of the high-frequency component can be used as the image feature amount relating to the perspective of the video. It is also possible to use only the luminance contrast as the image feature amount relating to the perspective of the video. The integrated value of the high-frequency component and the luminance contrast may be used as the image feature amount relating to the perspective of the video. An integrated value of a high-frequency component, a luminance contrast, and a luminance integrated value can also be used as the image feature amount relating to the perspective of a video. The integrated value of the high-frequency component, the luminance contrast, and the integrated value of the saturation can also be used as the image feature amount related to the perspective of the video.
The integrated value of the high-frequency component, the luminance contrast, the integrated luminance value, and the integrated chroma value can also be used as the image feature amount relating to the perspective of the video.

In the adding means 409, each of the multiplying means 405
The values for each of the parallax calculation areas E1 to E12 obtained by 408 are added. The value for each of the parallax calculation areas E1 to E12 obtained by the adding unit 409 is normalized by the fifth normalizing unit 410 to a value in the range of 0 to 10 (hereinafter, referred to as depth information). FIG.
9 shows the relationship between the output value of the value 09 and the depth information obtained by the fifth normalization means 410. Each parallax calculation area E
Depth information for each of E1 to E12 is used as a parallax calculation area E1 to E12.
This is information on the distance of the video for each of the twelve. Each of the parallax calculation areas E1 to E5 obtained by the fifth normalization unit 410
The depth information for each E12 is sent to the depth correction unit 411.

In a general image, a subject exists in the front and a background exists in the rear. Also, since there are many images that are in focus with respect to the subject, it is considered that the closer the object is, the higher the high-frequency component, contrast, brightness, and saturation are. Therefore, in the present embodiment, it is assumed that an object in front of an area where the integrated value of the high-frequency component, the luminance contrast, the integrated value of the luminance, and the integrated value of the saturation are larger is captured.

Therefore, it can be determined that the region where the depth information obtained by the adding means 409 is larger is the region where the object existing ahead is captured. When the stereoscopic position of the region in which the object present in the forefront is captured is set as the tube position of the stereoscopic display device, the depth information obtained by the adding unit 409 is inversely proportional to the depth from the tube position.

Hereinafter, the depth correction processing by the depth correction means 411 will be described.

It is easier to understand the depth correction processing by taking the actually set parallax calculation area as an example. Therefore, the 60 parallax calculation areas actually set for one field will be explained. The depth correction processing by the depth correction unit 411 will be described. FIG.
Indicates 60 parallax calculation areas F1 to F60 actually set for one field.

First, an average value of depth information is calculated for each row of the parallax calculation areas F1 to F60. When the depth information for each of the parallax calculation areas F1 to F60 has a value as shown in FIG. 17, the average value of the depth information for each of the first to sixth rows is 1.2, 3.6, 6.0, 7.2, 4.
0 and 1.2.

Next, from each row of the parallax calculation area, an area where many objects at the near position are reflected is extracted. That is,
The row having the largest average value of the depth information is extracted. FIG.
In the example of 7, the area of the fourth row is extracted.

Next, with respect to each area of the row below the extracted row, each area of the row below the extracted row is compared with the area immediately above so that the depth information does not suddenly decrease. Is adjusted. In particular,
For an area in which the depth information of each area in the row below the extracted row is smaller than the area immediately above by 3 or more, the depth information of the area is set to a value smaller by 2 than the depth information of the area immediately above. Can be changed.

In the example of FIG. 17, as shown in FIG. 18, first, among the regions F41 to F50 in the fifth row, regions F42 to F49 whose depth information is smaller than the depth information of the region immediately above by three or more. , The depth information is corrected.
Thereafter, the depth information is corrected for the regions F53 to F58 of the regions F51 to F60 in the sixth row whose depth information is smaller than the depth information (corrected depth information) of the region immediately above by three or more. Is done.

That is, when the relationship of the depth information with respect to the screen height at an arbitrary horizontal position is a relationship as shown by the curve U1 in FIG. 19, the relationship between the depth information and the screen height is corrected by the depth correction. However, FIG.
The correction is made so as to have the relationship shown in FIG.

As described above, among the rows in the parallax calculation area,
The reason that the depth information of the area below the area where many objects at the near position are reflected is corrected for the following reason.

In general, an object existing in front is often displayed on the lower side of the screen. Further, the object reflected on the lower side of the screen is often an image with little change such as the ground. An image with little change, such as the ground, has a low high-frequency component, so that the value of the depth information is small even though it is ahead. Therefore, depth information is increased by depth correction so that the depth information of an image located in front of the object and having a low high-frequency component is not larger than the value of the depth information of the area immediately above the image.

Depth information for each area (actually F1 to F60, but E1 to E12 for convenience of explanation) whose depth information has been corrected by the depth correction means 411 is as follows.
The renormalization means 412 normalizes the data within the range of 0 to 10. The depth information for each of the areas E1 to E12 obtained by the re-normalization means 412 is
13 is converted into parallax information for each of the regions E1 to E12.

The parallax information determining means 413 converts the depth information into parallax information for each of the regions E1 to E12 based on the relationship between the predetermined depth information and the parallax information. The relationship between depth information and disparity information is shown in FIG.
Are inversely proportional as shown by the straight line S1 or S2.

In FIG. 20, the relationship between the depth information indicated by the straight line S1 and the parallax information is used when a stereoscopic image having a relatively strong stereoscopic effect is desired to be obtained. The relationship between the depth information indicated by the straight line S2 and the parallax information is used when it is desired to obtain a stereoscopic image having a relatively weak stereoscopic effect. The relationship between the depth information and the parallax information is represented by a straight line S1 and a straight line S2.
It is possible to adjust the three-dimensional effect by adjusting between.

Each of the regions E1 to E1 thus obtained
The disparity information for each 2 is sent to the disparity control circuit 4 (see FIG. 2). Note that the depth correction by the depth correction unit 411 may be omitted.

FIG. 21 mainly shows the configuration of the parallax control circuit and the arbitrary pixel delay FIFO shown in FIG.

FIG. 21 shows an arbitrary pixel delay FIFO 11 to 11.
13, 21 to 23, left image arbitrary pixel delay FIFO 11 and right image arbitrary pixel delay FI for Y signal
Although only FO21 is shown, other arbitrary pixel delays FI
FO12, 13, 22, and 23 have the same configuration and perform the same control, so that other arbitrary pixel delay FIFOs
Descriptions of the configurations and control methods of 12, 13, 22, and 23 are omitted.

The disparity information calculated by the CPU 3 is disparity information for the center position of each of the disparity calculation areas E1 to E12. The parallax control circuit 4 obtains parallax information for each pixel position on a one-field screen based on the parallax information for the center position of each of the parallax calculation areas E1 to E12. Then, in order to generate a left image and a right image having parallax corresponding to the parallax information for the pixel position from the two-dimensional video signal for each pixel position, an arbitrary left video image is generated based on the parallax information for each pixel position. Pixel delay F
IFO 11-13 and right pixel arbitrary pixel delay FIFO
The read addresses 21 to 23 are controlled.

The parallax information for each pixel position in one field screen is obtained by a timing signal generation circuit 51, a parallax interpolation coefficient generation circuit 52, a parallax information storage means 60, and a parallax selection circuit 8.
0, and is generated by the first to fourth multipliers 81 to 84 and the addition circuit 85.

The horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync of the input video signal are input to the timing signal generating circuit 51. Further, a clock signal CLK for detecting a horizontal address in each horizontal period is also input to the timing signal generation circuit 51.

The timing signal generating circuit 51 generates a horizontal address signal HAD representing an absolute horizontal position of an input video signal and an absolute vertical position of the input video signal based on the horizontal synchronizing signal Hsync, the vertical synchronizing signal Vsync and the clock signal CLK. And a relative horizontal position signal HPOS representing the relative horizontal position of the input video signal.
And a relative vertical position signal VPOS indicating the relative vertical position of the input video signal is generated and output.

The relative horizontal position and the relative vertical position of the input video signal will be described.

As shown in FIG. 22, the parallax calculation areas E1 to E12 in FIG. 3 are set as follows. The entire screen is divided into 20 regions of 4 rows and 5 columns (hereinafter, referred to as a first divided region) as shown by a dotted line in FIG. Then, a quadrangular area having four vertices at the center of the first divided area at the upper left, the center of the first divided area at the upper right, the center of the first divided area at the lower left, and the center of the first divided area at the lower right is 3 Row 4
The column is divided into 12 regions (hereinafter, referred to as second divided regions), and each of the second divided regions is set as parallax calculation regions E1 to E12.

The number of pixels in the horizontal direction of the first divided region and the second divided region is represented by m, and the number of pixels of the first divided region and the second divided region in the vertical direction is represented by n. The relative horizontal position of the input video signal is represented by 0 to (m-1), with the left end of each first divided area being 0 and the right end being m.
The relative vertical position of the input video signal is represented by 0 to (n-1), with the upper end of each first divided area being 0 and the lower end being n.

Relative horizontal position signal HPO of input video signal
S and the relative vertical position VPOS are sent to the parallax interpolation coefficient generation circuit 52. The parallax interpolation coefficient generation circuit 52 generates a first parallax interpolation coefficient KUL based on the relative horizontal position signal HPOS, the relative vertical position VPOS, and the following equation (2).
A second parallax interpolation coefficient KUR, a third parallax interpolation coefficient KDL, and a fourth parallax interpolation coefficient KDR are generated and output.

[0117]

(Equation 2)

FIG. 2 shows the basic concept of a method of generating disparity information for each pixel position on a one-field screen.
3 will be described. It is assumed that the horizontal / vertical position (hereinafter, referred to as a target position) represented by the horizontal address signal HAD and the vertical address signal VAD is Pxy in FIG. A case where parallax information for the target position Pxy is obtained will be described.

(1) First, from the parallax information for each of the parallax calculation areas E1 to E12 calculated by the CPU 3, four vertices of the first divided area including the target position Pxy,
In this example, disparity information for the disparity calculation areas E1, E2, E5, and E6 centered on PE1, PE2, PE5, and PE6 is extracted as UL, UR, DL, and DR, respectively. That is, of the four vertices of the first divided region including the target position Pxy, the disparity information of the region E1 centered on the upper left vertex is the first disparity information UL, and the disparity information of the region E2 centered on the upper right vertex is UL. Is extracted as the second disparity information UR, the disparity information of the region E5 centered on the lower left vertex is extracted as the third disparity information DL, and the disparity information of the region E6 centered on the lower right vertex is extracted as the fourth disparity information DR. You.

However, as in the case where the first divided area including the target position is the first divided area at the upper left corner, only one vertex of the four vertices of the first divided area including the target position is disparity. If the parallax information corresponds to the center of the detection area, the parallax information of the parallax calculation area is the first to fourth parallax information U
Extracted as L, UR, DL, DR.

Further, as in the case where the first divided area including the target position is the first divided area to the right of the first divided area at the upper left corner, the four vertices of the first divided area including the target position are used. If only the lower two vertices of the first divided area correspond to the center of the parallax calculation area, the parallax information UL corresponding to the upper two vertices of the four vertices of the first divided area including the target position, As the UR, parallax information of a parallax calculation area centered on the lower vertex is extracted.

Also, as in the case where the first divided region including the target position is the first divided region below the first divided region at the upper left end, the four vertices of the first divided region including the target position are used. Among the four vertices of the first divided area including the position of interest, only the two vertices on the right correspond to the center of the parallax calculation area. , The parallax information of the parallax calculation area centered on the right vertex is extracted.

Also, as in the case where the first divided area including the target position is the first divided area on the left side of the first lower right divided area, the four vertices of the first divided area including the target position are used. If only the upper two vertices of the first divisional area correspond to the center of the parallax calculation area, the parallax information DL corresponding to the lower two vertices of the four vertices of the first divided area including the target position, As DR, parallax information of a parallax calculation area centered on the upper vertex is extracted.

Further, as in the case where the first divided region including the target position is the first divided region above and above the first divided region at the lower right, four vertices of the first divided region including the target position are used. Among the four vertices of the first divided area including the target position, only the two vertexes on the left side of the parallax calculation area correspond to the center of the parallax calculation area. , The parallax information of the parallax calculation area centered on the left vertex is extracted.

(2) Next, the first to fourth parallax interpolation coefficients K
UL, KUR, KDL and KDR are required.

The first parallax interpolation coefficient KUL is determined by the target position P
xy, the distance ΔX from the target position Pxy to the right side of the first divided area e with respect to the horizontal width m of the first divided area e including xy
R and the ratio {(m-HPOS) / m} to the first divided region e
の (n−VPO) of the vertical width n to the distance ΔYD from the target position Pxy to the lower side of the first divided region e.
S) / n}. That is, the first
Is larger as the distance between the upper left vertex PE1 of the first divided area e including the target position Pxy and the target position Pxy is smaller.

The second parallax interpolation coefficient KUR is determined by the target position P
xy, the distance ΔX from the target position Pxy to the left side of the first divided region e with respect to the horizontal width m of the first divided region e
L (HPOS / m) and the ratio {(n-VPOS) / n} of the distance ΔYD from the target position Pxy to the lower side of the first divided region e with respect to the vertical width n of the first divided region e.
And the product of That is, the second parallax interpolation coefficient KUR increases as the distance between the upper right vertex PE2 of the first divided region e including the target position Pxy and the target position Pxy decreases.

The third parallax interpolation coefficient KDL is calculated based on the target position P
xy, the distance ΔX from the target position Pxy to the right side of the first divided area e with respect to the horizontal width m of the first divided area e including xy
R and the ratio {(m-HPOS) / m} to the first divided region e
(VPOS / n) of the distance ΔYU from the target position Pxy to the upper side of the first divided area e with respect to the vertical width n of
And the product of That is, the third parallax interpolation coefficient KDL increases as the distance between the lower left vertex PE5 of the first divided region e including the target position Pxy and the target position Pxy decreases.

The fourth parallax interpolation coefficient KDR is calculated based on the target position P
xy, the distance ΔX from the target position Pxy to the left side of the first divided region e with respect to the horizontal width m of the first divided region e
L and the ratio (VPOS / n) of the vertical width n of the first divided area e to the distance ΔYU from the target position Pxy to the upper side of the first divided area e. Desired. That is, the fourth parallax interpolation coefficient KD
R increases as the distance between the lower right vertex PE6 of the first divided area e including the target position Pxy and the target position Pxy decreases.

(3) The first to fourth extracted in the above (1)
To the parallax information UL, UR, DL, DR of the first to fourth parallax interpolation coefficients KUL, calculated in (2) above, respectively.
KUR, KDL, and KDR are each multiplied. Then, the obtained four multiplication values are added to generate disparity information for the target position Pxy.

The parallax information storage means 60 stores the areas E1 to E1.
2 are provided with first to twelfth parallax registers 61 to 72 provided correspondingly to the two. The first to twelfth disparity registers 61 to 72 store disparity information for each of the regions E1 to E12 generated by the CPU 3.

At the subsequent stage of the parallax information storage means 60, a parallax selection circuit 80 is provided. In the parallax selection circuit 80,
Parallax information is sent from each of the parallax registers 61 to 72. Further, the horizontal address signal HAD and the vertical address signal VAD are sent from the timing signal generation circuit 51 to the parallax selection circuit 80.

According to the rule shown in FIG. 24 (a), the parallax selecting circuit 80 sets the area corresponding to the horizontal address signal HAD and the vertical address signal VAD (in the example of FIG. 23, the first area including the target position). Of the parallax calculation area centered on the upper left vertex of the
Select and output as L. Further, the parallax selection circuit 80
Is a region corresponding to the horizontal address signal HAD and the vertical address signal VAD according to the rule shown in FIG. 24B (in the example of FIG. 23, the center is set at the upper right vertex of the first region including the target position). The disparity information for the disparity calculation area) is selected and output as the second disparity information UR.

Further, the parallax selecting circuit 80 is provided in
According to the rule shown in (c), an area corresponding to the horizontal address signal HAD and the vertical address signal VAD (in the example of FIG. 23, a parallax calculation area centered on the lower left vertex of the first area including the target position). Is selected and output as third parallax information DL. Further, the parallax selection circuit 80 determines the area corresponding to the horizontal address signal HAD and the vertical address signal VAD (in the example of FIG. 23, the first area including the target position in accordance with the rule shown in FIG. 24D). Parallax calculation area centered on the lower right vertex)
Is selected and output as fourth parallax information DR. In FIG. 24, for example, symbols “” ”represented by a and b, such as 0 to m, are used as symbols meaning a or more and less than b.

The first selected by the parallax selection circuit 80
The disparity information UL, the second disparity information UR, the third disparity information DL, and the fourth disparity information DR are input to first, second, third, and fourth multipliers 81, 82, 83, 84, respectively.

First, second, third and fourth multipliers 8
1, 82, 83, and 84 also receive the first parallax interpolation coefficient KUL, the second parallax interpolation coefficient KUR, the third parallax interpolation coefficient KDL, and the fourth parallax interpolation coefficient KDR from the parallax interpolation coefficient generation circuit 52, respectively. I have.

The first multiplier 81 multiplies the first disparity information UL by a first disparity interpolation coefficient KUL. The second multiplier 82
The second parallax information UR is multiplied by a second parallax interpolation coefficient KUR. The third multiplier 83 multiplies the third disparity information DL by a third disparity interpolation coefficient KDL. The fourth multiplier 84 multiplies the fourth disparity information DR by a fourth disparity interpolation coefficient KDR.

The outputs of the multipliers 81, 82, 83 and 84 are added by an adder 85. Thereby, the disparity information PR for the target position is obtained.

Each of the arbitrary pixel delay FIFOs 11 and 21 is 1
To perform horizontal phase control in units smaller than pixels,
Each of the two line memories 11a, 11b, 21a,
21b. Each arbitrary pixel delay FIFO11, 2
1, two line memories 11a, 11b, 21a, 2
1b, a Y signal is input and a clock signal CLK is input.

The horizontal address signal HAD output from the timing signal generation circuit 51 is also input to the standard address generation circuit 90. Standard address generation circuit 90
Is a standard write address WAD and a standard read address R for the two line memories 11a, 11b, 21a, 21b in each of the arbitrary pixel delay FIFOs 11, 21.
Generate and output AD. Further, the standard address generation circuit 90 also outputs a synchronization signal Csync added to the left video signal and the right video signal obtained by the 2D / 3D converter. The horizontal synchronization signal represented by the synchronization signal Csync is a horizontal synchronization signal Hsync of the input video signal.
The signal is delayed by a predetermined number of clocks from c.

The standard read address RAD is used to advance or delay the horizontal phase of the video signal input to each of the arbitrary pixel delay FIFOs 11 and 21 with respect to the reference horizontal phase defined by the standard read address. In addition, it is delayed by a predetermined number of clocks from the standard write address WAD. The standard write address WAD output from the standard address generation circuit 90 is stored in the two line memories 11 in each of the arbitrary pixel delay FIFOs 11 and 21.
a, 11b, 21a, and 21b are input as write control signals indicating write addresses.

The standard read address RAD output from the standard address generation circuit 90 is input to an adder 91 and a subtractor 92, respectively. Adder 91 and subtractor 9
2, the parallax information PR of the target position output from the adding circuit 85 is also input.

At the adder 91, the standard read address R
The disparity information PR is added to AD. As a result, the left video read address PRL is obtained.

The integer part PRL1 of the left video read address PRL is stored in the first line memory 11a in the left video arbitrary pixel delay FIFO 11 in the read address RADL1.
Enter as Therefore, the first line memory 11
The Y signal is read from the address corresponding to the address RADL1 of a. The read Y signal is input to the first left video multiplier 101.

The address value obtained by adding 1 to the integer part PRL1 of the read address PRL for the left image is input to the second line memory 11b in the arbitrary pixel delay FIFO 11 for the left image as the read address RADL2. Therefore, the Y signal is read from the address corresponding to the address RADL2 of the second line memory 11b. The read Y signal is input to the second left video multiplier 102.

The read address RADL1 for the first line memory 11a is different from the read address RADL2 for the second line memory 11b by one, so that the Y signal read from the first line memory 11a The Y signal read from the second line memory 11b is a signal whose horizontal position is shifted by one.

The decimal part PRL2 of the left video read address PRL is input to the second left video multiplier 102 as a second left video interpolation coefficient. A value obtained by subtracting the decimal part PRL2 of the read address PRL for the left image from 1 (1-PR
L2) is input to the first left video multiplier 101 as a first left video interpolation coefficient.

Therefore, the first left video multiplier 101
Then, the Y signal read from the first line memory 11a is multiplied by a first left video interpolation coefficient (1-PRL2). In the second left video multiplier 102, the Y signal read from the second line memory 11b is multiplied by a second left video interpolation coefficient PRL2. Then, each multiplier 101,
The Y signal obtained by 102 is added by the adder 103, and then output as a left video Y signal YL-OUT.

Thus, the standard read address RAD
With respect to the reference horizontal phase defined by the above, a left image Y signal whose horizontal phase amount is delayed by an amount corresponding to the parallax information for the target position is obtained.

In the subtractor 92, the standard read address R
The disparity information PR is subtracted from AD. As a result, the right video read address PRR is obtained.

The integer part PRR1 of the right video read address PRR is stored in the first line memory 21a in the right video arbitrary pixel delay FIFO 21 in the read address RADR1.
Enter as Therefore, the first line memory 21
The Y signal is read from the address corresponding to the address RADR1 of a. The read Y signal is input to the first right video multiplier 111.

The address value obtained by adding 1 to the integer part PRR1 of the right video read address PRR is input to the second line memory 21b in the right video arbitrary pixel delay FIFO 21 as the read address RADR2. Therefore, the Y signal is read from the address corresponding to the address RADR2 of the second line memory 21b. The read Y signal is input to the second right video multiplier 112.

Since the read address RADR1 for the first line memory 21a and the read address RADR2 for the second line memory 21b are different by one, the Y signal read from the first line memory 21a and The Y signal read from the second line memory 21b is a signal whose horizontal position is shifted by one.

The decimal part PRR2 of the read address PRR for the right image is input to the second multiplier 112 for the right image as a second right image interpolation coefficient. A value obtained by subtracting the decimal part PRR2 of the read address PRR for the right image from 1 (1-PR
R2) is input to the first right image multiplier 111 as a first right image interpolation coefficient.

Therefore, the first right video multiplier 111
Then, the Y signal read from the first line memory 21a is multiplied by a first right video interpolation coefficient (1-PRR2). In the second right image multiplier 112, the Y signal read from the second line memory 21b is multiplied by a second right image interpolation coefficient PRR2. Then, each multiplier 111,
The Y signal obtained by 112 is added by the adder 113 and then output as a right video Y signal YR-OUT.

Thus, the standard read address RAD
With respect to the reference horizontal phase defined by the above, a Y signal for right video is obtained in which the horizontal phase amount is advanced by an amount corresponding to the parallax information for the target position.

FIG. 25 shows that the parallax information for the target position is 0.
3 shows the signals of the respective units.

When the parallax information is 0, the read address PRL for the left image output from the adder 91 and the read address PRR for the right image output from the subtractor 92.
Is an address consisting of only an integer part without a decimal part equal to the standard read address RAD.

Therefore, an arbitrary pixel delay FIF for left video
Read address RADL1 for the first line memory 11a in O11 and right image arbitrary pixel delay FIFO
The read address RADR1 for the first line memory 21a in the memory 21 is equal to the standard read address RAD.

A left image arbitrary pixel delay FIFO 11
The read address RADL2 for the second line memory 11b in the first and the read address RADR2 for the second line memory 21b in the right image arbitrary pixel delay FIFO 21 have a value that is one greater than the standard read address RAD.

The first left image interpolation coefficient (1-PRL)
2) and the first right video interpolation coefficient (1-PRR2) are 1
And the second left video interpolation coefficient PRL2 and the second right video interpolation coefficient PRR2 become zero.

As a result, the left image arbitrary pixel delay FIFO
11, the standard address RA of the first line memory 11a
The Y signal read from the address corresponding to D is output from the adder 103 as the left video Y signal YL-OUT, and corresponds to the standard address RAD of the first line memory 21a in the right video arbitrary pixel delay FIFO 21. The Y signal read from the address to be output is output from the adder 113 as a right video Y signal YR-OUT. That is, two Y signals having the same amount of phase shift in the horizontal direction, that is, two Y signals having no parallax are output as a left video Y signal and a right video Y signal.

FIG. 26 shows a case where the standard write address WAD for a certain target position is 20, the standard read address RAD for the above target position is 10, and the disparity information for the above target position is 1.2. Is shown. FIG. 27 shows signals of the respective units at that time.

In this case, the left video read address PRL output from the adder 91 is 11.2,
Its integer part PRL1 becomes 11, and its decimal part PRL2
Is 0.2.

Therefore, the arbitrary pixel delay FIF for the left image
The read address RADL1 for the first line memory 11a in O11 is 11, and the read address RADL2 for the second line memory 11b is 12. Further, the first left video interpolation coefficient KL1 ｛= (1-PR
L2)｝ is 0.8, and the second left image interpolation coefficient KL2
(= PRL2) is 0.2.

Therefore, an arbitrary pixel delay FIF for left video
The Y signal (Y ₁₁ ) is read from the address 11 of the first line memory 11 a in O 11, and a signal (0) that is 0.8 times the read Y signal (Y ₁₁ ) is read from the first multiplier 101. .
8 * Y ₁₁ ) is output.

On the other hand, a left image arbitrary pixel delay FIFO 11
, The Y signal (Y ₁₂ ) is read from the address 12 of the second line memory 11 b, and the signal (0...) Which is 0.2 times the Y signal (Y ₁₂ ) read from the second multiplier 102. 2 * Y
₁₂ ) is output. Then, from the adder 103, 0.
Y signal YL for left image corresponding to 8 * Y ₁₁ + 0.2 * Y ₁₂
−OUT is output. That is, read address 1
The Y signal corresponding to 1.2 is a left video Y signal YL-OU.
Output as T.

The read address PRR for the right image output from the subtractor 92 is 8.8, and its integer part PRR
1 becomes 8, and the decimal part PRR2 becomes 0.8.

Therefore, the arbitrary pixel delay FIF for the right image
The read address RADR1 for the first line memory 21a in O21 becomes 8, and the second line memory 2a
The read address RADR2 for 1b is 9.
Also, the first right video interpolation coefficient KR1 ｛= (1-PRR
2) と な り is 0.2, and the second right video interpolation coefficient KR2
(= PRR2) is 0.8.

Therefore, the arbitrary pixel delay FIF for the right image
Y signal (Y ₈₎ is read from the first line memory 21a of the address 8 in O21, 0.2 times the signal of the Y signal read out from the first multiplier 111 (Y ₈₎ (0 .2
* Y ₈ ) is output.

On the other hand, a right image arbitrary pixel delay FIFO 21
, The Y signal (Y ₉ ) is read from the address 9 of the second line memory 21 b, and the signal (0...) 0.8 times the read Y signal (Y ₉ ) from the second multiplier 112. 8 *
Y ₉ ) is output. Then, from the adder 113,
A right video Y signal YR-OUT corresponding to 0.2 * Y ₈ + 0.8 * Y ₉ is output. In other words, the Y signal corresponding to the read address 8.8 is the right video Y signal YR-OU.
Output as T.

As a result, a left image and a right image having a disparity of 11.2−8.8 = 2.4, that is, a disparity twice as large as the disparity information 1.2 are obtained.

In the 2D / 3D video converter, the original 2D / 3D video
Since a field memory for generating a video signal delayed in time with respect to the two-dimensional video signal is not required, the cost can be reduced. Further, the 2D / 3D video converter can obtain a stereoscopic video even if the video represented by the original two-dimensional video signal is a still video.

[1-2-2] Description of Second 2D / 3D Video Converter

FIG. 28 shows the overall configuration of the second 2D / 3D video converter. A luminance signal Y, a color difference signal RY, and a color difference signal BY constituting a two-dimensional video signal
Are converted into digital Y signals, RY signals, and BY signals by an AD conversion circuit 1 (ADC).

The Y signal is sent to the motion vector detection circuit 2 and the first left video arbitrary pixel delay FIFO 1
1 and the first right video arbitrary pixel delay FIFO 21. The RY signal has a second left image arbitrary pixel delay F
FIFO12 and second right image arbitrary pixel delay FIFO
22. The BY signal is sent to a third left image arbitrary pixel delay FIFO 13 and a third right image arbitrary pixel delay FIFO 23.

The motion vector detection circuit 2 performs, for each field, the motions for each of the 12 motion vector detection areas (hereinafter referred to as parallax calculation areas) E1 to E12 set in one field screen as shown in FIG. Calculate the vector. Then, the motion vector detection circuit 2 outputs data indicating an area where the calculated motion vector has low reliability (hereinafter referred to as an NG area), and each of the areas E <b> 1 to E <b> 1 other than the NG area.
The motion vector in the X direction for each E12, the maximum value of the motion vectors in the X direction of each of the areas E1 to E12 other than the NG area (including the data of the area where the motion vector in the X direction is the maximum value), and the area other than the NG area Of the motion vectors in the X direction of the respective regions E1 to E12 (including the data of the region where the motion vector in the X direction is the minimum value) and the motion vectors in the X direction of the respective regions E1 to E12 other than the NG region Is transmitted to the CPU 3 for each field.

The CPU 3 determines each of the parallax calculation areas E1 to E based on the information sent from the motion vector detection circuit 2.
The amount of depth or the amount of protrusion for 12 is calculated, and parallax information is generated for each of the parallax calculation areas E1 to E12 based on the calculated amount of depth or the amount of protrusion. In this example, the depth amount is calculated for each of the parallax calculation regions E1 to E12 such that the depth amount increases in the region where the background exists and decreases in the region where the subject exists. Details of the method of calculating the depth amount will be described later.

The disparity information for each of the disparity calculation areas E1 to E12 calculated by the CPU 3 is sent to the disparity control circuit 4. The parallax control circuit 4 controls the parallax calculation areas E1 to E1.
Based on the two pieces of disparity information, disparity information for each pixel position in each field is generated. Then, based on the obtained parallax information for each pixel position, each of the FIFOs 11 to 1
3, video signals (Y signal, RY signal, B
−Y signal) so that the read address is shifted between the left image arbitrary pixel delay FIFOs 11 to 13 and the right image arbitrary pixel delay FIFOs 21 to 23.
The read addresses of O11 to 13 and 21 to 23 are controlled. Therefore, the left image arbitrary pixel delay FIFO 11-
13 is different from the horizontal phase of the right video signal read from the right video arbitrary pixel delay FIFOs 21 to 23.

Left image arbitrary pixel delay FIFOs 11 to 13
From the left video signal (YL signal, (RY) L
Signal, (BY) L signal) is a DA conversion circuit (DAC)
After being converted into an analog signal by 5, it is sent to a stereoscopic display device (not shown) via the stereoscopic effect adjusting device 502.
The right video signal (YR signal, (RY) R signal, (B-
Y) R signal) is converted into an analog signal by a DA conversion circuit (DAC) 6, and then sent to a stereoscopic display device (not shown) via a stereoscopic effect adjusting device 502.

Since the horizontal phase of the left video signal is different from the horizontal phase of the right video signal, a parallax occurs between the left video and the right video. As a result, the left image is observed only with the left eye,
When the right image is observed only with the right eye, a three-dimensional image in which the subject is located in front of the background is obtained.

FIG. 29 shows a method of generating parallax information performed by the CPU 3.

The subject / background discriminating means 31 is based on the motion vector in the X direction of each of the parallax calculation areas E1 to E12 other than the NG area, and the image of each parallax calculation area other than the NG area is the subject. Or background. For example, Japanese Patent Application Laid-Open No.
The method disclosed in Japanese Patent No. 9517 is used.

The depth information generating means 32 calculates the motion vector in the X direction for each of the disparity calculation areas E1 to E12 other than the NG area, and the X of the disparity calculation areas E1 to E12 other than the NG area.
The maximum value of the motion vectors in the direction (including the data of the area where the motion vector in the X direction is the maximum value) and the minimum value of the motion vectors in the X direction of each of the disparity calculation areas E1 to E12 other than the NG area ( The depth amount (depth information) is determined for each of the parallax calculation regions E1 to E12 based on the data indicating the region where the motion vector in the X direction has the minimum value and the data indicating the NG region.

That is, the discrimination result of each of the parallax calculation areas E1 to E12 other than the NG area by the subject / background discrimination means 31 and the maximum of the X-direction motion vectors of the parallax calculation areas E1 to E12 other than the NG area. Value (including the data of the area where the motion vector in the X direction is the maximum value) and the minimum value of the motion vectors in the X direction of each of the parallax calculation areas E1 to E12 other than the NG area (the motion vector in the X direction is the minimum). And the parallax calculation area where the motion vector in the X direction is the maximum value and the parallax calculation area where the motion vector in the X direction is the minimum value. The screen position PPF is determined, and the stereoscopic position of the other parallax calculation area is determined as the innermost position PPR.

For example, when the image in the parallax calculation area where the X-direction motion vector has the maximum value is the subject and the image in the parallax calculation area where the X-direction motion vector has the minimum value is the background, FIG. As shown in (3), the stereoscopic view position of the parallax calculation area where the motion vector in the X direction is the maximum value is determined as the tube surface position PPF, and the stereoscopic view position of the parallax calculation area where the motion vector in the X direction is the minimum value is the most. The depth position PPR is determined.

When the image in the parallax calculation area where the motion vector in the X direction has the maximum value is the background and the image in the parallax calculation area where the motion vector in the X direction is the minimum value is the subject, the motion in the X direction is The stereoscopic vision position of the parallax calculation area where the vector is the maximum value is determined as the innermost position PPR, and the stereoscopic vision position of the parallax calculation area where the motion vector in the X direction is the minimum value is determined as the tube surface position PPF.

Here, the image in the parallax calculation area where the X-direction motion vector has the maximum value is the subject, and the image in the parallax calculation area where the X-direction motion vector has the minimum value is the background, as shown in FIG. As described above, the stereoscopic position of the parallax calculation area where the motion vector in the X direction is the maximum value is the screen position PPF.
Assuming that the stereoscopic viewing position of the parallax calculation area where the motion vector in the X direction is the minimum value is determined to be the deepest position PPR, a method of determining the depth amounts of the parallax calculation areas E1 to E12 will be described.

Among the parallax calculation areas other than the parallax calculation area having the maximum value of the motion vector in the X direction and the parallax calculation area having the minimum value, the stereoscopic viewing position of each parallax calculation area other than the NG area is as follows.
A position corresponding to the motion vector in the X direction of the parallax calculation area is determined between the tube surface position PPF and the innermost position PPR. In this example, the stereoscopic position is determined to be closer to the screen position PPF in the region where the motion vector in the X direction is larger, and the stereoscopic position is set to the innermost position PPR in the region where the motion vector in the X direction is smaller. Is determined at a position close to.

The stereoscopic position of each NG area is determined by whether the NG area is in the upper part of the screen (areas E1 to E4), in the middle part (areas E5 to E8), or in the lower part of the screen (areas E9 to E1).
It is determined according to whether it is in 2).

The stereoscopic position of the NG area at the bottom of the screen is determined at the center position Pa between the tube surface position PPF and the innermost position PPR. The stereoscopic position of the NG area at the top of the screen is determined to be the same position Pc as the innermost position PPR. The stereoscopic position of the NG area at the middle of the screen is the center position P between the stereoscopic position Pa of the NG area at the lower part of the screen and the stereoscopic position Pc of the NG area at the upper part of the screen.
b.

The reason why the stereoscopic position of the NG area is determined as described above will be described. In the NG area, the image is presumed to be the background. Normally, the background is closer to the lower side of the screen, and is farther to the upper side of the screen. Therefore, the stereoscopic viewing position of each NG position is determined such that the NG area on the upper side of the screen is located at a deeper position from the tube surface position PPF. In addition, since the image in the NG area is assumed to be the background, the stereoscopic position of the NG area on the lower side of the screen is determined to be a position deeper than the stereoscopic position of the area where the subject exists. .

As described above, each of the parallax calculation areas E1 to E
By determining the twelve stereoscopic viewing positions, the depth amount (depth information) of each of the parallax calculation areas E1 to E12 from the tube surface position PPF is determined.

The depth information selection means 33 includes depth information for each of the parallax calculation areas E1 to E12 of the current field generated by the depth information generation means 32 and each of the previous fields previously selected by the depth information selection means 33. Depth information for the parallax calculation areas E1 to E12 is input. Further, data indicating the integrated value of the absolute value of the motion vector in the X direction of each of the parallax calculation areas E1 to E12 other than the NG area is sent to the depth information selection means 33.

The depth information selecting means 33 determines whether the integrated value of the absolute value of the motion vector in the X direction of each of the parallax calculation areas E1 to E12 other than the NG area is equal to or larger than a predetermined value, that is, the video of the current field with respect to the previous field. Is large, the depth information of the current field is selected and output. When the integrated value of the absolute value of the motion vector in the X direction of each of the parallax calculation areas E1 to E12 other than the NG area is smaller than a predetermined value, that is, when the motion of the video of the current field with respect to the previous field is small, the depth information selection is performed. Means 33
Selects and outputs the depth information of the previous field.

The depth information for each of the parallax calculation areas E1 to E12 (hereinafter, referred to as first depth information for each of the areas E1 to E12) output from the depth information selection means 33 is abrupt between fields where the depth information is adjacent. Is sent to the smoothing processing means 40 for preventing the change to The smoothing processing means 40 includes a first multiplication means 3
4. It comprises an adding means 35 and a second multiplying means 36.

The first depth information for each of the parallax calculation areas E1 to E12 is multiplied by a coefficient α by the first multiplying means. Is normally set to, for example, 1/8. However, when the scene of the current field changes (scene changes) from the scene of the previous field, the coefficient α is set to 1. As a method of detecting such a scene change, for example, a method disclosed in Japanese Patent Application Laid-Open No. 8-149514 is used.

The output of the first multiplying means 34 (hereinafter, each area E
The second depth information for each of 1 to E12) is sent to the adding means 35. The adding means 35 includes a second multiplying means 36
(Hereinafter, referred to as fourth depth information for each of the regions E1 to E12), and the parallax calculation regions E1 to E1
The sum of the first depth information for each of the two and the fourth depth information of the corresponding parallax calculation area is calculated.

In the second multiplying means 36, the previous adding means 3
5 (hereinafter referred to as third depth information for each of the regions E1 to E12) is multiplied by a coefficient β. Is usually set to, for example, 7/8. However, when the scene of the current field changes (scene changes) from the scene of the previous field, the coefficient β is set to 0.

Therefore, if the scene of the current field has not changed from the scene of the previous field,
The multiplying unit 34 multiplies the first depth information for each of the parallax calculation areas E1 to E12 output from the depth information selecting unit 33 by ８. Thereby, the second depth information for each of the parallax calculation areas E1 to E12 is obtained.

The second depth information for each of the parallax calculation areas E1 to E12 is sent to the adding means 35. The adding means 35 further calculates each parallax obtained by multiplying the third depth information for each of the parallax calculation areas E1 to E12 previously output from the adding means 35 by 7/8 by the second multiplying means 36. Fourth depth information for each of the calculation areas E1 to E12 is also input.

In the adding means 35, each parallax calculation area E1
The sum of the second depth information of E12 and the fourth depth information of the corresponding parallax calculation area is calculated. Thereby, the third depth information for each of the parallax calculation areas E1 to E12 is obtained. The third depth information for each of the parallax calculation areas E1 to E12 is sent to the parallax control circuit 4 (see FIG. 28) as parallax information.

When the scene of the current field has changed from the scene of the previous field, the first multiplying means 34 adds the depth information for each of the parallax calculation areas E1 to E12 output from the depth information selecting means 33. Each is multiplied by one. Therefore, the parallax calculation areas E output from the depth information selecting unit 33 are output from the first multiplying unit 34.
Depth information for each of 1 to E12 is output as it is.

Since the coefficient of the second multiplying means 36 is 0,
The output of the second multiplying means 36 is 0. Therefore, the depth information for each of the parallax calculation areas E1 to E12 output from the depth information selection means 33 is output from the addition means 35 as it is. In other words, when the scene of the current field has changed from the scene of the previous field, the parallax calculation areas E1 to E1 output from the depth information selection unit 33 are different.
Depth information for each E12 is sent to the parallax control circuit 4 (see FIG. 28) as parallax information.

The configuration and operation of the parallax control circuit 4 in the second 2D / 3D video converter are the same as those of the first 2D / 3D video converter shown in FIG.
Since the configuration is the same as that of the parallax control circuit in the D / 3D video converter, the description of the configuration and operation will be omitted.

In the 2D / 3D video converter, the original 2D / 3D video
Since a field memory for generating a video signal delayed in time with respect to the two-dimensional video signal is not required, the cost can be reduced.

[1-3] Description of three-dimensional effect adjustment circuit

FIG. 31 shows the configuration of the stereoscopic effect adjustment circuit 502.

[0209] The stereoscopic effect adjusting circuit 502 includes a coefficient generating circuit 6
01, a left image three-dimensional effect adjustment circuit 602 for performing a three-dimensional effect adjustment process on the left image signal, and a right image three-dimensional effect adjustment circuit 603 for performing the three-dimensional effect adjustment process on the right image signal.

The configuration of the left image stereoscopic effect adjustment circuit 602,
Since the configuration of the three-dimensional effect adjustment circuit 603 for the right image is the same, only the three-dimensional effect adjustment circuit 602 for the left image will be described.

[0211] The coefficient generation circuit 601 outputs the parallax information PR for each pixel sent from the 2D / 3D video converter 501.
(Information on the perspective of the image) based on the first coefficient K
L, a second coefficient KH, and a third coefficient KC are generated. First
The coefficient KL is generated within a range of 0 or more and 1 or less (0 ≦ KL ≦ 1), and is a coefficient for adjusting a ratio of a low frequency component of an image. That is, the first coefficient KL is a coefficient for blurring the outline of the image, that is, a coefficient for reducing the sharpness of the outline of the image. The larger the value of the first coefficient KL, the more the image whose outline is blurred. Will be obtained.

The coefficient generation circuit 601 reduces the first coefficient KL for the pixel in which the image in front is shown,
The first coefficient KL is increased for a pixel on which an image behind is displayed. As described above, in this embodiment, the disparity information PR for a pixel in which an image in front is shown is small, and the disparity information PR for a pixel in which an image in back is shown is large. For this reason, as shown in FIG. 32, the coefficient generation circuit 601 sets the value of the first coefficient KL to 0 when the disparity information PR is equal to or less than a predetermined value, and sets the disparity information P
In a range where R is larger than a predetermined value, the value of the first coefficient KL is increased as the disparity information PR increases.

The second coefficient KH is generated within a range of 0 or more and 1 or less (0 ≦ KH ≦ 1), and is a coefficient for adjusting a ratio of a high frequency component of an image. That is, the second coefficient KH
Is a coefficient for sharpening the outline of the image, that is, a coefficient for increasing the sharpness of the outline of the image. As the value of the second coefficient KH increases, an image with a sharper outline can be obtained.

The coefficient generation circuit 601 increases the second coefficient KH for the pixel in which the image in front is shown,
The second coefficient KH is reduced for a pixel on which an image behind is displayed. As described above, in this embodiment, the disparity information PR for a pixel in which an image in front is shown is small, and the disparity information PR for a pixel in which an image in back is shown is large. For this reason, as shown in FIG. 33, in a range where the disparity information PR is equal to or less than a predetermined value, the coefficient generation circuit 601 determines that the second coefficient K
The value of H is reduced, and the value of the second coefficient KH is set to 0 in a range where the parallax information PR is larger than a predetermined value.

The third coefficient KC is a coefficient for adjusting the saturation of an image, and the saturation of the image is enhanced as the third coefficient KC increases. The coefficient generation circuit 601 increases the third coefficient KC for a pixel in which an image in front is shown, and decreases the third coefficient KC in a pixel in which an image behind is shown. As described above, in this embodiment, the disparity information PR for a pixel in which an image in front is shown is small, and the disparity information PR for a pixel in which an image in back is shown is large. Therefore, as illustrated in FIG. 34, the coefficient generation circuit 601 decreases the value of the third coefficient KC as the disparity information PR increases.

The stereoscopic effect adjustment circuit 602 for the left image has 2D
A luminance signal YL, a chrominance signal (RY) L, and a chrominance signal (BY) L, which form the left image and are transmitted from the / 3D image converter 501, are input.

The left image stereoscopic effect adjusting circuit 602 includes a circuit 610 for adjusting the sharpness of the outline of the image and a circuit 620 for adjusting the saturation of the image.

Circuit 610 for Adjusting Sharpness of Image Outline
Will be described. The circuit 610 for adjusting the sharpness of the outline of the image is a circuit 61 for adjusting the ratio of the low frequency component of the image.
1. It comprises a circuit 612 for adjusting the ratio of the high frequency component of the video and an addition circuit 613 for adding their outputs.

Circuit 6 for adjusting the ratio of the low frequency component of the video
Reference numeral 11 denotes a low-pass filter (LPF) 701 for extracting a low-frequency component of the luminance signal YL, and first multipliers 702 and 1- 1 for multiplying the low-frequency component of the luminance signal YL extracted by the low-pass filter 701 by a first coefficient KL. An arithmetic unit 703 that performs an operation of KL, a second multiplier 704 that multiplies the luminance signal YL by (1-KL) that is an output of the arithmetic unit 703, and an output of the first multiplier 702 and an output of the second multiplier 704. A first adder 705 for adding is provided.

Circuit 6 for adjusting the ratio of high frequency components of video
A high-pass filter (HPF) 711 and a high-pass filter 71 for extracting a high-frequency component of the luminance signal YL
1 to the high frequency component of the luminance signal YL extracted by
A third multiplier 712 for multiplying the coefficient KH is provided.

Circuit 6 for adjusting the ratio of low frequency components of video
The output of the eleventh (the output of the first adder 705) and the output of the circuit 612 for adjusting the ratio of the high frequency component of the video (the output of the third multiplier 712) are added by the addition circuit 613. The output YL-OUT of the addition circuit 613 is sent to a three-dimensional display device (not shown).

As described above, the first coefficient KL becomes smaller for the pixel in which the image in front is reflected, and the second coefficient KL becomes smaller.
The coefficient KH increases. Therefore, the ratio of the low-frequency component of the luminance signal YL is low, and the ratio of the high-frequency component of the luminance signal YL is high, for a pixel on which an image in front is shown. For this reason, the image for the pixel in which the image in front is shown is an image with a sharp outline.

On the other hand, the first coefficient KL becomes larger and the second coefficient KH becomes smaller for a pixel on which a video image located behind is displayed. Therefore, the ratio of the low-frequency component of the luminance signal YL is high, and the ratio of the high-frequency component of the luminance signal YL is low, for a pixel on which an image behind is displayed. For this reason, the image for the pixel in which the image on the rear is reflected is an image with a blurred outline. In this way, the image for the pixel where the image in front is shown is a sharp image, and the image for the pixel where the image in the back is image is a blurred image, so that the stereoscopic effect is emphasized. .

The circuit 620 for adjusting the saturation of an image will be described. The circuit 620 for adjusting the saturation of the image includes a fifth multiplier 7 for multiplying the color difference signal (RY) L by a third coefficient KC.
21 and a sixth multiplier 722 for multiplying the color difference signal (BY) L by a third coefficient KC. Fifth multiplier 721
(RY) L-OUT of the sixth multiplier 722 and the output (BY) L-OUT of the sixth multiplier 722 are sent to a three-dimensional display device (not shown).

As described above, the third coefficient KC becomes larger for a pixel in which an image located ahead is reflected. Therefore, for the pixel where the image in front is reflected,
The values of the color difference signals (RY) L and (BY) L increase, and the saturation increases. On the other hand, the third coefficient KC is smaller for a pixel in which a video image located behind is displayed. Therefore, for the pixel where the image behind is reflected,
The values of the color difference signals (RY) L and (BY) L decrease, and the saturation decreases. As described above, the saturation of the image with respect to the pixel where the image in front is reflected increases, and the saturation of the image with respect to the pixel in which the image behind is reflected lowers, so that the stereoscopic effect is emphasized.

[2] Description of Second Embodiment of the Invention

The following describes an embodiment in which the present invention is applied to a system for adjusting the three-dimensional effect of a three-dimensional video signal composed of a left video signal and a right video signal captured using two cameras. I do.

[2-1] Description of overall configuration of stereoscopic effect adjustment system.

FIG. 35 shows the configuration of the three-dimensional effect adjustment system.

This stereoscopic effect adjusting system detects a parallax information PR for each pixel from a three-dimensional video signal for each field, and a parallax information for each pixel obtained by the parallax detection circuit 801. A stereoscopic effect adjusting circuit 802 for adjusting the stereoscopic effect on the three-dimensional video signal based on the PR.

The parallax detection circuit 801 includes a selection circuit 901,
Motion vector detection circuit 902, vector correction circuit 903
And a parallax information generation circuit 904.

The selection circuit 901 receives the luminance signal YL-IN of the left video constituting the three-dimensional video and the luminance signal YR-IN of the right video constituting the three-dimensional video. The selection circuit receives the field identification signal FLD as a control signal.

The selection circuit 901 outputs the field identification signal F
Based on the LD, the luminance signal YL-IN for the left image and the luminance signal YR-IN for the right image are switched and output in units of one field. In this example, the field identification signal FLD goes high when the field of the input video signal is an odd field, and goes low when the field of the input video signal is an even field. Then, the selection circuit 901 outputs the field identification signal F
When LD is at H level (odd field), the luminance signal YL-IN in the left image is selected and output, and the field identification signal FLD is at L level (even field).
, The luminance signal YR-IN in the right image is selected and output.

[0234] The motion vector detection circuit 902 converts the video signal output from the selection circuit 901 into twelve motion vector detection areas (hereinafter, referred to as "fields") set in one field screen as shown in FIG. An X-direction motion vector is calculated for each of the parallax calculation areas E1 to E12.

The X-direction motion vectors for each of the parallax calculation areas E1 to E12 obtained by the motion vector detection circuit 902 are sent to the vector correction circuit 903. The horizontal motion of the video between the left video and the right video for each of the parallax calculation areas E1 to E12 obtained by the motion vector detection circuit 902 is shown. Since the left image and the right image have parallax, even for the same object, the horizontal position differs between the two images according to the distance from the camera. Therefore, X for each parallax calculation area E1 to E12
The directional motion vector corresponds to a parallax between both images in each of the parallax calculation areas E1 to E12.

However, even when the object is moving in the same direction, the X direction vector obtained when the left image changes to the right image and the X direction vector obtained when the right image changes to the left image In, the sign of the motion vector in the X direction is in the opposite direction. Therefore, a vector correction circuit 903 is provided to match the signs of the obtained X-direction vectors when the objects are moving in the same direction.

When the field identification signal FLD is at the H level (odd field), the vector correction circuit 903 converts the X-direction motion vector for each of the parallax calculation areas E1 to E12 sent from the motion vector detection circuit 902 into a parallax. It is sent to the information generation circuit 904 as it is.

If the field identification signal FLD is at L level (even field), the vector correction circuit 90
3 inverts the sign of the X-direction motion vector for each of the disparity calculation areas E1 to E12 sent from the motion vector detection circuit 902, and sends it to the disparity information generation circuit 904.

In the parallax information generation circuit 904, each of the parallax calculation areas E1 to E transmitted from the vector correction circuit 903.
The disparity information PR for each pixel is generated based on the X-direction motion vectors for each pixel.

That is, the X-direction motion vector for each of the parallax calculation areas E1 to E12 sent from the vector correction circuit 903 is used as the parallax information for each of the parallax calculation areas E1 to E12, and is the same as that described with reference to FIG. Then, the disparity information PR for each pixel is generated from the disparity information for each of the disparity calculation areas E1 to E12.

The stereoscopic effect adjusting circuit 802 performs a process for correcting the stereoscopic effect on the three-dimensional video signal based on the parallax information PR for each pixel obtained by the parallax information detecting circuit 801. This three-dimensional effect correction circuit 802 includes: FIG.
Since it is the same as the three-dimensional effect adjustment circuit 502, the description of its configuration and operation is omitted.

[0242]

According to the present invention, it is possible to adjust the stereoscopic effect of a stereoscopic video obtained by a three-dimensional video signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a 2D / 3D video conversion system.

FIG. 2 is a block diagram illustrating a configuration of a 2D / 3D video conversion device.

FIG. 3 is a schematic diagram illustrating a parallax calculation area.

FIG. 4 is a block diagram illustrating a configuration of a luminance integration circuit.

FIG. 5 is a block diagram illustrating a configuration of a high-frequency component integration circuit.

FIG. 6 is a circuit diagram showing a specific example of a high-pass filter 232 of FIG.

FIG. 7 is a graph showing input / output characteristics of the slice processing circuit 234 of FIG.

FIG. 8 is a block diagram showing another example of the high frequency component integrating circuit.

9 is a circuit diagram showing a specific example of the peak detection circuit 239 in FIG.

FIG. 10 is a time chart showing signals of various parts of a peak detection circuit 239.

FIG. 11 is a block diagram illustrating a configuration of a luminance contrast calculation circuit.

FIG. 12 is a circuit diagram illustrating a configuration of a luminance contrast detection circuit in FIG. 11;

FIG. 13 is a circuit diagram illustrating a configuration of a saturation integration circuit.

FIG. 14 is an explanatory diagram for describing a method of generating disparity information by a CPU.

FIG. 15 is a graph showing an input / output relationship of the normalizing means 410 of FIG.

FIG. 16 is a schematic diagram illustrating a parallax calculation area actually set.

FIG. 17 is a schematic diagram illustrating an example of depth information of each parallax calculation area before depth correction.

FIG. 18 is a schematic diagram illustrating depth information of each parallax calculation area after depth correction.

FIG. 19 is a graph showing the relationship between the height position of the screen before depth correction and depth information and the relationship between the height position of the screen after depth correction and depth information.

FIG. 20 is a graph showing a relationship between depth information and disparity information.

FIG. 21 is a block diagram mainly showing a configuration of a parallax control circuit and an arbitrary pixel delay FIFO.

FIG. 22 is a schematic diagram showing a relative horizontal position, a relative vertical position, and the like.

FIG. 23 is an explanatory diagram for describing a method of generating disparity information for a target pixel.

FIG. 24 is a diagram illustrating a selection rule by a parallax selection circuit.

FIG. 25 is a time chart showing signals of respective units when disparity information is 0.

FIG. 26 is a block diagram in which each address value when the disparity information is 1.2 is added to the disparity control circuit.

FIG. 27 is a time chart illustrating signals of respective units when the disparity information is 1.2.

FIG. 28 is a block diagram illustrating a configuration of another 2D / 3D video conversion device.

FIG. 29 is a functional block diagram illustrating a depth information generation process performed by a CPU;

FIG. 30 is an explanatory diagram for describing a method of generating depth information by a CPU.

FIG. 31 is a block diagram illustrating a configuration of a three-dimensional effect adjustment circuit.

FIG. 32 is a graph illustrating a relationship between disparity information PR for each pixel and a first coefficient KL.

FIG. 33 is a graph illustrating a relationship between disparity information PR for each pixel and a second coefficient KH.

FIG. 34 is a graph illustrating a relationship between disparity information PR for each pixel and a third coefficient KC.

FIG. 35 is a block diagram illustrating a configuration of a three-dimensional effect adjustment system.

[Explanation of symbols]

 Reference numeral 501 2D / 3D video conversion circuit 502 Stereoscopic effect adjustment circuit 601 Coefficient generation circuit 602 Left image stereoscopic effect adjustment circuit 603 Right image stereoscopic effect adjustment circuit 801 Parallax detection circuit 802 Stereoscopic effect adjustment circuit

Claims (13)

[Claims] 1. A 3D image based on information on the perspective of an image for each predetermined unit area within one field screen of a 3D image.
A stereoscopic effect adjusting method for adjusting the stereoscopic effect of a three-dimensional image by controlling the sharpness of the outline of the image for each predetermined unit area of the three-dimensional image. 2. A three-dimensional image based on information on the perspective of an image for each predetermined unit area within a one-field screen of a three-dimensional image.
A stereoscopic effect adjusting method for adjusting the stereoscopic effect of a three-dimensional image by controlling the saturation of the image for each predetermined unit area of the three-dimensional image. 3. A three-dimensional image based on information on the perspective of an image for each predetermined unit area within a one-field screen of a three-dimensional image.
By controlling the sharpness of the outline of the image and the saturation of the image for each predetermined unit area of the three-dimensional image, 3
A stereoscopic effect adjustment method that adjusts the stereoscopic effect of 3D images. 4. For an area where a close image is shown,
2. The method according to claim 1, wherein the sharpness of the outline of the image is controlled so that the sharpness of the outline of the image is high and the sharpness of the outline of the image is low in a region where a distant image is reflected. A stereoscopic effect adjustment method that adjusts the stereoscopic effect of 3D images. 5. For an area where a close image is shown,
3. The stereoscopic effect of a three-dimensional image according to claim 2, wherein the saturation of the image is controlled so that the saturation of the image is high and the saturation of the image is low in an area where a distant image is reflected. Adjusting stereoscopic effect. 6. For an area where a close image is shown,
For areas where a distant image is projected so that the sharpness of the outline of the image is high, the sharpness of the outline of the image is controlled so that the sharpness of the outline of the image is low and an area where a close image is shown 4. The method according to claim 3, wherein the saturation of the image is controlled so that the saturation of the image is increased with respect to the image, and the saturation of the image is decreased with respect to a region where a distant image is reflected.
A stereoscopic effect adjustment method that adjusts the stereoscopic effect of 3D images. 7. A three-dimensional image based on information on the perspective of an image for each predetermined unit area within a one-field screen of a three-dimensional image.
A three-dimensional effect adjusting device comprising an outline control means for controlling the sharpness of an outline of an image for each predetermined unit area of a two-dimensional image. 8. A three-dimensional image based on information on the perspective of the image for each predetermined unit area within a one-field screen of a three-dimensional image.
A three-dimensional effect adjusting device comprising a saturation control unit for controlling the saturation of an image for each predetermined unit area of a two-dimensional image. 9. A three-dimensional image based on information on the perspective of an image for each predetermined unit area within a one-field screen of a three-dimensional image.
Contour control means for controlling the sharpness of the outline of the image for each predetermined unit area of the three-dimensional image; A three-dimensional effect adjustment device comprising: a saturation control unit configured to control a saturation of an image for each predetermined unit area. 10. The contour control means increases the sharpness of the contour of the image in a region where a near image is projected, and increases the sharpness of the contour of the image in a region where a far image is projected. 8. The three-dimensional effect adjusting device according to claim 7, wherein the sharpness of the outline of the image is controlled so as to be lower. 11. The saturation control means increases the saturation of the image in an area where a near image is displayed, and lowers the saturation of the image in an area where a distant image is reflected. 9. The three-dimensional effect adjusting device according to claim 8, wherein the three-dimensional effect adjusting device controls the saturation of an image. 12. The contour control means increases the sharpness of the contour of an image in a region where a distant image is projected, so that the sharpness of the contour of the image is high in a region where a near image is projected. The saturation control means controls the sharpness of the outline of the video so that the image becomes lower, and the saturation control means displays the distant video so that the saturation of the video becomes higher in the area where the closer video is displayed. 10. The three-dimensional effect adjustment device according to claim 9, wherein the saturation of the image is controlled so that the saturation of the image is reduced in the region where the image is displayed. 13. A contour control means for a region in which a near image is shown, reduces the ratio of a low-frequency component of the image and increases the ratio of a high-frequency component of the image, and sets a region in which a distant image is shown. 13. The three-dimensional effect adjusting device according to claim 7, wherein the ratio of the low-frequency component of the video is increased and the ratio of the high-frequency component of the video is reduced.