JPH1051685A - Image interpolation processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture interpolation processor improving the degree of freedom in the constitution, etc., of a memory and speedily executing am image interpolation processing by successive reading. SOLUTION: In this image interpolation processor, A DRAM access control circuit 2 does not re-read overlapped image data but reads newly required image data in already read image data and a main memory address generation circuit 2 changes the starting address of the reading of the main memory 6 to cumulatively add an increment part to this to generate the reading address of image data to read newly. A image processing arithmetic block 4 executes arithmetic processing to image data. A 16-pixel buffer 5 temporarily stores image data of maximum 16 pixels to execute cache operation to the main memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image synthesizing apparatus and a recording medium for use in a still image control apparatus for editing still image information formed by reading an image from a negative film or a photograph.

[0002]

2. Description of the Related Art Conventionally, there has been an image reading apparatus which reads an image as image data using a scanner and records the read image data on a rewritable recording medium.
Further, there has been an image interpolation processing device that performs an interpolation process on image data by further performing an arithmetic process on image data read by such an image reading device.

This image interpolation processing apparatus includes a first image interpolation processing apparatus which reads out image data necessary for interpolation processing by parallel processing and performs an operation, and a buffer which reads out image data required for interpolation processing by serial processing. There is a second image interpolation processing device that performs an operation after storing the image in the second image interpolation processing device.
The first image interpolation processing device simultaneously reads out four or sixteen points of image data around the image data to be subjected to the interpolation processing and stores them separately in four or sixteen memories to achieve high-speed processing by parallel processing. Things. The second image interpolation processing device is configured to control the image data around the image data to be subjected to the interpolation processing.
The calculation is performed while sequentially reading out the image data of points or 16 points and sequentially storing them in the buffer.

[0004]

However, in the first conventional image interpolation processing apparatus, when performing the image interpolation processing, a large number of peripheral data are not separately stored in parallel in the memory. Therefore, the number of memories increases, and the configuration is fixed for simultaneous reading. Therefore, there is a disadvantage that the memory capacity cannot be increased and the system cannot contribute to the development of the system. Also,
In the second conventional image interpolation processing apparatus, when performing the image interpolation processing, it is conceivable that the interpolation processing is performed using software for serial processing. There was an inconvenience of becoming longer.

The present invention has been made in view of the above points, and provides an image interpolation processing apparatus which has a high degree of freedom in a memory configuration and the like and can perform image interpolation processing at high speed by a sequential reading method. Aim.

[0006]

According to the present invention, there is provided an image interpolation processing apparatus comprising: a virtual logical address generating means for sequentially generating virtual logical addresses for accessing a designated area; A pre-virtual logical address storing means for storing a virtual logical address; a physical address generating means for generating a physical address required for an operation from the previous virtual logical address and the current virtual logical address; Means for temporarily storing data read by the reading means, and arithmetic means for performing a predetermined operation on the data stored in the buffer, and performing interpolation processing using a plurality of image data. In addition, the image data already used for the interpolation processing of the previous data is not Using data before accumulated in §, it is obtained so as to read only the newly required data.

According to the image interpolation processing device of the present invention, the following operation is performed. The reading means fetches 16 pixels indicated by the physical address around the logical address, and the calculating means performs an arithmetic process from these 16 pixels to obtain data of a logical address which is a virtual point. Here, the buffer operates to perform a cache operation.
The cache operation is a write / read operation of a small-capacity but high-speed processing buffer for a large-capacity but low-speed processing image data supply source. This is an operation that performs processing to increase the processing time as viewed from the image data supply source.

First, the case where there is no cache operation will be described. This operation is performed when the change of the logical address is 4 in the row direction. In this case, the previous pixel read range used for calculating the previous logical address does not overlap with the current pixel read range. That is, it is necessary to separately read the previous pixel read range indicating the range of 16 physical addresses and the current pixel read range indicating the range of 16 physical addresses by the reading unit. There is no. Therefore,
When the difference between the logical addresses is 4 or more, the cache operation is not performed. When the change of the logical address is 4 or more, the address during that period is not read, so that the operation is considerably reduced. For the previous pixel read range and the current pixel read range, a read address is generated in the physical address generation means by designating a start address and an increment of +4 in the row direction, respectively.

Next, the case of four pixels in the cache will be described. This operation is performed when the change of the logical address is 3 in the row direction.
This is the operation when. In this case, there are four pixels that overlap the previous pixel read range 19 used to calculate the previous logical address and the current pixel read range used to calculate the current logical address, and these four pixels are stored in the buffer. Pixels to be cached. That is, it is not necessary to read the entire current pixel reading range after reading the previous pixel reading range, and the four pixels to be cached are not re-read by the reading means, and the newly necessary remaining one is read.
It operates to read only two pixels. For the previous pixel read range and the current pixel read range, a read address is generated by designating a start address and an increment of +3 in the row direction by the physical address generation means.

Next, the case of eight pixels in the cache will be described. This operation is performed when the change of the logical address is 2 in the row direction.
This is the operation when. In this case, the previous pixel read range indicating the range of 16 physical addresses used to calculate the previous logical address, and the current pixel read range indicating the range of 16 physical addresses used to calculate the current logical address are: There are eight overlapping pixels, and these eight pixels are the pixels to be cached in the buffer. That is,
There is no need to read the entire current pixel read range after reading the previous pixel read range 19, and the read means does not reread the eight pixels to be cached, but reads only the newly required remaining eight pixels. I do. For the previous pixel read range and the current pixel read range, a read address is generated in the physical address generation means by designating a start address and plus 2 in the incremented row direction, respectively.

Next, the case of a cache having 12 pixels will be described. This operation is performed when the address change from the previous logical address to the current logical address is 1 in the row direction. In this case, the previous pixel read range indicating the range of 16 physical addresses used to calculate the previous logical address, and the current pixel read range indicating the range of 16 physical addresses used to calculate the current logical address are: There are 12 overlapping pixels, and these 12 pixels are cached in the buffer. That is, there is no need to read the entire current pixel read range after reading the previous pixel read range, and the 12 pixels to be cached need not be read again by the read means, and the new necessary 4 pixels are read.
Operates to read only pixels. For the previous pixel read range and the current pixel read range, the physical address generation means generates a read address by designating a start address and +1 in the row direction corresponding to the increment in the row direction.

Next, the case of a cache of 16 pixels will be described. This operation is performed when the address change from the previous logical address to the current logical address is the integer part 0. In this case, the previous pixel read range indicating the range of 16 physical addresses used to calculate the previous logical address, and the current pixel read range indicating the range of 16 physical addresses used to calculate the current logical address are: There are 16 overlapping pixels, and these 16 pixels are cached in the buffer. In other words, the pixels required for the calculation by the calculation means are all common, and there is no need to read the current pixel reading range after reading the previous pixel reading range, and the operation is performed using 16 pixels cached in the buffer.

Next, the case of a 12-pixel cache in the column direction will be described. This operation is performed when the address change from the previous logical address to the current logical address is 1 in the column direction. In this case, the previous pixel read range indicating the range of 16 physical addresses used to calculate the previous logical address, and the current pixel read range indicating the range of 16 physical addresses used to calculate the current logical address are: There are 12 overlapping pixels, and these 12 pixels are cached in the buffer. That is, after reading the previous pixel read range, it is not necessary to read the entire current pixel read range, and the cached 1
An operation is performed such that only the remaining four pixels which are newly required are read without rereading the two pixels by the reading means. Also,
For the previous pixel read range and the current pixel read range, a read address is generated by designating a start address and an increment of +1 in the column direction, respectively, in the physical address generation means.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the image interpolation processing device of the present embodiment, a still image control device to which the image interpolation processing device of the present embodiment is applied will be described with reference to FIGS. .

[Configuration of Still Image Control Apparatus] As shown in FIG.
(Minidisc) 25 and texture MD26 each M
It is configured to be housed in the D drive unit. In the image data MD25, high-resolution, medium-resolution, and low-resolution image data are recorded in an image data format. In the texture MD 26, character data, image data, and the like have been input in advance, and texture data as an initial image for image synthesis and key data are recorded in high resolution, medium resolution, and low resolution. Also,
The still image control device 24 includes a monitor 23 for displaying image data, a keyboard 27 for performing operations for specifying image data capture, recording, reproduction, printing, and the like.
A scanner 28 for reading image data and a printer 29 for printing image data are connected.

As shown in FIG. 17, a still image control unit 24 includes an image processing circuit 30 for generating high-resolution image data for printing and medium-resolution image data for the monitor 23 from image data captured by the scanner 28. And generating low-resolution image data for index display from medium-resolution image data from the image processing circuit 30 to obtain high-resolution image data.
MD control circuits 31 and 33 that generate medium-resolution and low-resolution image data and signal-process reproduced high-resolution, medium-resolution, and low-resolution image data for image processing, and image data MD25 and texture MD26. MD drive circuits 32 and 34 for recording or reproducing image data and texture data
, Keyboard 27, scanner 28, printer 29
And an interface circuit 35 for interfacing with the still image control device 24.

[Configuration of Scanner] First, the scanner 2
8 will be described. The scanner 28 includes a CCD image sensor that reads a still image recorded on a negative film, a positive film, a photograph, or the like, and an A / A that forms digital image data by converting an image signal supplied as an analog signal from the CCD image sensor. D converter and A
It comprises a correction unit for performing correction processing such as shading correction and color masking correction on image data from the / D converter, and an interface connected to a bus line.

[Configuration of Printer] Next, the printer 2
9 will be described. The printer 29 includes an interface connected to the bus line, a data conversion circuit that performs data conversion processing suitable for printing the supplied image data, and prints a still image corresponding to the image data from the data conversion circuit on printer paper. And a thermal head. The printing operation in the printer 29 is controlled according to print control data for controlling the number of prints, the color tone, and the like.

[Structure of MD Control Circuit] As shown in FIG. 18, each of the MD control circuits 31 and 33 has an MD control CPU 36 for controlling the entire circuit and a thinning-out process for medium-resolution image data to obtain a low-resolution image data. An index image generation circuit 37 for generating image data, a JPEG processing circuit 38 for performing still image compression processing and decompression, a CPU interface circuit 39 for buffering data to perform a recording or reproduction interface, and MD driving circuits 32 and 34. And a SCSI control circuit 40 for controlling data transfer by a SCSI command. The index image generation circuit 37 has a 1/64 thinning unit that forms low-resolution index image data by thinning out intermediate resolution image data to 1/64. Also, the JPEG processing circuit 38 is divided into blocks by a raster block conversion unit that divides each pixel data of high resolution, middle resolution or low resolution into blocks of 16 pixels suitable for compression processing, and a raster block conversion unit. A compression / decompression unit for performing a fixed length encoding process on the image data. The compression / decompression unit includes a discrete cosine / transform circuit (DCT circuit), a quantization circuit, and a fixed-length encoding circuit.

[Configuration of MD Drive Circuit] MD Drive Circuit 3
Reference numerals 2 and 34 denote interface units for interfacing with the MD control circuit, and MD drive circuits 32 and 3.
4, an EFM circuit that performs 8-14 modulation processing on image data of each resolution, and a disk recording that records or reproduces image data and texture data on image data MD25 and texture data MD26. It has a playback unit. Here, the image data MD25 is an image data recording medium, a texture MD.
Reference numeral 26 denotes an image-synthesized data recording medium, and the disk recording / reproducing unit constitutes data reading means.

[Configuration of Interface Circuit] As shown in FIG. 19, the interface circuit 35 includes a data buffer 43 for temporarily storing high-resolution image data for printing to be supplied to the printer 29, and a printer 29.
A SCSI control circuit 42 for controlling a data buffer 43 and an SCS
And a SCSI control CPU 41 for controlling the I control circuit 42. The monitor 23 and the keyboard 27 have only data lines.

[Configuration of Image Processing Circuit] As shown in FIG. 20, the image processing circuit 30 performs a color processing by a buffer 44 for temporarily storing image data read by the scanner 28 and a one-dimensional lookup table. One-dimensional color processing circuit 45 for performing line adjustment, and a line adjustment circuit 46 for performing line adjustment
And a data buffer 47 for temporarily storing image data.
A color pallet circuit 48 for coloring, a three-dimensional color processing circuit 49 for performing color processing using a three-dimensional lookup table, and a bus switch 5 for switching bus lines.
0 and 51.

The image processing circuit 30 includes a main memory 6 for storing image data, a title memory 6a for storing texture data, a key memory 6b for storing key data, a main memory 6, a title memory 6a and a key memory. Controlling the writing or reading of image data, texture data and key data to and from the memory 6b to perform image synthesis, and thinning out high-resolution image data read by the scanner 28 to generate medium-resolution image data And a main memory control circuit 1. Here, the main memory 4 constitutes image data storage means, the title memory 6a constitutes image composite data storage means, and the key memory 6b constitutes key data storage means.

The image processing circuit 30 includes a video memory 7 for storing medium-resolution image data for the monitor 8,
A video memory control circuit 52 controls writing or reading of image data to / from the video memory 7;
Memory control CPU for controlling main memory control circuit 1 and video memory control circuit 52
53.

The image processing circuit 30 includes a keyboard 2
7, a system control CPU 54 for generating a control signal in response to an input operation, and a display control circuit 5 for controlling the display on the monitor 23 according to the control signal from the system control CPU 54.
5, a D / A conversion circuit 56 for converting medium-resolution image data for the monitor 23 from the video memory 7 to analog image data, and a display control signal from the display control circuit 55 for converting the analog image data. An analog switch 57 for switching and a buffer 58 for temporarily storing analog image data to be output to the monitor 23 are provided.

Here, the main memory 6, which temporarily stores the fetched image data, the title memory 6a, and the key memory 6b are constituted by frame memories. The frame memory includes a main memory 6 and a title memory 6a.
, An R frame memory for reading and writing red (R) image data, a G frame memory for reading and writing green (G) image data, and a blue (B) image data for reading and writing. The key memory 6b is composed of a single-color frame memory.

The above-mentioned frame memories for each color logically have a DR of 2048 pixels × 1024 pixels × 8 bits in length × width × depth and a total of 16 Mbits.
AM (Dynamic RAM) is stacked in three layers in the horizontal direction, and the three DRAMs are configured to have a storage area of 2048 × 3072 × 8 bits, that is, 6 Mbytes or 48 Mbits. The frame memory is logically formed by laminating frame memories for each color having a storage area of 2048 × 3072 × 8 bits in the depth direction, for example, in the order of RGB. Therefore, the frame memory is 2048 ×
It has a storage area of 3072 × 24 bits.
The system control CPU 54 is provided with a random access memory (RAM) for temporarily storing management information of the image data read from the mini disk when the image data is rearranged in the reproduction order and recorded on the mini disk.

[Configuration of Main Memory Control Circuit]
As shown in FIG. 21, the main memory control circuit 1 includes a CPU register 59 for storing data and commands from the memory control CPU 53, a main memory 6, a title memory 6a, and a key memory 6b.
A memory access unit 60 for accessing the image data, a thinning / expansion processing unit 65 for thinning or expanding high-resolution image data to medium-resolution image data, and an image synthesis operation block 67 for performing image synthesis operation And DMA
A DMA processing unit 68 for performing a transfer operation. CPU
The register 59 includes a chip select signal (XCS REG, XC) for accessing the register or the DRAM.
CS DRAM), data write or data read signals (XWR, XRD), address strobe signals (XA
S), address signals (A20-0), data (D7-
0) is supplied.

[Structure of Memory Access Unit] The memory access unit 60 is a DRAM access for controlling writing or reading of image data, texture data and key data to and from the DRAMs forming the main memory 6, the title memory 6a and the key memory 6b. Control circuit 2, title memory 6a and key memory 6b
Memory address generating circuit 62 for generating an address for the main memory, a main memory address generating circuit 3 for generating an address for the main memory 6, and a DRAM
And a refresh control circuit 61 for controlling the refresh operation. From the DRAM access control circuit 2, a row address strobe signal (CAS),
Column address strobe signal (RAS), write enable signal (WE), output enable signal (OE)
Is output. Here, the DRAM access control circuit 2 constitutes a reading unit for sequentially reading data specified by a physical address. The title memory address generation circuit 62 outputs a title memory address signal (TA
10 to 0) are output. The main memory address generating circuit 3 outputs a 12-bit main memory address signal (MA11 to MA) consisting of an integer part corresponding to a physical address of the 20 logical addresses, and a decimal number of the 20 logical addresses. An 8-bit address signal (MA19 to MA12) is output to the thinning / decompression processing unit 65. The configuration of the main memory address generation circuit 3 will be described later in detail with reference to FIG. Here, the main memory address generating circuit 3 is required to execute a virtual logical address generating means for generating a virtual logical address, a previous virtual logical address storing means for storing a previous virtual logical address, and an operation from the previous virtual logical address and the current virtual logical address. Physical address generating means for generating various physical addresses. The title memory address generation circuit 62 supplies an address signal to the title memory 6a and the key memory 6b.

[Structure of Thinning / Expansion Processing Unit] The thinning / expansion processing unit 65 has an operation coefficient memory 66 having thinning / expansion coefficients and an image processing operation block 4 for performing thinning / expansion calculation. For the image processing operation block 4,
Main memory data of each color of R, G, B (MR7 to 0,
MG7-0, MB7-0) are input and output. The image processing operation block 4 stores the main memory data (MR7-0, M
G7-0, MB7-0), a 16-pixel buffer for temporarily storing 16-pixel data, and an operation for thinning or decompression processing on each data from the 16-pixel buffer based on coefficients from the operation coefficient memory. And an operation circuit to be applied. The arithmetic circuit includes a 1/4 thinning-out unit that forms high-resolution image data by thinning out the high-resolution image data from the scanner 28 to 1/4, and the intermediate resolution image data from the 1/4 thinning circuit 25. A 1/64 thinning unit that forms low-resolution image data by thinning to 1/64, high-resolution image data, intermediate-resolution image data from a 1/4 thinning unit, and a low-resolution image from a 1/64 thinning unit And a selector unit for selecting and outputting data. The reason why the storage capacity of the 16-pixel buffer is set to 16 pixels is that the processing in the JPEG processing circuit in the MD control circuit described above with reference to FIG. 18 is performed based on this 16-pixel block unit.

[Structure of Image Synthesis Operation Block] The image synthesis operation block 67 includes texture memory data (TR7-0, TG7-0, TB7-0) for each of R, G, and B colors.
And key signal data (K3-0) are input and output.
The image synthesis operation block 67 includes the image processing operation block 4
Main memory data (MR7-
0, MG7-0, MB7-0) and texture memory data (TR7-0, TG7-0, TB7-0)
And image synthesizing using key signal data (K3 to K0).

[Configuration of DMA Processing Unit] DMA Processing Unit 68
Is a main sequencer 69 for controlling a DMA transfer sequence, an INT DMA sequencer 70 for controlling a data write DMA transfer sequence, and an EXT DM sequencer for controlling a data read DMA transfer sequence.
A sequencer 71, double buffer control 72 for switching between two banks to control data writing or data reading, double buffer 73 having two banks, clock control circuit 74 for controlling DMA transfer clock, and interface control And an interface control circuit 75 for performing the operation. The clock control circuit 74 outputs an operation clock signal (CPU XTAL) of the memory control CPU 53,
An image clock signal (DCLK) and a quadruple image clock signal (DCLK4) are output. From the interface control circuit 75, an image transfer clock signal (PC
LK), a DMA acknowledge signal (REQOUT) and a DMA request signal (REQIN). Image output data of each color of R, G, B (DR7-0, DG7-0, DB7-0) from the double buffer 73
Is output.

[Outline of Recording Operation] Next, a normal recording operation of the still image control device having such a configuration will be described. First, desired image data is transferred to the MD drive circuit 32,
Image data MD (mini-disc) 25 mounted on
Alternatively, when recording on the texture MD 26, the user operates the keyboard 27 to specify a destination (scanner 28) of image data and sets an output destination of the captured image data to the MD drive circuits 32 and 34. . As a result, the system control CPU
54 controls the scanner 28 to the operating state.

[Description of Scanner Operation] First, the operation of the scanner 28 will be described. When a film, a photograph, and the like are placed on a document reading table, the scanner 28 scans the document by scanning a CCD line sensor. The CCD line sensor forms an image signal corresponding to the read image and supplies this to an A / D converter. The A / D converter forms image data by digitizing the image signal supplied from the CCD line sensor, and supplies this to the correction unit. For example, when an image is read from a 35 mm film, the correction unit corrects the image data into image data having a size of 1200 pixels × 1700 pixels in length and width and outputs the image data.

[Explanation of Operation of Image Processing Circuit] Next, the operation of the image processing circuit will be described. The image data formed by the scanner 28 is, for example, 1024 pixels × 15 pixels in length × width.
This is high-resolution image data of 36 pixels, and is supplied to the video memory 7 in the frame memory. When the high-resolution image data is supplied to the video memory 7, the video memory control circuit 52 temporarily stores the high-resolution image data, and controls the writing and reading of the video memory 7 so as to read out the stored high-resolution image data. . The high-resolution image data is transferred to the thinning / decompression processing unit 65 of the main memory control circuit 1 and the main memory 6 via the data line, the bus line, and the bus switch 51 in this order. The memory control circuit 1
The main memory 6 is written and controlled so that the high-resolution image data transferred to the main memory 6 is temporarily stored.

When high-resolution image data is stored in the main memory 6, a memory control CPU 5 for image processing
3 converts this high-resolution image data into, for example, 480 pixels ×
The thinning / expansion processing unit 65 is controlled so as to convert the image data to the 640 pixel monitor display intermediate resolution image data. Thus, the high-resolution image data is read from the main memory 6 by the read control of the memory control circuit 1 and supplied to the thinning / decompression processing unit 65 of the memory control circuit 1.

The high-resolution image data is converted into intermediate-resolution image data by the thinning / expansion processing section 65, and supplied to the video memory 7 via the bus switch 51, the bus line, and the data line. When the intermediate resolution image data is supplied to the video memory 7, the video memory control circuit 52 controls the writing of the video memory 7 so as to temporarily store the intermediate resolution image data, and controls the reading of the video memory 7 so as to read the same. Thereby, the intermediate resolution image data stored in the video memory 7 is read and supplied to the monitor 8 via the D / A conversion circuit 56, the analog switch 57, the buffer 58, and the interface circuit 35.

As described above, the intermediate resolution image data supplied to the video memory 7 is converted into an analog signal by the D / A conversion circuit 56 to be an image signal for display on the monitor of the intermediate resolution. As a result, the image captured by the scanner 28 is displayed on the monitor 8. The system control CPU 54 of the image processing circuit 30 operates the scanner 28 by operating the keyboard 27.
When image processing such as enlargement processing, reduction processing, etc. of the image taken in by the CPU is specified, the memory control CPU 53 performs the specified image processing on the image data read from the main memory 6. The thinning / decompression processing unit 65 is controlled via the main memory control circuit 1 via the. The image data on which the specified image processing has been performed by the thinning / expansion processing section 65 is supplied to the monitor 8. Thus, the image on which the specified image processing has been performed is displayed on the monitor 8. Also, system control CP
The U54 thins out the main memory control circuit 1 and supplies the data (image processing information) indicating the image processing applied to the image data to the decompression processing unit 65 via the bus line and the bus switch.

[Description of Operation of Thinning / Expansion Processing Unit] Next, the operation of the thinning / expansion processing unit 65 will be described. The user checks the image displayed on the monitor 8 as to whether or not the image is the desired image. Specify the recording of the image displayed in.

The system control CPU 54 detects that the recording designation key has been turned on, and, if there is data indicating that recording has been designated and image processing information, via the bus line and the bus switch 51. hand,
The data is supplied to the operation coefficient memory 66 of the thinning / expansion processing unit 65.

The operation coefficient memory 66 temporarily stores the image processing information, if any, and controls the image processing operation block 4 to take in high-resolution image data. When the high-resolution image data is taken into the thinning / decompression processing unit 65 via the bus line and the bus switch 51, it is temporarily stored in the image processing operation block 4.
When the high-resolution image data is stored in the image processing operation block 4, the image processing operation block 4 converts the high-resolution image data into, for example, 1/4 for each line based on the image processing information stored in the operation coefficient memory 66. Image processing control is performed so as to perform thinning processing.

In the 1/4 thinning-out processing, by performing thinning-out processing so that the pixels of the high resolution image data are reduced to 1/4, intermediate resolution image data of 480 pixels × 640 pixels is formed. The intermediate resolution image data is subjected to 1/64 thinning processing. In the 1/64 thinning process, low resolution image data (index image data) of 60 pixels × 80 pixels is formed by performing a thinning process to reduce the pixels of the intermediate resolution image data to 1/64.

The switching of the image processing operation block 4 is controlled by the memory control CPU 53. That is, the memory control CPU 53 selects, for example, image data of each resolution generated by the image processing operation block 4 in the order of high-resolution image data, intermediate-resolution image data, and low-resolution image data, and outputs the data. Control switching. Each resolution image data from the image processing operation block 4 is transferred via the double buffer 73 in the DMA processing unit 68 and
1 and 33 are supplied to the JPEG processing circuit 38.

[Operation of JPEG Processing Circuit] Image data of each resolution transferred via the double buffer 73 in the DMA processing unit 68 of the main memory control circuit 1
The data is supplied to a raster block conversion unit in the JPEG processing circuit 38. The raster block conversion unit divides each image data into processing blocks of 8 × 8 pixels, which is, for example, four times 16 pixels, which is a processing unit of the compression encoding, and supplies this to the compression / decompression processing unit.

Here, each resolution image data is divided into processing blocks of 8 pixels × 8 pixels in the raster block conversion section, while the low resolution image data has an image size of 60 × 80 pixels. is there. For this reason,
If the low-resolution image data is divided into processing blocks of 8 pixels × 8 pixels, the vertical pixels cannot be divided by 8 pixels (60 pixels / 8 pixels = 7.5 pixels). Cannot be divided in units of processing blocks of 8 pixels × 8 pixels.

Thus, when the low-resolution image data is supplied, the raster block converter adds dummy data of 4 pixels × 80 pixels to the upper or lower stage of the image data, thereby obtaining the 60 × 80 pixels. The low-resolution image data of the pixel is defined as low-resolution image data of 64 pixels × 80 pixels. Then, since the pixels in the vertical direction are divisible by 8 pixels, the low-resolution image data of 64 pixels × 80 pixels is divided into 8 processing blocks × 10 processing blocks and supplied to the compression / decompression processing unit. Note that the dummy data is removed at the time of index display, and an image (eg, a black image or a white image) related to the dummy data
Is not added to the index image and displayed.

The compression / decompression processing section is composed of a discrete cosine / transform circuit (DCT circuit), a quantization circuit, and a fixed-length encoding circuit. Supplied. The DCT circuit is
The image data of each resolution is converted on the frequency axis to perform a DCT process to form a DCT coefficient, and the image data of each resolution subjected to the DCT is supplied to a quantization circuit. The quantization circuit is, for example, an MD control CPU
The image data of each resolution is quantized using an appropriate quantization coefficient set by 36, and these are supplied to a fixed-length encoding circuit.

The fixed-length coding circuit performs fixed-length coding on the DCT coefficients of the image data of each resolution quantized with appropriate quantization coefficients, and feeds back the result of the fixed-length coding processing to the MD control CPU 36. MD control CPU
36 forms an optimal quantization coefficient for quantizing the image data in accordance with the result of the fixed-length encoding processing, and supplies this to a quantization circuit. The quantization circuit quantizes the image data using the optimal quantization coefficient set for the second time, and supplies this to the fixed-length encoding circuit. Thus, the fixed-length encoding circuit can perform fixed-length encoding on the image data of each resolution so as to have a predetermined data length.

More specifically, by such a compression encoding process, the intermediate resolution image data is subjected to a fixed length encoding process to a data length of two clusters, which is twice as large as one recording unit, ie, one cluster. The data is subjected to a fixed-length encoding process to a data length of 8 clusters, and the low-resolution image data is 1/15.
A fixed length encoding process is performed on the data length of the cluster. The fixed-length encoded image data of each resolution is supplied to the MD driving circuits 32 and 34 via the CPU interface circuit 39 and the SCSI control circuit 40, respectively. The SCSI control circuit 40 converts operation commands for the MD drive circuits 32 and 34 supplied from the MD control CPU 36 via the CPU interface circuit 39 into SCSI commands. Then, the SCSI control circuit 40 transfers the image data of each resolution to the MD drive circuits 32 and 34 based on the SCSI interface. MD Control C
When the image processing information is added to the supplied image data, the PU 36 supplies the image processing information to the MD driving circuits 32 and 34 together with the image data of each resolution.

[Description of Operation of MD Drive Circuit] Next, the operation of the MD drive circuit will be described. MD control circuit 31,
The image data and image processing information of each resolution from 33 are
Each is supplied to the interface unit. When the image data and the image processing information of each resolution are supplied to the interface unit, the controller controls the interface unit so as to take them into the MD drive circuit. The image data and image processing information of each resolution taken into the MD drive circuit via the interface unit are respectively supplied to the EFM circuit. When the image data and the image processing information of each resolution are supplied to the EFM circuit, the controller performs so-called EFM processing (8-14 modulation processing) on the image data and the image processing information of each resolution fixed-length coded. The EFM circuit is controlled as described above. The EFM-processed image data of each resolution and image processing information are supplied to the disk recording / reproducing unit. When the image data and the image processing information are supplied to the disk recording / reproducing unit, the controller controls the disk recording / reproducing unit to record the image data and the image processing information of each resolution on the mini disks 25 and 26, respectively. As a result, the image data of each resolution and the image processing information thereof are recorded on the mini disks 25 and 26.

Specifically, the mini disks 25 and 26
It is a magneto-optical disk with a diameter of 64 mm,
200 pieces of image data can be rewritten any number of times for each resolution. The image data for 200 sheets is divided into four albums, and the image data for 50 sheets is managed as one album. Therefore, when recording the image data, the user uses the keyboard 27 to select an album in which the image data is to be recorded. Thus, the system control CPU 54 controls the disk recording / reproducing unit via the controller so that the image data of each resolution is captured and recorded in the album selected by the user in the order of capture.

At this time, the low resolution image data is recorded as an index file for an index for displaying a plurality of images recorded in the album on one screen, and the intermediate resolution image data is recorded in the album. The high-resolution image data is recorded as a high-resolution image file for printing for printing an image relating to the high-resolution image data. Be recorded.

[Configuration of the Image Interpolation Processing Apparatus of the Present Embodiment] The configuration of the image interpolation processing apparatus of the present embodiment will be described below with reference to FIGS. The main part of the image interpolation processing device of the present embodiment is a DRAM access control inside the main memory control circuit 1 in the image processing circuit shown in FIG. 20 of the still image control device shown in FIG. It corresponds to the circuit 2, the main memory address generation circuit 3, the image processing operation block 4, and the 16-pixel buffer 5.

Components corresponding to those shown in FIGS. 16 to 21 are denoted by the same reference numerals, and detailed description thereof will be omitted. First, the configuration of the image interpolation processing device according to the present embodiment will be described. As shown in FIG. 1, the image interpolation processing device includes a main memory control circuit 1, a main memory 6, a video memory 7, and a monitor 8.
The main memory control circuit 1 has a DRAM access control circuit 2, a main memory address generation circuit 3, an image processing operation block 4, and a 16 pixel buffer 5. Here, the DRAM access control circuit 2 constitutes reading means for sequentially reading data specified by a physical address, and the main memory address generation circuit 2 generates a virtual logical address for generating a virtual logical address for accessing a specified area. Means and means for storing a pre-virtual logical address for storing the pre-virtual logical address, and a physical address generating means for generating a physical address required for calculation from the pre-virtual logical address and the current virtual logical address. The 16 pixel buffer 5 constitutes a buffer for temporarily storing the read data, and the image processing operation block 4 constitutes an operation means for performing an operation for thinning or decompression processing on the data accumulated in the buffer. I do. Further, when performing the interpolation processing using a plurality of image data, the image interpolation processing apparatus does not reread the image data already used in the interpolation processing of the previous data by the reading means and stores the previous data stored in the buffer. And has a function of reading only newly required data.

Here, the image data stored in the main memory 6 is supplied to the main memory 6 after being read by the above-described scanner 28, and the image data MD2
5 is supplied to the main memory 6 after being read. At this time, the texture data stored in the title memory 6a and the key signal data stored in the key memory 6b are read from the texture data MD26 and then supplied to the title memory 6a and the key memory 6b.

In the main memory 6, high-resolution, medium-resolution and low-resolution image data are recorded in an image data format described later. At this time, character data, image data, and the like are input to the title memory in advance, and the texture data serving as an initial image for image composition is converted to a high-resolution, medium-resolution, and low-resolution image data in the same texture data format as the image data. It is stored at the resolution. At this time, the key memory 6 stores data of the key signal K.

[Configuration of Main Memory Address Generation Circuit]
The main memory address generation circuit 2 loads an additional value indicating an increment with respect to the start address in accordance with the position of the start address from which the image data is read and the scan direction of the start address, and accumulates the added value to the read address to obtain the image data. Has a function of generating a virtual logical address for reading out the data. In the present embodiment, in particular, the main memory address generating circuit 2 includes a virtual logical address generating means for generating a virtual logical address for accessing a designated area and a previous virtual logical address storing means for storing a previous virtual logical address. And having physical address generation means for generating a physical address required for the operation from the previous virtual logical address and the current virtual logical address, and further, when performing interpolation processing using a plurality of image data,
It has a function of generating only a virtual logical address of newly required data without generating a virtual logical address for the image data already used for the interpolation processing of the previous data. Further, the virtual logical address has an integer part and a decimal part, and the physical address indicates an integer part. The decimal part has a function to be used for the operation in the operation circuit of the image processing operation block 4.

As shown in FIG. 2, the main memory address generating circuit starts a 20-bit start consisting of an integer part 12 bits and a decimal part 8 bits from 8-bit data (D7-0) from the CPU bus indicating the start of reading. A start address register 9 for generating and holding an address, an address register 10 for cumulatively adding and holding a 20-bit X and Y output address to the start address, and an integer part 8 based on data from the CPU bus indicating the added value A delta address register 11 for generating and holding a 16-bit delta address consisting of 8 bits and a fractional part of 8 bits;
It has a delta register 12 for holding a delta address at the same timing as the address register 10, and a 20-bit calculator 13 for adding the output of the address register 10 and the output of the delta register 12 to generate a 20-bit cumulative addition signal. . Here, the start address register 9 is supplied with data of an arbitrary start address for image reading from the CPU bus, and the delta address register 11 is provided with an arbitrary delta for image reading corresponding to the start address. Address data is supplied. The load terminal LD of the address register 10 is supplied with an address load signal AL, the select terminal SEL is supplied with an address select signal AS, and the clock terminal CLK is supplied with a clock signal CL. Here, the address load signal AL and the address select signal AS are signals generated according to the DMA operation sequence.

The reason that the start address and the delta address registers are configured in two stages is that if the register is one stage, the register cannot be accessed from the CPU during the DMA operation sequence, so the register value is rewritten. Therefore, even if the register is set in two stages and the DMA operation sequence is in progress, the next DM
This is because the DMA transfer is performed quickly while holding the data for the A transfer. Here, the X address and the Y address are configured to be generated by a common main memory address generation circuit. However, actually, two main memory address generation circuits having the same X address and Y address are prepared and the X address and the Y address are prepared. And the Y address are generated separately. Also, although the main memory address generation circuit 3 in the main memory control circuit shown in FIG. 21 has been shown to generate a 12-bit address signal of MA11 to MA11, as shown in FIG. A 20-bit X address signal and a Y address signal are output, and
The integer part 12 is obtained from the 0-bit X address and Y address signals.
Bit (MA19 to MA8) and decimal part 8 bit (MA7 to MA7)
0). The 12 bits of the integer part are used as a physical address to access a 4096 × 4096 memory space of the main memory 4 composed of DRAM, and 20 bits including a decimal part are used as a logical address. It is used for the interpolation calculation processing in the image processing calculation block 4 shown in FIG. The address conversion circuit 18 includes, for example, a buffer for sequentially storing a 20-bit X address and a Y address signal, a buffer for storing upper 12 bits (MA 19 to 8), a buffer for storing lower 8 bits (MA 7 to MA 0),
A timing signal generator for supplying timing signals for input and output of these buffers.

Here, the address register 10 constitutes a virtual logical address generating means for generating a virtual logical address for accessing a designated area and a previous virtual logical address storing means for storing a previous virtual logical address.
The address conversion means 18 constitutes a physical address generation means for generating a physical address required for the operation from the previous virtual logical address and the current virtual logical address. Further, when performing interpolation processing using a plurality of image data, the start address register 9 and the delta address register 11 do not generate a virtual logical address for the image data already used for the interpolation processing of the previous data. Means for generating only the virtual logical address of the data required for.

As shown in FIG. 3, the address register 10 has a selector 14 and a 20-bit D flip-flop 17. Here, the selector 14
It has a switch 15 and a switch 16. Switch 15
Has a fixed contact 15a and a fixed contact 15b, and a movable contact 15c. The switch 16 has a fixed contact 16a and a fixed contact 16b, and a movable contact 16c. The fixed contact 15a is connected to the output terminal of the 20-bit D flip-flop 17, and the fixed contact 15a has a 20-bit D flip-flop.
X address and Y which are output signals of flip-flop 17
An address signal is provided. The fixed contact 15b is connected to the output terminal of the 20-bit arithmetic unit 13, and the fixed contact 15b is configured to be supplied with the cumulative addition signal ALU from the 20-bit arithmetic unit 13. Further, the movable contact 15c and the fixed contact 16a are connected.
The fixed contact 16b is connected to the output terminal of the start address register 9, and the fixed contact 16b is configured to be supplied with a start address output signal SO from the start address register 9. The movable contact 16c is connected to the input terminal of the 20-bit D flip-flop 17.
The control terminal of the switch 15 has a select terminal SEL.
, And a control terminal of the switch 16 is supplied with an address load signal AL via a load terminal LD. The clock signal CLK is applied to the clock terminal CLK of the 20-bit D flip-flop 17.
Is supplied.

[Operation of the Image Interpolation Processing Apparatus of the Present Embodiment] Next, referring to FIGS. 1, 2, 3 and 4 to 15, the image of the present embodiment thus constructed will be described. The operation of the interpolation processing device will be described. 4, 6, and 8
In FIGS. 10, 12, and 14, points indicated by circles are physical addresses, and points indicated by crosses are logical addresses. In the present embodiment, 16 addresses around the logical address
The pixel is fetched, arithmetic processing is performed from the 16 pixels, and operation is performed to obtain data of a logical address which is a virtual point. Here, an operation is performed to cause the above-described 16-pixel buffer 5 to perform a cache operation. The cache operation is an operation of writing / reading a small-capacity but high-speed 16-pixel buffer 5 to / from a large-capacity but low-speed processing main memory 6. This refers to an operation of performing a write / read process to shorten the processing time as viewed from the main memory 6.

First, the case where there is no cache operation will be described. In FIG. 4, the logical address is changed from P1 to P2.
The operation when the state changes to will be described. This operation is performed when the address change from the logical address P1 to the logical address P2 is 4 in the row direction. In this case, a P1 pixel read range 19 indicating a range of 16 physical addresses indicated by a dotted line around P1 used to calculate the logical address P1, and a solid line around P2 used to calculate the logical address P2 Does not overlap with the P2 pixel reading range 20 indicating the range of 16 physical addresses. That is, a P1 pixel reading range 19 indicating a range of 16 physical addresses indicated by a dotted line around P1 and a P2 pixel reading range 19
It is necessary to separately read the P2 pixel read range 20 indicating the range of 16 physical addresses indicated by a solid line around the area, and there is no physical address to be cached in the 16-pixel buffer 5. Therefore, the logical addresses P1 and P
When the difference from 2 is 4 or more, the cache operation is not performed. When the change of the logical address is 4 or more, the address during that period is not read, so that the operation is considerably reduced. As an example, there is a case where the resolution is converted from a high-resolution original image composed of 2048 × 3072 pixels to a low-resolution image composed of 512 × 768 pixels. Therefore, in this example, since the number of data to be transferred is smaller than that of the original image, efficient operation of the cache is not required. Note that the main scanning is performed in a horizontal direction, that is, a row direction, in which pixels are read. In the P1 pixel read range 19 and the P2 pixel read range 20, read addresses are generated in the main memory address generation circuit 3 by designating a start address and a plus four delta address in an increasing row direction.

In this case, when the column address strobe signal (xRAS) supplied to the main memory 6 for the X address from the DRAM access control circuit 2 is at the low level four times, the reading of the addresses in the four columns in the column direction is performed. to enable. Also, a row address strobe signal (xCA)
When S) is at the low level four times, it is possible to read addresses of four rows in the row direction. As a result, 4 × 4 16 pixels can be read for the P1 pixel, and 4 × 4 16 pixels can be read for the P2 pixel. At this time, the P1 pixel read time TR1 and the P2 pixel read time TR2 are the same time. Further, the P1 calculation time TC1 after the P1 pixel reading time TR1 ends and the P2 pixel reading time TR
The P2 operation time TC2 after the completion of the second operation is the same.

Next, the case of four cache pixels will be described. The operation when the logical address changes from P1 to P2 in FIG. 6 will be described. This operation is performed when the address change from the logical address P1 to the logical address P2 is 3 in the row direction. In this case, a P1 pixel reading range 19 indicating a range of 16 physical addresses indicated by a dotted line around P1 used for calculating the logical address P1, and a P1 used for calculating the logical address P2.
There are four pixels that overlap the P2 pixel reading range 20 indicating the range of 16 physical addresses indicated by the solid line around 2 and these four pixels are cached pixels 21
Becomes That is, after reading the P1 pixel reading range 19 indicating the range of 16 physical addresses indicated by the dotted line around P1, the P2 pixel reading range indicating the range of 16 physical addresses indicated by the solid line around P2 is read. It is not necessary to read all of the 20 pixels, and it operates to read only the newly necessary remaining 12 pixels without rereading the four pixels indicated by the pixel 21 to be cached. Note that the main scanning is performed in a horizontal direction, that is, a row direction, in which pixels are read. Further, the P1 pixel read range 19 and the P2 pixel read range 20 correspond to the main memory address generation circuit 3.
, A read address is generated by designating a start address and a plus 3 delta address in the row direction for the increment.

In this case, as shown in FIG. 7, a column address strobe signal (x) supplied from the DRAM access control circuit 2 to the main memory 6 for the X address.
When RAS) is at the low level four times, it is possible to read addresses of four columns in the column direction. Further, when the row address strobe signal (xCAS) is at the low level four or three times, it is possible to read the addresses of four or three rows in the row direction. Thereby, 4 × 4 for the P1 pixel
As for 16 pixels of P2 pixels, 12 pixels of 3 × 4 can be read. At this time, the P2 pixel read time TR2 is one third shorter than the P1 pixel read time TR1. In addition, P1 after the P1 pixel reading time TR1 ends.
The P2 calculation time TC2 after the end of the P2 pixel reading time TR2 is shorter by one third than the one calculation time TC1.

Next, the case of eight pixels in the cache will be described. In FIG. 8, the operation when the logical address changes from P1 to P2 will be described. This operation is performed when the address change from the logical address P1 to the logical address P2 is 2 in the row direction. In this case, a P1 pixel reading range 19 indicating a range of 16 physical addresses indicated by a dotted line around P1 used for calculating the logical address P1, and a P1 used for calculating the logical address P2.
There are eight pixels that overlap the P2 pixel read range 20 indicating the range of 16 physical addresses indicated by the solid line around the pixel 2, and these eight pixels are cached pixels 21.
Becomes That is, after reading the P1 pixel reading range 19 indicating the range of 16 physical addresses indicated by the dotted line around P1, the P2 pixel reading range indicating the range of 16 physical addresses indicated by the solid line around P2 is read. It is not necessary to read all of the 20 pixels, and it operates so as to read only the newly necessary remaining 8 pixels without rereading the 8 pixels indicated by the pixel 21 to be cached. Note that the main scanning is performed in a horizontal direction, that is, a row direction, in which pixels are read. In the P1 pixel read range 19 and the P2 pixel read range 20, read addresses are generated in the main memory address generation circuit 3 by designating a start address and a plus 2 delta address in the increasing row direction.

In this case, as shown in FIG. 9, a column address strobe signal (x) supplied from DRAM access control circuit 2 to main memory 6 in response to an X address.
When RAS) is at the low level four times, it is possible to read addresses of four columns in the column direction. Further, when the row address strobe signal (xCAS) is at the low level four or two times, it is possible to read the addresses of four or two rows in the row direction. Thereby, 4 × 4 for the P1 pixel
As for 16 pixels and P2 pixels, 8 pixels of 2 × 4 can be read. At this time, the P1 pixel reading time T
The P2 pixel reading time TR2 is shorter by half than R1. Also, P1 after the end of the P1 pixel reading time TR1
The P2 calculation time TC2 after the end of the P2 pixel read time TR2 is shorter than the calculation time TC1 by half.

Next, the case of a cache having 12 pixels will be described. In FIG. 10, the logical addresses are changed from P1 to P.
The operation when the number changes to 2 will be described. This operation is performed when the address change from the logical address P1 to the logical address P2 is 1 in the row direction. In this case, a P1 pixel read range 19 indicating a range of 16 physical addresses indicated by a dotted line around P1 used to calculate the logical address P1, and a solid line around P2 used to calculate the logical address P2 There are 12 pixels that overlap with the P2 pixel read range 20 indicating the range of 16 physical addresses indicated by, and these 12 pixels are the pixels 21 to be cached. That is, 1 shown by a dotted line around P1
After reading the P1 pixel reading range 19 indicating the range of six physical addresses, 16 shown by a solid line around P2 is read.
P2 pixel reading range 2 indicating the range of physical addresses
It is not necessary to read all 0's, and it operates to read only the newly required remaining 4 pixels without rereading the 12 pixels indicated by the pixel 21 to be cached. Note that the main scanning is performed in a horizontal direction, that is, a row direction, in which pixels are read. Also, the P1 pixel reading range 19 and P
In the two-pixel reading range 20, the main memory address generating circuit 3 generates a read address by designating a start address and a plus one delta address in the row direction corresponding to the increase in the row direction.

In this case, as shown in FIG.
When the column address strobe signal (xRAS) supplied to the main memory 6 with respect to the X address from the access control circuit 2 is at a low level four times, it is possible to read addresses in four columns in the column direction. Further, when the row address strobe signal (xCAS) is at the low level four or one time, it is possible to read the address of four rows or one row in the row direction. As a result, 4 pixels are obtained for the P1 pixel.
With regard to 16 × 4 pixels and P2 pixels, 4 × 1 × 4 pixels can be read. At this time, the P2 pixel read time TR2 is two-thirds of the P1 pixel read time TR1.
Be shorter. Further, the P2 pixel read time TR2 is longer than the P1 calculation time TC1 after the end of the P1 pixel read time TR1.
The P2 operation time TC2 after the end is reduced by two thirds.

Next, the case of a cache of 16 pixels will be described. In FIG. 12, the logical addresses are changed from P1 to P.
The operation when the number changes to 2 will be described. This operation is performed when the change in the address of the integer part from the logical address P1 to the logical address P2 is 0. In this case, a P1 pixel read range 19 indicating a range of 16 physical addresses indicated by a dotted line around P1 used to calculate the logical address P1, and a solid line around P2 used to calculate the logical address P2 There are 16 pixels that overlap with the P2 pixel read range 20 indicating the range of 16 physical addresses indicated by {circle around (1)}, and these 16 pixels are the pixels 21 to be cached. That is, all the pixels required for the operation are common, and after reading the P1 pixel reading range 19 indicating the range of 16 physical addresses indicated by the dotted line around P1, the 16 pixels indicated by the solid line around P2 are read. It is not necessary to read the P2 pixel reading range 20 indicating the range of the physical address, and operates so as to use 16 pixels indicated by the pixels 21 to be cached. Note that the main scanning is performed in a horizontal direction, that is, a row direction, in which pixels are read. Also,
P1 pixel reading range 19 and P2 pixel reading range 20
Means that the main memory address generation circuit 3 generates a read address by designating a start address and a delta address of a decimal part of the increment in the row direction, respectively.

In this case, as shown in FIG.
When the column address strobe signal (xRAS) supplied to the main memory 6 with respect to the X address from the access control circuit 2 is at a low level four times, it is possible to read addresses in four columns in the column direction. In addition, when the row address strobe signal (xCAS) is at the low level four or one time, the idle reading is enabled. As a result, 4 × 4 16 pixels for the P1 pixel and nothing for the P2 pixel are read. At this time, the P2 pixel read time TR2 is considerably shorter than the P1 pixel read time TR1. The P2 pixel read time T is longer than the P1 calculation time TC1 after the end of the P1 pixel read time TR1.
The P2 operation time TC2 after the end of R2 becomes considerably short.

As described above, it can be understood that the cache operation with respect to the change of the logical address becomes effective depending on the direction of the enlargement processing of the image data. The following effects are obtained when the operation is performed without using the cache. 100% when the reduction ratio is 1/4, approximately 150% when the reduction ratio is 1/2, approximately 200% when the enlargement ratio is 1/1, approximately 250% when the enlargement ratio is 2/1, and when the enlargement ratio is 4/1. About 300
%. In the above example, the operation of the address cache is shown only by the change of the logical address in the row direction. However, the operation can be similarly applied to the change of the logical address in the column direction. Hereinafter, an example of a change in the logical address in the column direction will be described.

Next, a description will be given of the case of a cache having 12 pixels in the column direction. In FIG. 14, the operation when the logical address changes from P1 to P2 in the column direction will be described.
This operation is performed when the address change from the logical address P1 to the logical address P2 is 1 in the column direction. In this case, P1 used to calculate the logical address P1
, A P1 pixel reading range 19 indicating a range of 16 physical addresses indicated by a dotted line, and a P2 indicating a range of 16 physical addresses indicated by a solid line around P2 used for calculating a logical address P2. There are 12 pixels that overlap the pixel reading range 20, and these 12 pixels are the cached pixels 21. That is, P1 indicating a range of 16 physical addresses indicated by a dotted line around P1
After reading the pixel read range 19, it is not necessary to read the entire P2 pixel read range 20 indicating the range of 16 physical addresses indicated by solid lines around P2. Operates so as to read only the newly required remaining four pixels without re-reading. Note that the pixel is read in the horizontal direction,
That is, the main scanning is performed in the row direction. In the P1 pixel read range 19 and the P2 pixel read range 20, read addresses are generated in the main memory address generation circuit 3 by designating a start address and a plus one delta address corresponding to the increment in the column direction.

In this case, as shown in FIG.
When the column address strobe signal (xRAS) supplied from the access control circuit 2 to the main memory 6 with respect to the X address is at the low level five times, it is possible to read addresses in five columns in the column direction. Further, when the row address strobe signal (xCAS) is at the low level four times, it is possible to read the addresses of four rows in the row direction. As a result, for the P1 pixel, 4 × 4 16 pixels, P2
As for pixels, 4 × 1 pixels can be read. At this time, P2 is longer than P1 pixel reading time TR1.
The pixel reading time TR2 becomes considerably shorter. Also, P1
The P2 operation time TC2 after the end of the P2 pixel read time TR2 is considerably shorter than the P1 operation time TC1 after the end of the pixel read time TR1.

[Operation of Main Memory Address Generation Circuit]
As shown in FIG. 2, the main memory address generation circuit
By appropriately changing the start address and the delta address which is the increment of the start address, the operation is performed to change the generated value of the main memory address and change the image reading range.

First, the operation without a cache will be described.
In the case of the horizontal reversal operation of the image, the start address register 9 is supplied with the data of the start address for reading the P1 image read range 19 of the image from the CPU bus, and the delta address register 11 corresponds to the start address. X is supplied with data of a plus 4 delta address. The load terminal LD of the address register 10 is supplied with an address load signal AL, the select terminal SEL is supplied with an address select signal AS, and the clock terminal CLK is supplied with a clock signal CL.

In the start address register 9,
In the main scanning in the X direction, the address is sequentially incremented by 4 in the X direction from the start address. When reading of the address of one line in the X direction is completed, the address is incremented by 1 in the Y direction, and then sequentially incremented by 4 to 16
The pixel is incremented. Here, in the start address register 9, 2 bits consisting of an integer part of 12 bits and a decimal part of 8 bits are derived from 8-bit data from the CPU bus.
Data of a 0-bit start address is generated. The same applies to the following description.

In the address register 10, when the address load signal AL becomes active, the switch 16 of the selector 14 is controlled to switch, so that the fixed contact 16b and the movable contact 16c are connected, and the start address output signal SO is loaded. You. The address load signal AL is supplied in response to a DMA start pulse indicating the start of a DMA sequence. This address load signal AL is supplied only once in the DMA sequence. That is, the address load signal AL becomes active once at the start of the DMA sequence,
Until the start of the MA sequence, the switch 16 of the selector 14 is switched and controlled so that the fixed contact 16a and the movable contact 1
6c is connected.

After the switch 16 of the selector 14 is switched and controlled to connect the fixed contact 16a and the movable contact 16c, when the address select signal AS becomes active in the address register 10, the switch 15 of the selector 14 The switching control is performed to connect the fixed contact 15b and the movable contact 15c, and the cumulative addition signal ALU is loaded. The address select signal AS is
D in which DMA transfer is actually performed in the DMA sequence
It is supplied in response to the MA transfer pulse. The DMA transfer pulse does not always occur continuously in the DMA sequence but occurs several times intermittently. If the address select signal AS is an X-direction main scan in an address table having 10 × 10 address data, X is 100
Times and Y is fed ten times. That is, the address select signal AS changes at the timing of incrementing the address. Then, in the address register 10, the address is cumulatively added each time the address select signal AS becomes active.

After the switch 16 of the selector 14 is switched and the fixed contact 16a and the movable contact 16c are connected, when the address select signal AS becomes negative in the address register 10, the switch 15 of the selector 14 Switching is controlled so that the fixed contact 15a and the movable contact 15c are connected, and a 20-bit D
The X and Y address signals which are output signals of the flip-flop 17 are loaded. The address select signal AS is negative when no DMA transfer pulse is generated in the DMA sequence. Thus, DM
The reason for loading the X and Y address signals, which are the output signals of the 20-bit D flip-flop 17 when the DMA transfer pulse is not generated in the A sequence, is that the DMA transfer pulse is output regardless of the timing of the clock signal CL. This is because the cumulative addition signal ALU is loaded at the timing when it is generated and cumulatively added, and the same data is held at the timing when no DMA transfer pulse is generated.

The start address output signal SO, the accumulated addition signal ALU or the X and Y address signals loaded into the address register 10 in this way are selected by the selector 14 and then output to the 20-bit D flip-flop 1.
7 is supplied. Start address output signals SO, X, and Y address signals latched by the 20-bit D flip-flop 17 based on the cycle of the clock signal CL are output, and supplied to one input terminal A of the 20-bit arithmetic unit 13.

In the delta address register 11, a plus 4 delta address for the X address is loaded. The load timing in the delta address register 11 is performed in correspondence with the address increment timing in the start address register 9 described above. Here, the delta address register 11 generates 16-bit delta address data composed of an 8-bit integer part and a 8-bit decimal part from the 8-bit data from the CPU bus. The same applies to the following description. The delta address output signal DO output from the delta address register 11 is loaded into the delta register 12 when the address load signal AL is active. Delta address output signal D
The timing at which O is loaded into the delta register 12 is performed in accordance with the timing at which the start address output signal SO in the address register 10 is loaded. Then, the delta address output from the delta register 12 is supplied to the other input terminal B of the 20-bit operation unit 13. In the 20-bit arithmetic unit 13, the 20-bit X and Y address signals supplied to one input terminal A and the plus 4 which is the 16-bit delta address supplied to the other input terminal B are added. 20
A bit cumulative addition signal ALU is output. Then, each time it is sequentially incremented, the cumulative addition signal ALU which is increased by 4 is supplied to the address register 10. In this way, by adding plus 4 to the X address and accumulatively adding to the start address output signal and converting it into 12-bit integer part (MA19-8) and 8-bit decimal part (MA7-0), cache No address can be generated.

Here, the start address and the delta address registers are configured in two stages, respectively. If the register has only one stage, the CPU cannot access the register during the DMA operation sequence. Although the value cannot be rewritten, the registers are set in two stages, and even if the address register 10 and the delta register 12 in the second stage are operating in the DMA operation sequence, the start address register 9 and the delta The following D is stored in the address register 11.
By holding the data for MA transfer, the next DMA transfer can be performed quickly.

Similarly, in the case of a cache of four pixels, the start address register 9 and the digital address register 11 set a plus 3 delta address in the X direction with respect to the start address,
In the case of cache 8 pixels, a plus 2 delta address is set in the X direction for the start address, and in the case of cache 12 pixels, a plus 1 delta address is set in the X direction for the start address. In the case of 16 pixels of cache, a delta address of 0 is set to the start address, and in the case of 12 pixels of cache in the column direction, a delta address of 1 is added to the start address in the Y direction. If the respective settings are made, the other operations are the same as those described above, and a description thereof will be omitted.

[Explanation of Format of Image Data of Mini Disc] Next, the format of image data of the mini disc will be described. The image data recorded in the format of the image data of the mini-disc is recorded in the image data MD25 shown in FIG. The mini disc on which such image data of each resolution is recorded has a new format for recording image data described below.

[Cluster Structure] First, the cluster structure will be described. Recording and reproduction are performed on the mini-disc in units of “cluster”. One cluster corresponds to, for example, two or three tracks, and one data track is formed by successively recording these clusters in time. The one cluster is composed of a sub-data area of 4 sectors (1352 is 2352 bytes) and a main data area of 32 sectors, and each address is recorded for each sector.

The data is actually recorded in each sector in the area of 2,048 bytes out of 2352 bytes, and the remaining byte area includes header data and an error correction code based on a periodic pattern and an address. Etc. are recorded. When sub-data and subsequent data are recorded in another area in a 4-sector sub-data area,
Linking data or the like indicating that the subsequent data is recorded in another area is recorded. Further, TOC data, audio data, image data, and the like are recorded in the main data area of 32 sectors.

[Track Structure] Next, the track structure will be described. The entire area of the mini disk is composed of a pit area in which data is recorded in embossed pits, and a magneto-optical area (MO area) in which a groove is provided and data is recorded and reproduced by a magneto-optical method. The pit area is a reproduction-only management area in which a P-TOC (pre-mastered table of contents), which is management information recorded on the mini-disc, is recorded, and a P-TOC sector described later is repeatedly recorded. ing.

The MO area extends from immediately after the lead-in area on the innermost peripheral side of the disk to the end of the lead-out area on the outermost peripheral side of the disk. And this MO
Of the area, a recordable area from immediately after the lead-in area to immediately before the lead-out area on the outermost peripheral side of the disk is a recordable area. The recordable area includes a recording / playback management area formed at the head of the recordable area, and a recordable area formed immediately after the recording / playback management area and immediately before the lead-out area.

The data track includes “FL1”, “FL”
Data files having image data indicated as "2" and "FL3" and "Data U-TOC" for managing each data file are recorded. "Data U-TO
"C" may be recorded at any position within the recordable area. However, in the still image control device, among the data files of the image data, the data file is the innermost disk side of the disk. Data file "FL1"
Is recorded just before.

Next, the "data U-TOC" is stored in each data file "FL1", "FL2",
"FL3" is collectively managed as one data track. The unrecorded block “EB” in this data track and in the data track is “Data U-TO” recorded before the data file “FL1” 109.
“C” is managed in cluster units. The free area is a margin area.

[Structure of Data Track] Next, the structure of the data track will be described. The configuration of each data file “FL1”, “FL2”, “FL3” having image data and the data track on which the data U-TOC is recorded will be described. Each data file recorded in the data track is managed as a part (a track portion on which a series of physically continuous data is recorded on the disk) by the data U-TOC recorded in the data track. Has become.

The data U-TOC is recorded at the physical head position of the data track. That is, the data U is located at the position closest to the inner circumference of the disk in the data track.
-The TOC is recorded. When the data track is divided into a plurality of parts, the data U-TOC is recorded at the head of the part located on the innermost side of the disk.

The data U-TOC includes a boot area of one cluster and a volume management area of 16 clusters. The area following the data U-TOC is a file extents area. The file extensions area includes data files “FL1”, “FL2”, “FL3”,
“EB” and the like are recorded. A data file can be further recorded in the unrecorded block “EB”.

The volume management area is 0 to 1
023, which is a total of 1024 management blocks. The data area in one management block is 2048 bytes, and each data recorded in this management block is management information for recording / reproducing a data file.

[Description of File and Hierarchical Structure of File] Next, a description of the hierarchical structure of a file and a file will be given with reference to FIG. Files used in the still image control device include a management file, an image file, an index image file, and the like. The extension of the file name of the management file is “PMF”. By detecting the extension of “PMF”, the file is identified as a management file. The management file contains a comprehensive information management file (OV INF. PMF (f
1)), image data management file (PIC INF. P
MF (f3)), print data management file (PRT)
INF. PMF (f17)), playback control management file (PMS INF. PMF).

The extension of the file name of each image file is “PMP”. By detecting the extension of “PMP”, the file is identified as an image file. The image files include a high-resolution image file for recording high-resolution image data HD and an intermediate-resolution image file for recording intermediate-resolution image data SD. The intermediate resolution image file includes a “PSNnnnn.PMP file” having image data of 640 pixels × 480 pixels with an aspect ratio of 4: 3, and a “PSNnnnnnn” having image data of 848 pixels × 480 pixels with an aspect ratio of 16: 9. .PMP file ".

The high-resolution image file is composed of a “PHPnnnn.PMP file” having image data of 1536 pixels × 1024 pixels with an aspect ratio of 3: 2, and image data of 1920 pixels × 1080 pixels with an aspect ratio of 16: 9. "PHWnnnnnn.PMP file"
There is. As a file for recording an ultra-high-resolution image file HD as one of the high-resolution image files, a “PUPnnnnnn.PMP file” having image data of 3072 pixels × 2048 pixels with an aspect ratio of 3: 2, 1920 pixels x 16: 9 ratio
“PHWnnnn” having image data of 1080 pixels
n. PMP file ". Note that the extension is "PM
The first three characters (for example, PHP or the like) of the file name of the image file set as “P” are determined according to the type of the image,
The next five characters (nnnnn) are determined by the image numbers assigned in the order in which the image files were formed.

Next, the still image control device manages image data recorded on the mini-disc in a hierarchical directory structure. This hierarchical directory is, for example, as shown in FIG. 22, a directory D1 (PIC MD), in which file management is performed. The directory D1 includes a comprehensive information management file f1 (OV) for managing the entire information. INF. PMF) and a comprehensive index file f2 (OV) for managing the entire index file IDX. PMX) and image directories D2 to D4 of each album (PIC0000 to PI
C00002).

In this example, the directory numbers "00000" to "00" are used as the image directories.
002 ”image directories (PIC00000)-
(PIC00002). The five characters following "PIC" in each image directory are assigned as directory numbers in the order of formation of each image directory, thereby indicating the image directory name.

The directory (PIC) MD), a print directory (PRINT) for managing print control data such as print color, print size, rotation, and the like, and a telop directory (TER) for managing telops such as titles of images to be displayed on a monitor.
OP. PMO) and a keyword search directory (KW) attached to each image and the image number of each image. DTBS. P
MO) and a time stamp directory (TS DTBS. PMO) and a playback control directory (PMSEQ) for managing program playback that plays only specified images.

The image directory D2 (PIC0000)
0) includes an image data management file f3 (PIC) for managing a plurality of image files designated by a directory number “00000”. INF. PMF) and an image index file f4 (PIDX000.PMX) in which index images of the image directory D2 are combined.
Is recorded. Also, this image directory D2
Includes an intermediate resolution image file f formed based on the image data designated by the image number “00000”.
5 (PSN0000.PMP) and a high-resolution image file f6 (PHP0000.PMP). Also, an intermediate resolution image file f7 (PSN00001.PMP) and an ultra-high resolution image file f9 (PUP00001.PMP) formed based on the image file data designated by the image number “00001” are recorded. . An intermediate resolution image file f10 (PSN00002.PMP) formed based on the image data designated by the image number “00002” and the image data formed based on the image data designated by the image number “00003” Intermediate resolution image file f11 (PSN
00003. PMP) is recorded.

Next, the image directory (PIC00001) specified by the directory number “00001” is stored in the image data management file f12 (PIC I
NF. PMF) and two index files f13 and f14 (PID) for managing the index image of each image.
X000. PMX, PIDX001. PMX) is recorded. Note that two image index files f
13, f14, the image directory D3 (P
IC00001) to manage an index image corresponding to an image file recorded therein.
Formally, two index files are linked and used.

Next, the print directory (PRIN)
T) includes a print data management file f17 (PRT) for managing a plurality of print data files.
INF. PMF) and print data files f18 and f19 managed by the print data management file.
(PRT000.PMO to PRT001.PMO) are recorded. Next, the playback control directory (PMSE
Q) includes a playback control management file (PMS) for managing a playback control data file recorded in a playback control directory (PMSEQ). INF. PMF) and a plurality of reproduction control data files (PMS000.PMO to PMSnnn.PM) for controlling the image sequence.
O) is recorded.

[0106]

According to the image interpolation processing apparatus of the present invention,
Virtual logical address generating means for sequentially generating virtual logical addresses for accessing a designated area; previous virtual logical address storing means for storing previous virtual logical addresses generated by the virtual logical address generating means; A physical address generating means for generating a physical address necessary for the operation from the current virtual logical address, a reading means for sequentially reading data specified by the physical address, and a buffer for temporarily storing data read by the reading means. An arithmetic unit for performing a predetermined operation on the data stored in the buffer, and performing the interpolation process using a plurality of image data. Data that is newly needed using the previous data stored in the buffer without rereading So it was to read the ask,
There is an effect that the image interpolation processing can be performed at high speed while giving a degree of freedom to the configuration of the memory and the like and adopting the sequential reading method.

Further, according to the image interpolation processing apparatus of the present invention, in the above description, the virtual logical address has an integer part and a decimal part, the physical address indicates the integer part, and the decimal part is used for the arithmetic operation by the arithmetic means. Therefore, there is an effect that an address can be specified by a physical address of an integer part with respect to the specified virtual logical address, and the operation of the decimal part can be performed to calculate the position of the virtual logical address.

Further, according to the image interpolation processing apparatus of the present invention, in the above description, the readout unit reads out data of 16 pixels at a maximum of 4 pixels each in the main scanning direction and the sub-scanning direction around the virtual logical address. As a result, there is an effect that it is possible to read out only data of newly required pixels without reading out duplicate data among the already read out 16 pixels.

Further, according to the image interpolation processing apparatus of the present invention, in the above description, the buffer stores data of up to four pixels each of 16 pixels in the main scanning direction and the sub-scanning direction around the virtual logical address. Therefore, there is an effect that writing and reading can be performed at a high speed in a small-capacity buffer.

Further, according to the image interpolation processing apparatus of the present invention, in the above description, the calculating means performs a thinning or decompression operation on the data. There is an effect that a processing operation can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of an image interpolation processing device according to the present invention.

FIG. 2 is a diagram showing a circuit configuration of a main memory address generation circuit provided in a memory control circuit in an image processing circuit of a still image control device using an embodiment of the image interpolation processing device according to the present invention.

FIG. 3 is a diagram showing a circuit configuration of an address register in a main memory address generation circuit provided in a memory control circuit in an image processing circuit of a still image control device using an embodiment of the image interpolation processing device according to the present invention. It is.

FIG. 4 is a diagram showing an operation without a cache of the image interpolation processing apparatus according to the embodiment of the present invention;

FIG. 5 is a timing chart showing an operation without caching of the image interpolation processing apparatus according to one embodiment of the present invention;

FIG. 6 is a diagram illustrating an operation of four pixels of a cache in an embodiment of an image interpolation processing device according to the present invention.

FIG. 7 is a timing chart showing an operation of four pixels of the cache in the embodiment of the image interpolation processing device according to the present invention.

FIG. 8 is a diagram illustrating an operation of eight pixels of a cache in an embodiment of an image interpolation processing device according to the present invention.

FIG. 9 is a timing chart showing an operation of eight pixels of a cache in an embodiment of the image interpolation processing device according to the present invention.

FIG. 10 is a diagram illustrating an operation of 12 pixels of a cache in an embodiment of an image interpolation processing device according to the present invention.

FIG. 11 is a timing chart showing the operation of 12 pixels of the cache in the embodiment of the image interpolation processing device according to the present invention.

FIG. 12 is a diagram illustrating an operation of 16 pixels of a cache in an embodiment of an image interpolation processing device according to the present invention.

FIG. 13 is a timing chart showing the operation of 16 pixels of the cache in the embodiment of the image interpolation processing device according to the present invention.

FIG. 14 is a diagram illustrating the operation of 12 pixels in the column direction cache of the image interpolation processing apparatus according to an embodiment of the present invention.

FIG. 15 is a timing chart showing the operation of 12 pixels in the column direction cache in the embodiment of the image interpolation processing device according to the present invention.

FIG. 16 is an external view of a still image control device using an embodiment of the image interpolation processing device according to the present invention.

FIG. 17 is a block diagram illustrating a configuration of a still image control device using an embodiment of the image interpolation processing device according to the present invention.

FIG. 18 is a block diagram illustrating a configuration of an MD control circuit of a still image control device using an embodiment of the image interpolation processing device according to the present invention.

FIG. 19 is a block diagram illustrating a configuration of an interface circuit of a still image control device using an embodiment of an image interpolation processing device according to the present invention.

FIG. 20 is a block diagram illustrating a configuration of an image processing circuit of a still image control device using an embodiment of the image interpolation processing device according to the present invention.

FIG. 21 is a block diagram illustrating a configuration of a main memory control circuit in an image processing circuit of a still image control device using an embodiment of the image interpolation processing device according to the present invention.

FIG. 22 is a diagram illustrating a hierarchical directory structure of image data of a still image control device using an embodiment of an image interpolation processing device according to the present invention.

[Explanation of symbols]

1 main memory control circuit, 2 DRAM access control circuit, 3 main memory address generation circuit, 4 image processing operation block, 516 pixel buffer, 6 main memory, 7 video memory, 8 monitor, 9 start address register, 10 address register, 11 Delta address register, 12
Delta register, 13 20-bit arithmetic unit, 14 selector, 15 switch, 16 switch, 172
0-bit D flip-flop, 18 address conversion circuit, 19 P1 pixel read range, 20 P2 pixel read range, 21 cached pixels, TR1 P1
Pixel reading time, TR2P2 pixel reading time, TC
1 P1 calculation time, TC2 P2 calculation time, 24 still image control devices, 25 image data MD, 26 texture MD, 27 keyboard, 28 scanner, 29 printer, 30 image processing device, 31 MD control circuit, 32 MD drive circuit, 33 MD control circuit, 34MD drive circuit, 35 interface circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical display location H04N 1/00 H04N 1/387 1/387 G06F 15/66 355C

Claims (5)

[Claims] 1. A virtual logical address generating means for sequentially generating virtual logical addresses for accessing a designated area, and a previous virtual logical address storing means for storing a previous virtual logical address generated by the virtual logical address generating means. Physical address generating means for generating a physical address required for operation from the previous virtual logical address and the current virtual logical address; reading means for sequentially reading data specified by the physical address; And a calculating means for performing a predetermined operation on the data stored in the buffer. When performing the interpolation processing using a plurality of image data, the interpolation processing of the previous data is already performed. The image data used for the above is stored in the buffer without being re-read by the reading means. Using the previous data, the image interpolation processing apparatus is characterized in that so as to read only the newly required data. 2. The image interpolation processing device according to claim 1, wherein the virtual logical address has an integer part and a decimal part, the physical address indicates the integer part, and the decimal part is used for an operation in the arithmetic means. An image interpolation processing device characterized by being used. 3. The image interpolation processing apparatus according to claim 1, wherein said readout means reads out 16-pixel data of a maximum of 4 pixels in each of the main scanning direction and the sub-scanning direction around the virtual logical address. An image interpolation processing device, characterized in that: 4. The image interpolation processing apparatus according to claim 1, wherein the buffer includes a maximum of four pixels each in the main scanning direction and the sub-scanning direction around the virtual logical address.
An image interpolation processing device wherein data of six pixels is stored. 5. The image interpolation processing apparatus according to claim 1, wherein said calculation means performs a calculation of thinning or decompression processing on said data.