JPH1051328A - Squelch control circuit for receiver - Google Patents

Squelch control circuit for receiver

Info

Publication number
JPH1051328A
JPH1051328A JP20212696A JP20212696A JPH1051328A JP H1051328 A JPH1051328 A JP H1051328A JP 20212696 A JP20212696 A JP 20212696A JP 20212696 A JP20212696 A JP 20212696A JP H1051328 A JPH1051328 A JP H1051328A
Authority
JP
Japan
Prior art keywords
signal
frequency
set value
cpu
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20212696A
Other languages
Japanese (ja)
Inventor
Yukiteru Hoshi
幸輝 星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP20212696A priority Critical patent/JPH1051328A/en
Publication of JPH1051328A publication Critical patent/JPH1051328A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To operate a control circuit under an optimum setting at all times without the need for setting by variable resistors for all operating frequencies by solving a problem of setting by the variable resistors for each frequency depending on the frequency characteristic in a conventional squelch control circuit. SOLUTION: An analog switch 1 inserted to an audio signal line is subject to close/open control by a CPU 5. The CPU 5 compares a reception level with a set value and provides an output of a squelch control signal to control the switch 1. A value set by a variable resistor 2 is stored by the CPU 5 into a memory 6 together with frequency data of a received signal and the stored setting data are read corresponding to the frequency based on the received frequency data and the read signal is compared with a level of a received signal and a squelch control signal is outputted. Thus, a noise signal is eliminated from the audio signal line.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、受信機のスケルチ
制御回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a squelch control circuit for a receiver.

【0002】[0002]

【従来の技術】受信機では、空中線から入力される受信
信号が無い場合は、スピーカ等から雑音が出されるのを
防ぐためにスケルチ制御回路が用いられる。
2. Description of the Related Art In a receiver, a squelch control circuit is used to prevent noise from being output from a speaker or the like when there is no reception signal input from an antenna.

【0003】図2は従来のスケルチ制御回路のブロック
図で、空中線で受信された受信信号は、復調されオーデ
ィオ(Audio)信号としてスケルチ制御回路に入力
される。オーディオ信号は信号ラインを閉/開するアナ
ログスイッチ1を通してスピーカ等へ向け出力される。
FIG. 2 is a block diagram of a conventional squelch control circuit. A received signal received by an antenna is demodulated and input to the squelch control circuit as an audio signal. The audio signal is output to a speaker or the like through an analog switch 1 for closing / opening a signal line.

【0004】アナログ・スイッチ1の閉/開制御は、コ
ンパレータ7を用いて行なわれる。コンパレータ7へ
は、受信信号の一部を検波した受信レベル値と、電源電
圧を可変抵抗器8により設定した設定値が入力される。
コンパレータ7は、この2つの値を比較し、受信レベル
値が設定値以上になった場合にアナログ・スイッチ1が
閉となりオーディオ出力がスピーカ等に出力され、受信
レベル値が設定値以下になるとアナログ・スイッチ1を
開くように制御を行う。
The closing / opening control of the analog switch 1 is performed by using a comparator 7. The comparator 7 receives a reception level value obtained by detecting a part of the reception signal and a set value obtained by setting the power supply voltage by the variable resistor 8.
The comparator 7 compares these two values, and when the reception level value exceeds the set value, the analog switch 1 is closed and the audio output is output to a speaker or the like.・ Control to open switch 1.

【0005】[0005]

【発明が解決しようとする課題】上記従来のスケルチ制
御回路では、通常、受信信号が無い場合にアナログ・ス
イッチ1が開となってオーディオ信号ライン(スピーカ
等への出力)に雑音が出力されないように可変抵抗器8
による設定値を最高感度点に設定している。しかし、受
信機の周波数特性により受信レベル値が周波数によって
変化するため、周波数によっては、アナログ・スイッチ
1が閉となり雑音が出力されてしまう。したがって、そ
のたびに可変抵抗器8の値を設定変更しなければならな
い欠点があった。
In the above-mentioned conventional squelch control circuit, normally, when there is no reception signal, the analog switch 1 is opened so that noise is not output to an audio signal line (output to a speaker or the like). Variable resistor 8
Is set to the highest sensitivity point. However, since the reception level value changes depending on the frequency due to the frequency characteristics of the receiver, the analog switch 1 is closed and the noise is output depending on the frequency. Therefore, there is a disadvantage that the value of the variable resistor 8 must be changed every time.

【0006】本発明の目的は、この問題点の周波数特性
による周波数毎の可変抵抗器の設定を解決し、全ての運
用周波数において可変抵抗器の設定変更を行なうことな
く、常に最適の設定でスケルチ制御ができるスケルチ制
御回路を提供することにある。
An object of the present invention is to solve the problem of setting the variable resistor for each frequency based on the frequency characteristic, and to always squelch the optimum setting without changing the setting of the variable resistor at all operating frequencies. It is to provide a squelch control circuit capable of controlling.

【0007】[0007]

【課題を解決するための手段】上記の目的は、オーディ
オ信号の受信レベルを設定値と比較してスケルチ制御信
号を出力するCPUと、該CPUによって、受信信号の
周波数データをもとに周波数毎に上記受信レベルと比較
する設定値を格納するとともに読み出されるメモリとを
設けたことによって達成される。
SUMMARY OF THE INVENTION The object of the present invention is to provide a CPU that compares a reception level of an audio signal with a set value and outputs a squelch control signal. And a memory for storing and reading a set value to be compared with the reception level.

【0008】上記の手段によると、CPUは、オーディ
オ信号の受信レベルと可変抵抗器等による設定値とを比
較してスケルチ制御信号を出力し、受信機のオーディオ
信号をアナログ・スイッチで閉/開しスケルチ制御す
る。またCPUは、上記受信レベルと比較する設定値を
受信信号の周波数データをもとに周波数毎にメモリに格
納する。さらにCPUは、次回から受信信号の周波数デ
ータによりメモリに格納した設定値を読み出して受信レ
ベルと比較することによりスケルチ制御信号を出力する
よう動作する。
According to the above means, the CPU compares the reception level of the audio signal with the set value of the variable resistor or the like, outputs a squelch control signal, and closes / opens the audio signal of the receiver with an analog switch. Squelch control. Further, the CPU stores the set value to be compared with the reception level in the memory for each frequency based on the frequency data of the reception signal. Further, the CPU operates so as to output the squelch control signal by reading the set value stored in the memory from the next time based on the frequency data of the received signal and comparing it with the received level.

【0009】[0009]

【発明の実施の形態】以下本発明の実施の形態を図面に
より説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0010】図1は、本発明の一実施形態のスケルチ制
御回路のブロック図を示す。受信機による受信信号は図
示しない復調回路により復調されオーディオ信号として
入力される。オーディオ信号ラインにはスケルチ制御の
閉/開をするアナログ・スイッチ1が挿入され、オーデ
ィオ信号はこのスイッチ1を通してスピーカ等へ出力さ
れる。アナログ・スイッチ1の閉/開制御はCPU5を
用いて行なう。
FIG. 1 is a block diagram showing a squelch control circuit according to an embodiment of the present invention. A signal received by the receiver is demodulated by a demodulation circuit (not shown) and input as an audio signal. An analog switch 1 for closing / opening the squelch control is inserted into the audio signal line, and the audio signal is output to a speaker or the like through the switch 1. The closing / opening control of the analog switch 1 is performed using the CPU 5.

【0011】CPU5は、アナログ・ディジタル変換器
3によりディジタル化された受信レベル値と、可変抵抗
器2から入力されアナログ・ディジタル変換器4により
ディジタル化された設定値とを比較し、受信レベル値が
設定値以上になったときアナログ・スイッチ1に対して
閉の制御、受信レベル値が設定値以下になったときアナ
ログ・スイッチ1を開に制御するスケルチ制御信号を出
力する。
The CPU 5 compares the reception level value digitized by the analog / digital converter 3 with the set value input from the variable resistor 2 and digitized by the analog / digital converter 4, and When the received signal level is equal to or greater than the set value, the squelch control signal for controlling the analog switch 1 to be closed and for controlling the analog switch 1 to be opened when the received level value is equal to or less than the set value are output.

【0012】可変抵抗器2は、受信信号が無い場合オー
ディオ信号ラインに雑音が出力されないようアナログ・
スイッチ1を開とするように設定値を最高感度点に設定
する。これは受信機の周波数特性により受信レベルが周
波数によって変化するから、周波数によって設定値をそ
の都度最適値に設定し直す。
The variable resistor 2 has an analog resistor to prevent noise from being output to the audio signal line when there is no received signal.
The set value is set to the highest sensitivity point so that the switch 1 is opened. Since the reception level changes depending on the frequency due to the frequency characteristics of the receiver, the set value is reset to the optimum value each time depending on the frequency.

【0013】そこでCPU5は、可変抵抗器2による設
定値を受信信号の周波数データをもとに周波数毎にメモ
リ6に格納する。格納データは次回の受信機の運用にお
いて、受信信号の周波数データをもとに周波数に対応し
た格納した設定値を読み出し、受信レベル値と比較す
る。
The CPU 5 stores the set value of the variable resistor 2 in the memory 6 for each frequency based on the frequency data of the received signal. As for the stored data, in the next operation of the receiver, the stored set value corresponding to the frequency is read out based on the frequency data of the received signal and compared with the received level value.

【0014】このように受信レベルと比較する設定値は
メモリ6に格納されているので、受信機の運用におい
て、可変抵抗器2により設定値を最適値にいちいち設定
する必要がなく、CPU5はメモリ6から設定値データ
を読み出して受信レベルと比較しスケルチ制御信号を出
力できる。また受信信号の周波数が変化しても、メモリ
6に格納したデータは周波数データをもとに周波数毎に
設定値を格納してあるので、CPU5は受信信号の周波
数に対応した設定値データを読み出すことができる。こ
れにより周波数が変化しても常に最適の設定値をもって
受信レベルと比較でき、比較信号によるアナログ・スイ
ッチ1の閉/開制御が適切に行なわれ、常にオーディオ
信号ラインの雑音出力を抑制することができる。
Since the set value to be compared with the reception level is stored in the memory 6, it is not necessary to set the set value to the optimum value by the variable resistor 2 in the operation of the receiver. The squelch control signal can be output by reading the set value data from No. 6 and comparing it with the reception level. Even if the frequency of the received signal changes, the data stored in the memory 6 stores the set value for each frequency based on the frequency data, so the CPU 5 reads the set value data corresponding to the frequency of the received signal. be able to. Thus, even if the frequency changes, the reception level can always be compared with the optimum set value, and the closing / opening control of the analog switch 1 is appropriately performed by the comparison signal, so that the noise output of the audio signal line is always suppressed. it can.

【0015】[0015]

【発明の効果】以上のように本発明によれば、周波数特
性によるスケルチ回路の周波数毎の設定値の設定が不要
となり、オペレータは設定作業に煩らわされずに受信機
の運用が出来る効果がある。
As described above, according to the present invention, there is no need to set a set value for each frequency of the squelch circuit based on the frequency characteristics, and the operator can operate the receiver without bothering the setting work. There is.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の回路構成図。FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

【図2】従来のスケルチ回路構成図。FIG. 2 is a configuration diagram of a conventional squelch circuit.

【符号の説明】[Explanation of symbols]

1…アナログ・スイッチ、2…可変抵抗器、3,4…ア
ナログ・ディジタル変換器、5…CPU、6…メモリ。
1 ... Analog switch, 2 ... Variable resistor, 3,4 ... Analog to digital converter, 5 ... CPU, 6 ... Memory.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 受信機のオーディオ信号を受信レベルに
応じてスケルチ制御するスケルチ制御回路において、オ
ーディオ信号の受信レベルを設定値と比較してスケルチ
制御信号を出力するCPUと、該CPUによって、受信
信号の周波数データをもとに周波数毎に上記受信レベル
と比較する設定値を格納するとともに読み出されるメモ
リとを設けたことを特徴とする受信機のスケルチ制御回
路。
1. A squelch control circuit for squelch controlling an audio signal of a receiver according to a reception level, a CPU for comparing a reception level of the audio signal with a set value and outputting a squelch control signal, and A squelch control circuit for a receiver, comprising: a memory for storing a set value to be compared with the reception level for each frequency based on frequency data of a signal and reading the set value.
JP20212696A 1996-07-31 1996-07-31 Squelch control circuit for receiver Pending JPH1051328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20212696A JPH1051328A (en) 1996-07-31 1996-07-31 Squelch control circuit for receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20212696A JPH1051328A (en) 1996-07-31 1996-07-31 Squelch control circuit for receiver

Publications (1)

Publication Number Publication Date
JPH1051328A true JPH1051328A (en) 1998-02-20

Family

ID=16452402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20212696A Pending JPH1051328A (en) 1996-07-31 1996-07-31 Squelch control circuit for receiver

Country Status (1)

Country Link
JP (1) JPH1051328A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6286906B1 (en) 1999-03-25 2001-09-11 Nissan Motor Co., Ltd. Balance weight

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6286906B1 (en) 1999-03-25 2001-09-11 Nissan Motor Co., Ltd. Balance weight

Similar Documents

Publication Publication Date Title
JPH10513017A (en) Differential feedforward amplifier power control for wireless receiver systems
KR0179968B1 (en) Sound signal output circuit and the method
JP2008535396A (en) Method and apparatus for dynamic gain and phase compensation
US5394476A (en) Volume control device
CA1302296C (en) Muting circuit in a digital audio system
JPH1051328A (en) Squelch control circuit for receiver
JP2940595B2 (en) Receiver with antenna switch
CA2053124C (en) Speech detection circuit
JP3116312B2 (en) Squelch circuit
JP3624241B2 (en) Method and apparatus for improving broadband detection of tones
JP4042328B2 (en) High frequency signal receiver
KR940000095B1 (en) Receiving signal agc circuit and method
JP3780169B2 (en) Voice squelch circuit
JPH0795772B2 (en) Signal sound detector
KR100418754B1 (en) A wireless controlled locking device using DTMF
JPH09326712A (en) Squelch circuit, its method and radio equipment
JP2865431B2 (en) Sound correction device
JPH1041835A (en) Squelch circuit for radio receiver
JP3304153B2 (en) Data waveform shaping circuit
JP4413397B2 (en) FM radio squelch circuit
JP3187261B2 (en) Filter circuit
JPH0733471Y2 (en) Diversity receiver
JP3128473B2 (en) Radio receiver
JPH0210680Y2 (en)
JP2555131Y2 (en) Squelch equipment